A strong Wi-Fi evolution path

WiFi evolution path is as following[41] :

802.11ac Technology Overview

5 GHz supported

Even wider channels (80 MHz and 160 MHz)

Higher order modulation (256-QAM)

Beam forming (explicit)

Backwards compability with 11a/b/g/n [16]

80 MHz is contiguous and 4.5x faster than 20 MHz

160 MHz can be either contiguous or in two non-contiguous

80 MHz slices

Channel Allocations

Wave 2

What will wave 2 802.11ac deliver?

MU-MIMO: Transmit data to multiple devices simultaneously

VHT160 : Doubles max data rate[16] Type Data Rate (Mbps)

11n 3x3 HT40 450

11ac 3x3 VHT80 1300

11ac 4x4 VHT160 3467

802.11ac: Up to 3x increase in throughput per stream

3x more in the future with MU-MIMO[41] :

Sub-carriers

OFDM subcarriers used in 802.11a, 802.11n and

802.11ac [16]

QAM constellations

Constellation diagrams for 16-, 64-, 256-QAM [16]

Data Rate

11n and 11ac data-rate Table[8]

802.11ac: Higher data rates at all ranges

With the identical throughput, 802.11ac has longer

transmission distance than 802.11n[41].

Block Diagram

Block diagram[16] :

DAC

A Digital-to-Analog converter(DAC) generates the

sampled output using the sampling clock from the

synthesizer or clock distribution chip.

Hence, the sampling clock quality is direct correlation

of the sampled DAC output performance[17].

Besides, due to the limited number of bits in a practical

DAC, there will be quantization noise, which is not

affected when the TX power is reduced[16]

DAC

Clock signal with high Noise Spectrum Density(NSD) in

spectrum turns to waveform with jitter, and vice

versa[17].

DAC

NSD in spectrum (jitter in waveform) leads to EVM issue

due to phase error.

In addition, it leads to Adjacent Channel Power

Ratio(ACPR) issue as well[19].

Am

plit

ud

e

Adjacent

Channel

Channel

Separation

frequency Phase noise

DAC

DAC can be seen as a clock divider plus a mixer. The

clock and its noise enter the divider together, and then

the divider output mixes with signal source to form the

DAC output[17].

DAC acts like a divider, dividing the clock frequency

and therefore lowers the clock phase noise.

DAC

The following equation illustrates how clock noise

performance is improved by DAC[17].

DAC

According to the equation, we know :

The lower the clock NSD is, the lower DAC output NSD will

be.

The lower DAC output frequency is, the lower DAC output

NSD will be.

The higher clock frequency is, the lower DAC output NSD

will be.

DAC

According to measurement, it proves again that the

lower DAC output frequency is, the lower DAC output

NSD will be.

Besides, the DAC output noise should be a

combination of clock noise and DAC intrinsic noise.

DAC

According to measurement, it proves that the lower

DAC output frequency is, the lower DAC intrinsic noise

will be[17].

DAC

SNR can be derived as:

Take 256 QAM for example, the EVM requirement is

2.5%, then SNR is 32 dB.

DAC output NSD limit can be derived as:

Hence, we take 256 QAM(SNR = 32 dB), BW = 80 MHz

for example, the DAC output NSD should NOT be larger

than : -32 – 79 = -111(dBc/Hz)

Besides, in order to meet EVM requirement, the wider

the bandwidth is, the lower the DAC output NSD should

be. Because wider bandwidth contributes to more

stringent DAC output NSD requirement.

DAC

As mentioned above, the relationship between DAC

output NSD and clock NSD is :

Thus, the clock NSD should NOT larger than -97(dBc/Hz)

Assuming fclock is 983.04 MHz, and fDAC_Output is 200 MHz,

we are capable of deriving clock NSD requirement as :

DAC

As mentioned above, NSD in spectrum (jitter in

waveform) leads to EVM issue due to phase error.

The measurement is as following :

From the measurement, it proves again that the higher

the clock jitter is, the higher the EVM will be[17].

DAC

The influence of peaking NSD and average NSD is

shown below. If the clock NSD is lower than the

predicted value, then the DAC EVM specification can be

met. If there is some peaking in clock phase noise

curve, then the DAC EVM may fluctuate and the

fluctuation depends on the peaking power[17].

DAC

With channel bandwidth = 80 MHz, the spectrum mask

specification is as following:

A (0 dBc, @ 39 MHz offset)

B (20 dBc, @ 41 MHz offset)

C (28 dBc, @ 80 MHz offset)

D (40 dBc, @ 120 MHz offset)

Basically, spectrum mask is just wideband ACPR, which

is related to NSD of DAC output and clock.

DAC

Hence, the NSD of DAC output and clock should be as

low as possible to meet spectrum mask specification.

fclock fDAC DAC

DAC

B (20 dBc, @ 41 MHz offset) Take point B for example, the NSD

of DAC output can be derived as :

With channel bandwidth = 80 MHz, assuming the ACPR

requirement is 70 dBc, then

-70 - 10*log(80MHz) = -149 dBc/Hz

Thus, @ 41 MHz from fDAC_output , the NSD of DAC output

should NOT be larger than -149 dBc/Hz to meet

Spectrum mask requirement.

DAC

B (20 dBc, @ 41 MHz offset) Again, take point B for example,

the NSD of clock can be derived

as :

Thus, @ 41 MHz from fClock , the NSD of clock should

NOT be larger than -135 dBc/Hz to meet Spectrum mask

requirement.

OFDM

Orthogonal Frequency Division Multiplexing, OFDM, is

frequently referred to as multi-carrier modulation

because it transmits signals over multiple subcarriers

simultaneously.

It is based on the Fast Fourier transform (FFT) concept,

which allows the multiple subcarriers to overlap yet

maintain their integrity[20].

OFDM

Over a long transmission distance, the signal passes

through a variety of physical mediums. As a result, the

actual received signal contains the direct path signal

overlaid with signal reflections of smaller amplitudes.

This is called multipath.

OFDM

Multipath makes received signal slightly distorted. The

direct path signal arrives as expected, but slightly

attenuated reflections arrive later. These reflections

interfere with subsequent symbols transmitted along

the direct path.

Thus, multipath causes Inter Symbol Interference(ISI)

because the reflections will make up a significant

percentage of the symbol period. This problem

becomes much more significant at high symbol

rates[21].

OFDM

OFDM systems mitigate this problem by utilizing a

longer symbol period, which doesn’t sacrifice throughput by utilizing multiple sub-carriers per

channel[21].

OFDM

In addition, high throughput are achieved in OFDM due

to precise carrier spacing and exact amplitude and

phase settings for each individual carrier constellation.

This is accomplished using computational modulation

schemes rather than traditional analog modulation[20].

Given the fact that the multiple subcarrier spectrum can

overlap as long as they are orthogonal, Spectrum

efficiency can be improved. As mentioned above, the

modern OFDM systems are FFT/IFFT based[34].

RX

OFDM

Spectrum of FFT based OFDM Signal (Digital)[34] :

OFDM

However, in terms of RF section, OFDM design face

several key issues, including power consumption,

linearity, phase distortion and phase noise. These

issues will impact throughput.

OFDM

One of the most difficult engineering concerns in the

RF section of is handling very large peak-to-average

power ratios (PAPRs). A peak in the signal power will

occur when all, or most, of the sub-carriers align

themselves in phase. In general, this will occur once

every symbol period[20-22].

Average Power

Peak Power

Time

OFDM Symbol Power

OFDM

The value of the PAPR is directly proportional to the

number of carriers, and is given by:

where N is the number of carriers[20].

Besides, the more number of subcarriers, the wider the

bandwidth will be. In other words, PAPR is proportional

to bandwidth as well. 802.11ac

Bandwidth Number of

subcarriers

(IFFT Size)

20 MHz 64

40 MHz 128

80 MHz 256

160 MHz 512

OFDM

For example, for the 802.11a OFDM standard, if the

phases of all 52 carriers line up simultaneously during a

symbol period, the PAPR will be 17 dB, let alone

802.11ac because the higher order modulation leads to

higher PAPR[20].

If the peak power is larger than PA’s compression point, the signal will be clipped, resulting in distortion and

nonlinear effect[23].

OFDM

Given the fact that the clipped waveform is like square

waveform, which is rich in harmonics[42].

Thus, in terms of waveform, it illustrates that why

clipping distortion produces harmonics. The more

serious the clipping distortion is, the larger harmonics

there will be.

OFDM

In order to achieve the desired linearity at the PA output,

the PA must be operated with significant backoff from

its saturation point. The larger the PAPR is, the more

backoff should be[24].

OFDM

With desired linearity, in terms of PA’s efficiency, the more backoff leads to lower output power, which

results in lower efficiency.

Maximum power efficiency of a Class B PA is 78.5%.

Nevertheless, when accounting for a signal having a

PAPR of 10 dB, this efficiency drops to 7.85 %[20]

OFDM

Thus, for 802.11ac, due to its wide bandwidth and high

order modulation, PAPR is large, and this leads to high

linearity requirement and high DC power

consumption[20].

High DC power consumption leads to thermal issue,

which aggravates PA’s linearity and results in EVM and spectrum mask issue[25].

PA

OFDM

Therefore, add GND vias in thermal pad as many as

possible to mitigate thermal issue, thereby improving

RF performance.

Linearity Concerns

OFDM modulation is also very sensitive to the inter-

modulation distortion (IMD) that results from mild non-

linearity in the RF section. Because the subcarriers are

equally spaced, the third-order IMD will appear exactly

on top of another carrier.

Power

Frequency

OFDM Carriers

IMD3 interference

These IMD interference will contribute to a noise-like

cloud surrounding each constellation point[20].

Linearity Concerns

For higher-level modulations, these constellation

clouds can contribute to an increase in bit errors for

each carrier. Even a modest increase in bit error rate

(BER) for each carrier can result in a dramatic increase

in the cumulative error rate over a packet.

As shown below, the larger the IIP3 is, the lower IMD3

interference will be[26].Thus, in an OFDM design,

enough linearity is necessary [20].

Linearity Concerns

In terms of TX performance, a noise-like cloud

surrounding each constellation point leads to EVM

issue.

In terms of RX performance, an increase in symbol

error rate decreases SNR, thereby aggravating

sensitivity.

Linearity Concerns

For the receiver, the power levels are much lower but

the linearity requirement is even more challenging. This

arises from the possible presence of adjacent

channel interference from other, independent but

closely located, WLAN networks[20].

WiFi

Terminal

WiFi

Terminal

WiFi

Terminal

RX

Desired TX

Undesired TX

Because the possibility of the interfering transmitter

location being nearer than the desired transmitter, the

adjacent channel blocker is often received with a

significantly stronger signal power level than the

desired channel. Power

Frequency

Desired TX

Undesired TX

Linearity Concerns

The strong blocker may saturate LNA, leading to gain

reduction. The stronger the blocker is, the more gain

reduction will be[27].

Gain

Blocker Power

Linearity Concerns

According to Friis Formula :

lower gain leads to higher noise figure, thereby

aggravating sensitivity[27].

Gain

Frequency

Noise Figure

Linearity Concerns

But, actually, an infinite gain increment does NOT lead

to an infinite noise figure reduction.

Besides, an infinite gain increment does lead to an

infinite IIP3 reduction. As mentioned above, with

blocker, poor linearity leads to poor sensitivity as

well[28].

LNA Gain V.S Cascade Noise Figure & IIP3

IIP3

NF

Linearity Concerns

Thus, in order to achieve desired sensitivity, the

linearity is the larger the better.

But the gain is neither the larger the better nor the

smaller the better. It is the more exact the better.

LNA enabled Bypass Mode

Gain (dB) 12 -7

IIP3 (dBm) 4 20

Take SKYWORKS SKY85608-11 for example, the gain

and IIP3 are 12 dB and 4 dBm respectively while

activating LNA.

With bypass mode, the IIP3 increases to 20 dBm. It

proves again that LNA’s gain is a compromise between

linearity and noise figure[29].

Phase Noise

By definition, multi-carrier modulation requires very

close proximity of the adjacent individual carriers. This

is possible due to the relatively low data rate for each

carrier.

However, upon down-conversion in the receiver, any

phase noise associated with the local oscillator (LO)

synthesizer will be superimposed onto the low data rate

modulation[20].

Frequency

Power

LO with phase noise

OFDM Carriers

Frequency

Power

Down-converted

OFDM Carriers

With LO phase noise

Phase Noise

As a result, making LO phase noise level sufficiently

low becomes extremely important to achieve low BER

in an OFDM design[20].

Otherwise, as in the case of IMD, a modest increase in

the BER for each carrier can result in a dramatic

increase in the symbol error, thereby aggravating

sensitivity[20].

Phase Noise

Take Broadcom BCM4359 for example, these areas

marked red should be kept out, because these areas are

VCO related circuits[30].

Otherwise, the parasitic effect will aggravate

the phase noise.

Phase Noise

The phase noise of an on-chip VCO will dominate, due

to the low Q of its spiral inductors[20,31].

Nevertheless, the phase noise of crystal(XTAL) also

matters. With poor phase noise of XTAL, the VCO phase

noise aggravates as well[20].

BCM4359

XTAL, 37.4 MHz

XTAL with phase noise

Phase Noise

Besides, we ought to care the power traces related to

VCO, PLL, LO, and synthesizer very much because they

affect phase noise as well[32].

According to the formula below, the lower the IDD is, the

larger the phase noise will be. Thus, the IR drop should

be as low as possible.

Phase Noise

If the input signal is interfered by high frequency noise,

the output signal will has spurs[32].

Hence, keep noisy traces away from XTAL and VCO

power trace.

In addition, reserve bypass capacitor for these power

pins and the location of bypass capacitor should be as

close to chip as possible.

Phase Noise

If the voltage of VCO has large ripple, the phase noise

aggravates as well. Thus, as in the case of bypass

capacitor, reserve decoupling capacitor for these power

pins and the location of decoupling capacitor should be

as close to chip as possible[32].

Time

Voltage Ripple

As shown below, the larger the decoupling capacitor

value is, the lower phase noise will be.

Phase Noise

As mentioned above, the poor power supply

contributes to large phase noise and spurs. Thus, we

can use a clean external power supply to check the root

cause of poor phase noise[32].

Offset Frequency(Hz)

Ph

as

e N

ois

e (

dB

c/H

z)

Poor Power Supply

Clean Power Supply

PA

Constant envelope signal : shape of spectrum

unchanged.

Constant Envelope

Variable Envelope

Variable envelope signal : shape of spectrum manifest

as noise like shoulders, known as spectral regrowth.

For every one 1 dB drop in TX power, the regrowth

drops by 3 dB(2 dB net)[16].

PA

Given the fact that OFDM has high PAPR, the peaks in

the OFDM signal cause distortions[16].

Thus, as mentioned above, the PA must be operated

with significant backoff from its saturation point to

achieve desired linearity[33].

PA Non-linearity

PCIe

According to Shannon Theorem :

We know that channel capacity is proportional to SNR.

SNR(dB)

Data Rate

(Mbps/MHz)

In terms of TX, the higher SNR is, the lower EVM will be.

SNR(dB)

EVM

(%)

SNR(dB)

BER

(%)

In terms of RX, the higher SNR is, the lower BER will be,

which leads to better sensitivity.

PCIe

Thus, both lower EVM and better sensitivity will lead to

higher throughput.

However, take Broadcom BCM4359 for example, the PCIe

interface between BCM4359 and Baseband chip affects

throughput as well. So we also need to take care of it

circumspectly.

BCM 4359

PCIE _ REFCLK _ P

PCIE _ REFCLK _ N

PCIE _ T X _ N

PCIE _ RX _ P

PCIE _ RX _ N

PCIE _ T X _ P

Baseband Chip

When placing series components on these lines, select

component sizes such that pads have a width similar to the

PCIe line. Doing this will reduce reflections from impedance

mismatches.

PCIe

As shown above, there are three PCIe differential pairs, and

their impedance should be 100Ω.

In each pair, match the lengths of each pair member to less

than 30 mils.

Impedance Discontinuity

Reference

[1] CHALLENGES IN DESIGNING 5 GHZ 802.11AC WIFI POWER AMPLIFIERS, RFMD

[2] WCN3660 EVM Degradation Issue Technical Note, Qualcomm

[3] SE5516A: Dual-Band 802.11a/b/g/n/ac WLAN Front-End Module, SKYWORKS

[4] 802.11ac Technology Introduction White Paper, RHODE & SCHWARZ

[5] WLAN IEEE 802.11ac Wide bandwidth high speed 802.11ac technology and testing,

RHODE & SCHWARZ

[6] ACPF-7024 ISM Bandpass Filter (2401 – 2482 MHz), AVAGO

[7] WCN36x0(A) RF Matching Guidelines, Qualcomm

[8] MCS Index for 802.11n and 802.11ac Chart

[9] Sources of Error in IQ Based RF Signal Generation

[10] Integration Aids 802.11ac Mobile Wi-Fi Front Ends

[11] Mini filters for multiband devices, TDK

[12] QCA61x4-1 RF Matching Guidelines, Qualcomm

[13] QCA61x4, QCA937x, QCA65x4 Design Guidelines/Training Slides, Qualcomm

[14] QCA6164-1 with External 2.4G and 5G RFFM Reference Design Example, Qualcomm

[15] WLAN/BT/FM Training Using WCN3660, WCN3660A, or WCN3680, Qualcomm

[16] 802.11ac Wi-Fi Fundamentals

[17] Effects of Clock Noise on High-Speed DAC Performance, Texas Instruments

[18] DIGITAL-TO-ANALOG CONVERTER ICs, Analog Devices

[19] Optimizing the Stimulus to Maximize System Performance

[20] The OFDM Challenge

[21] OFDM and Multi-Channel Communication Systems, National Instruments

[22] 4G Broadband-what you need to know about LTE

[23] Wideband Digital Pre-Distortion Modeling for LTE-Advanced, Keysight

[24] Linearize Power Amps With RF Predistortion

[25] Wideband High Dynamic Range Limiting Amplifier

[26] IMD Measurement with E5072A ENA Series Network Analyzer, Keysight

[27] SAW-less Direct Conversion Receiver Consideration

[28] Sensitivity or selectivity -- How does eLNA impact the receriver performance

[29] SKY85608-11: 5 GHz, 802.11ac Switch/Low-Noise Amplifier Front-End, SKYWORKS

[30] BCM4359 Printed Circuit Board Layout Guidelines, Broadcom

[31] Designing A Low-Noise VCO

[32] GPS RF FRONT-END CONSIDERATIONS

[33] EXAMPLE: 802_11a_RX_Sensitivity, National Instruments

[34] Fundamentals of OFDM Communication Technology

[35] ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise?

[36] A New Leap Towards True Software-Defined Radio

[37] What are Anti-Aliasing Filters and Why are They Used?, National Instruments

[38] Switched-Capacitor Filters Beat Active Filters at Their Own Game

[39] Agile ADCs Enable Digital Cellular Receivers

[40] NAVIGATE THE AFE AND DATA-CONVERTER MAZE IN MOBILE WIRELESS

TERMINALS, MAXIM

[41] The Wi-Fi Evolution An integral part of the wireless landscape, Qualcomm

[42] VLSI Testing Lectures 13 and 14: Radio Frequency (RF) Testing