Engineering Science and Technology, an International Journal 19 (2016) 1416–1423

Contents lists available at ScienceDirect

Engineering Science and Technology,an International Journal

journal homepage: www.elsevier .com/locate / jestch

Full Length Article

8051 microcontroller to FPGA and ADC interface design for high speedparallel processing systems – Application in ultrasound scanners

http://dx.doi.org/10.1016/j.jestch.2016.04.0042215-0986/� 2016 Karabuk University. Publishing services by Elsevier B.V.This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

⇑ Corresponding author at: Room No. 299, 2nd Block, Centre for Bio-MedicalEngineering, Indian Institute of Technology, New Delhi, India.

E-mail address: bmz108120@cbme.iitd.ac.in (J. Jean Rossario Raj).

Peer review under responsibility of Karabuk University.

J. Jean Rossario Raj a,⇑, S.M.K. Rahman a,b, Sneh Anand a,b

aCenter for Bio-Medical Engineering, Indian Institute of Technology, New Delhi, IndiabBio Medical Engineering Unit, All India Institute of Medical Sciences, New Delhi, India

a r t i c l e i n f o

Article history:Received 17 January 2016Revised 28 March 2016Accepted 20 April 2016Available online 5 May 2016

Keywords:ADCFPGAMicrocontrollerSerial peripheral interfaceUltrasound scanner

a b s t r a c t

Microcontrollers perform the hardware control in many instruments. Instruments requiring huge datathroughput and parallel computing use FPGA’s for data processing. The microcontroller in turn configuresthe application hardware devices such as FPGA’s, ADC’s and Ethernet chips etc. The interfacing of thesedevices uses address/data bus interface, serial interface or serial peripheral interface. The choice of theinterface depends upon the input/output pins available with different devices, programming ease andproprietary interfaces supported by devices such as ADC’s. The novelty of this paper is to describe theprogramming logic used for various types of interface scenarios from microcontroller to differentprogrammable devices. The study presented describes the methods and logic flowcharts for differentinterfaces. The implementation of the interface logics were in prototype hardware for ultrasoundscanner. The internal devices were controlled from the graphical user interface in a laptop and the scanresults are taken. It is seen that the optimum solution of the hardware design can be achieved by using acommon serial interface towards all the devices.� 2016 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC

BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction

Field programmable gate arrays (FPGA’s) are used in systemsthat require huge data throughput and parallel computing [1,2].Microcontrollers offer major advancement as an internal andexternal control [3]. Microcontrollers control majority of the inter-nal devices in a typical circuit board. Moreover, majority of theapplication specific chips have built-in interfaces controlledthrough the microcontroller. Microcontrollers come with an uni-versal serial bus (USB) interface through which it is interfaced withan external device such as a host computer [4]. The interfacing ofmicrocontroller through USB from host computer using MATLABprogramming tool is studied in [5]. This provides unique advantageof integration of hardware and software [6,7]. The programming ofthe microcontroller is performed in traditional languages such as‘C’ or ‘C++’ [8,9]. Object oriented programming languages providebetter reusability and flexibility in the firmware and software ofsuch systems [10]. FPGA codes are written in VHSIC (very high-speed integrated circuit) hardware description language (VHDL).

Microcontrollers and FPGA’s have wide range of application inthe area of instrumentation [11,12].

A study was carried out in the development of a prototype hard-ware for ultrasound scanner which required parallel processingand external control [13]. A block schematic of the microcontrollerinterfacing in the prototype hardware is shown in Fig. 1, where theinterface towards different devices such as analog to digital con-verter (ADC), FPGA’s, gigabit Ethernet controller (media access con-trol device or MAC), and gigabit Ethernet physical layer device(PHY) is shown. The microcontroller interface can use address/databus interfacing which is the simplest method of interfacing as dataread and write operations can be done in the byte form [14]. How-ever, this is suitable only when sufficient number of hardware pinsis available in the interfacing devices. Second method uses a serialperipheral interface (SPI) which uses serial data processing for bothdata and address bytes [15]. This requires serialization of the dataand address that makes the programming more complex and occu-pies more memory space. The third method uses serial interfacethat uses common serial pin for both read and write operationswhich is further more complex. This method requires additionalbyte to identify whether the intended operation is read or write.

In certain cases, the application specific chip manufacturers likeADC, dictates the type of interface to be used for the microcon-troller interfacing. Hence, this aspect also needs consideration for

Micro controller

USB Interface

Rx FPGA

ADC

SPI Interface

Serial Interface

Tx FPGA

Gigabit Ethernet Phy

Address / Data bus Interface

MDIO Interface

Gigabit Ethernet

Controller

Inline control

Fig. 1. Block schematic of the experimental setup.

Microcontroller C8051F340

FPGA Spartan 3E

XC3S250E_208

8 Bit address Bus

8 Bit Data Bus

READ

WRITE

CHIP SELECT

FPGA Program to read/write from MC

MC Program to Read / Write to FPGA

Fig. 2. Block schematic of the microcontroller – FPGA address/data bus interfacing.

Assign Address Pins with Address Byte

Chip Select = 0

Configure Port mode = OUT

e.g. P4MDOUT=0xFF

Assign Data to data pins

Write Pin = 0

Wait

Write Pin = 1

Chip Select = 1 Address = 0xFF

Data = 0xFF

Start

End

Start

Assign Address Pins with Address Byte

Chip Select = 0

Read Pin = 0

Configure Port mode = IN

e.g. P4MDOUT=0x00

Read Data from data pins

Read Pin = 1

Chip Select = 1 Address = 0xFF

Data = 0xFF

End

Fig. 3. Flow chart of microcontroller firmware for address/data bus interfacing –Write and Read operations.

Start

End

Continue to Next Address

Read Register-0

& Move Data to Data Bus

Continue to Next Address

Read Data Bus & Move Data to Register-0

Yes Yes Yes

No No

Yes

No No

Write Pin = 0 & Chip Select = 0

Read Pin= 0 & Chip Select = 0

Address = 0 Address = 0

Fig. 4. Flow chart of FPGA program for address/data bus interfacing.

Microcontroller C8051F340

Rx FPGA Spartan 3E

XC3S250E_208

MOSI

MISO

CHIP SELECT

FPGA Program to read/write from MC

SLAVE

MC Program to Read / Write to FPGA

MASTER

CLOCK

Fig. 5. Block schematic of the microcontroller – FPGA SPI bus interfacing.

J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423 1417

interfacing. When multiple devices are programmed through acommon programming bus, chip select (CS) is used to decide thedevice to be programmed. In such case, signals for the input/output(IO), clock etc., are common across all the devices.

The novelty of this paper is a study on the different methodsused for interfacing between the microcontroller and parallel pro-cessing devices such as FPGA’s and data converters. The paper alsocompares and studies the best algorithm for different implementa-tion conditions.

2. Materials and methods

2.1. Choosing of the microcontroller and FPGA

The microcontroller used was C8051F340 from silicon laborato-ries. It operates at a maximum speed of 48 MHz with 4k ofon-board random access memory (RAM) and 64k flash memory.The microcontroller has integrated USB receiver and USBcontroller. It has 48 IO pins configured as five IO buses with eightIO’s each. The microprocessor in the ultrasound scanner prototypeinterfaces with a bank of ADC’s and FPGA’s. The microprocessorfirmware is written in C language [16]. One IO bus is used as theprogramming header for programming the microcontrollerthrough the USB from the host computer. The transfer of firmwareto the microcontroller is through this header using the program-mer hardware of m/s silicon labs.

For logic emulation systems the FPGA provides faster computa-tion as compared to software simulation [17]. The logic designs arecustomised for high performance in different types of applications[18]. In multimode system, the FPGA’s yield significant hardwaresavings and provides generic hardware in [19]. In order to meetthe above requirements, Xilinx FPGA, Spartan 3E (XC3S500E_208)with the following specifications is chosen. The FPGA has 172 I/OPins and 216K Blocks of RAM. Low voltage differential signalling(LVDS) is used for interfacing with high voltage pulser and receiverchips. The speed of the IO Bus is 622Mbps, with EEPROM havingmaster–slave/JTAG (joint test action group) programming headers.

2.2. Microcontroller – FPGA interface using address/data bus

The microcontroller to transmit side FPGA (Tx-FPGA) interfacewas implemented using address/data bus method as shown inFig. 1. This method was chosen since the FPGA and microcontroller

1418 J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423

had sufficient number of IO pins i.e. 19 pins. Hence, to make theprogram logic simple, address/data bus method of interfacingwas used. The interconnection between the FPGA and the micro-controller used 8-bit address bus, 8-bit data bus, read, write andCS as shown in Fig. 2. The address bus is simplex i.e. from micro-controller to the FPGA whereas the data bus is duplex. The logic0 or low in read or write pin indicates that the proposed operationis read or write.

The flow chart of the microcontroller program for read andwrite operations of the microcontroller is given in Fig. 3. In thewrite operation, the data bus uses OUT mode where as in read

Clock = 0 MOSI = 0

Chip Select = 0

Start

Stop

Clock = 0 MOSI = 0

Chip Select = 1

FPGA Write – Address Byte

Read / Write Operation

FPGA Read – Data Byte

FPGA Write– Data Byte

Write

Read

FPGA Write – 01 Byte (Write indicator )

FPGA Write – Address Byte

FPGA Write – 00 Byte (Read indicator )

Fig. 6. Flow chart of microcontroller firmwa

Rising Edge of Clock

Count = 0

Read Data Bit from MOSI to LSB of logic

vector

Increment counter

Count >= 16

Count = 24

Read Operation

LSB=1, Read LSB=0, Write

No

Yes

Yes Yes

Yes

Yes

No No

No

No

No

Move laddress l

Move addresRegist

logic

RisingC

Move Mto M

Shift dve

Cou

Cou

Incrco

No

Count >= 8

Fig. 7. Flow chart of FPGA prog

operation, the data bus uses IN mode. This is configured usingthe P4MDOUT configuration depending upon the port being con-figured. CS is pulled low depending upon the device to be pro-grammed. Read or write pins are made active low dependingupon the read or write operation. The address byte is sent to theaddress bus pins. In case of write operation, data byte is also sentto the data bus pins whereas in read operation, data byte is readfrom the data bus pins.

The FPGA logic for the RW operations is presented in Fig. 4.FPGA logic waits for the CS pins to be active low. FPGA initiatesRW operation during the falling edge of the CS. When write pin

Count > 8

Count = 0

Increment counter

Next Bit = 0

MOSI = 0

MOSI = 1

Exit

FPGA Write Byte Sub Routine

Clock = 1

Clock = 0

Del

ay

No

Yes

No

Yes

Count > 8

Count = 0

Increment counter

Data = Data | 0

Data = Data | 1

Exit

FPGA Read Byte Sub Routine

Clock = 1

Clock = 0

Del

ay

No

Yes

MISO = 0

Yes

No

re for SPI bus interfacing towards FPGA.

Yes

ast byte to ogic vector

Move previous byte to address logic vector

Move last byte to Data logic vector

data from s location er to data vector

Edge of lock

SB of data ISO

ata logic ctor

nt = 0

nt = 8

ement unter

Move data from data logic vector to

address location register

Rising Edge of Clock

Yes

No Yes

ram for SPI bus interfacing.

Microcontroller

C8051F340 CLOCK

Data IO

ADC-1

ADC-2

ADC-3

ADC-4

Chip Select 1

Chip Select 2

Chip Select 3 Chip Select 4

Fig. 8. Block schematic of the microcontroller – ADC serial bus interfacing.

J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423 1419

goes to active low, FPGA reads the address & data from the address& data pins and moves data to the respective register location.Similarly, in the read operation, when the read pin goes to activelow, FPGA reads the address from the address pins. The data fromthe corresponding address location register is placed in the databus pins.

2.3. Microcontroller – FPGA interface using SPI bus

In the receive side FPGA (Rx-FPGA), sufficient IO pins were notavailable. Hence, address/data bus type of interfacing followed inTx-FPGA was not used. Here, serial interface using SPI bus wasused. The block schematic of the microcontroller to Rx-FPGA inter-face is given in Fig. 5. In this method, the microcontroller is actingas the master and the Rx-FPGA is acting as the slave. The serialaddress/data path frommicrocontroller to FPGA is referred as mas-ter out slave in (MOSI) and from FPGA to microcontroller is

Count = 0

Increment counter

Return

Port Mode = IN

Data IO = 1

Data = Data | 1

Clock = 0

Delay

Clock = 1

Delay

Count > 8

Microcontroller Read Byte Sub Routine

No

No

Yes

Yes

Data = Data | 0

Chip Select

Stop

MicrocontrolWrite – Addre

Byte

Read / Writ

MicrocontrolWrite – Data B

MicrocontrolRead – Data B

Chip Select

Start

Composite Flow

MicrocontroWrite –

Read/Write F

Fig. 9. Flow chart of microcontroller firmware

referred as master in slave out (MISO). The other interface IO’sincludes the CS and the clock, which are supplied by the microcon-troller. The major challenge in SPI is to send and receive the data inserial format, i.e., bit by bit.

The microcontroller program flowchart for SPI is given in Fig. 6.An active low CS signal is used to identify the FPGA device to bewritten. The microcontroller uses the write byte, read byte, sub-routines of Fig. 6 for serial write, and read operations. The timeduration for toggling of the clock pin between the active low andactive high is controlled by the delay. In each clock, one bit ismoved to the MOSI pin during the write operation and one bit isread from the MISO pin during the read operation. This cycle iscontinued for 8 bits. In the read/write (RW) operation, one byteof RW flag is written to the FPGA indicating the type of operation.Further, in write operation, address and data bytes are writtenwhereas in read operation, address byte is written and data is readfrom the MISO pins.

The flow chart of the FPGA program is given in Fig. 7. When CSbecomes active low, FPGA reads from MOSI pin bit by bit duringthe rising edge of the microcontroller clock. When FPGA completesreading one byte, based on the byte flag value, it decides whetherthe operations is read or write. FPGA further reads the addressbyte. For read operation, FPGA uses a logic vector for temporarystorage of the address value. FPGAmoves the data from the registerat the address location to the MISO pin bit by bit. In write opera-tion, FPGA reads the next byte as well. FPGA moves the data valueto a temporary logic vector. Further FPGA writes the data value tothe register at the address location.

2.4. Microcontroller – ADC interface using serial bus

In the developed prototype of the ultrasound scanner, AD9272from M/s Analog Devices is used as the receiver which has thecomplete analog front end comprising of the low noise amplifier(LNA), variable gain amplifier (VGA), time gain compensation(TGC) and the ADC [20]. Each AD9272 comprises of eight channels.Four such AD9272’s are used in the design. The same data IO andclock from the microcontroller is used for all the four ADC’s. The

Count = 0

Increment counter

Return

Port Mode = OUT

Next Bit to be sent = 1

Data IO = 1

Data IO = 0

Clock = 0

Delay

Clock = 1

Delay

Count > 8

Microcontroller Write Byte Sub Routine

No

No

Yes

Yes

ler ss

e

ler yte

ler yte

chart

ller

lag

for Serial bus interfacing towards ADC’s.

Tx FPGA

Rx FPGA

Microcontroller

Receiver & ADC

Ethernet MAC

Ethernet PHY

Microcontroller Programming

header

Tx FPGA Programming

header

Transmit Pulsers

Fig. 10. Ultrasound scanner prototype hardware.

1420 J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423

chips are selected for command execution based on the CS. Theblock schematic of interconnection of microcontroller to the ADC’sis given in Fig. 8.

The flowchart of the microcontroller firmware for the interfacewith ADC’s is given in Fig. 9. The algorithm uses read byte andwrite byte sub-routines for RW operations respectively. Since thesame pin of the microcontroller is used for both send and receive,

Pulser channel enabling

ReadCommand Buttons Tx & Rx-FPGA configurations

Fig. 11. MATLAB GUI for configuratio

the port mode is changed to IN or OUT suitably. The sub-routinewrites or reads bit by bit for a complete byte using the IO pin. Inthe composite flowchart, RW flag is written first followed by theaddress, which gives an indication of the forthcoming operation.In case of read, the microcontroller reads the data byte or in caseof write, the microcontroller writes the data byte as per the logicof the sub-routine. A delay is given for performing the read or writeoperation. The operation is bit by bit.

3. Results and discussions

A prototype developed for the ultrasound scanner with USBinterface is shown in Fig. 10. The prototype has the silicon labora-tories C8051F340 microcontroller, Xilinx FPGA’s and ADC’s(AD9272) from analog devices. It has the microcontroller program-ming header as well as the FPGA programming headers. The pro-gramming of the microcontroller as well as the FPGA’s wasperformed through the headers. The prototype is connected tothe laptop graphical user interface (GUI) through the USB interface.

A GUI is developed usingMATLAB software for the configurationof different parameters of the devices. The GUI is shown in Fig. 11.Through this GUI, the different parameters of the FPGA’s and ADC’sare configured through themicrocontroller. The transmit frequency,pulse burst width, selection of the channels for the transducer exci-tation etc., are selected from the GUI. This configures the Tx-FPGAfor controlling these operations. This control from microcontrollerto the Tx-FPGA is through the address/data bus parallel interface.

ADC configuration

or Write Configuration Register Values

n of various scanner parameters.

Positive Pulse Trail of Excitation pulses

Negative Pulse Trail of Excitation pulses

Fig. 12. Output pulse waveform based on microcontroller FPGA control.

J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423 1421

A channel is selected as shown in Fig. 11. Configure FPGA command,transfers the HEX values to the microcontroller, which in-turnwrites the Tx FPGA registers through the parallel interface. TheTx-FPGA generates the required enable and excitation pulses. Theoutput pulse waveforms of the transmit section used for excitingthe ultrasound transducer array is shown in Fig. 12 showing the pos-itive and negative trail of high voltage pulses.

Similarly, AD9272 parameters like the LNA Gain, VGA Gain, AAFupper and lower cutoff frequencies, generation of test pattern etc.,

Data length UDP Pr

Fig. 13. Ethernet packets received from the prototype through micro

are controlled by programming the ADC’s through the microcon-troller as shown in Fig. 11. The control to the ADC is through serialinterface. In addition, the control to the Rx-FPGA is through SPIinterface. In addition, the start and stop of scan is controlled bythe configuration of the transmit and receive FPGA’s. Upon startof a scan, the Tx-FPGA, excites the selected channels. The Rx-FPGA receives the data from the ADC’s, convert the data into pack-ets and it is sent to the laptop over the Ethernet interface. The Eth-ernet packets received from the prototype is shown in Fig. 13.

The stop scan disables the channels and stop sending the Ether-net data packets. Thus by programming control through the micro-controller, the developed hardware is able to be controlled veryeffectively. The image was taken using a linear array transducerprobe working at 4 MHz. The receive beamforming, image andvideo processing algorithms like smoothening, sharpening, his-togram equalization etc., were performed in MATLAB graphicaluser interface. The receive beamforming required delay and sumalgorithm for the simultaneously received channels. The imageobtained with a lab phantom indicating the position of the inclu-sion as well as the depth of the phantom is given in Fig. 14.

The comparison of the three methods of microcontroller inter-facing is given in Table 1.

It is seen from Table 1 that serial interfacing is the most com-plex but most efficient in respect of pin usage and can be com-monly used across all the devices. Usually execution time is notan important criterion as the microcontroller interface is used formachine control. However, in case the microcontroller interfaceis used for data transfer, address/data bus configuration is pre-ferred. Hence, the actual type of interfacing required is to bedecided after weighing all the pros and cons of different interfacingmethods.

otocol Port 104 – ACR-NEMA

controller, FPGA control and captured in Wireshark application.

Reflection by Inclusion and inside air gaps

Reflection from bottom surface Phantom with inclusion

used for the evaluation

Fig. 14. Ultrasound image of a phantom with inclusion captured using the prototype.

Table 1Comparison of the microcontroller interfacing methods.

Address/data bus SPI bus Serial bus

Hardware pins required to interface Address: 8 Clock: 1 Clock: 1Data: 8 MOSI: 1 Data: 1Read: 1 MISO: 1 CS: 1Write: 1 CS: 1 Total: 3CS: 1 Total: 4Total: 19

Minimum active clock cycles to execute write instruction 1 RW flag: 8 RW flag: 2Data: 8 Data: 8Address: 8 Address: 8Total: 24 Total: 18

Minimum active clock cycles to execute read instruction Write address: 1 RW flag: 8 RW flag: 2Read data: 1 Write address: 8 Write address: 8Total: 2 Read address: 8 Read address: 8

Read data: 8 Read data: 8Total: 32 Total: 26

Execution time Fast Slow Slow

Reliability High Medium LowProgram simplicity Simple Medium Complex

Program volume and storage requirements in microcontroller and FPGA Less More Maximum

1422 J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423

4. Conclusion

The most important part of the development of the firmwarewas in the development of the interface programs that was suit-able for the interfaces supported by the application specific deviceas well as the availability of pins in the interface devices. Interfacedesign is the most important step in the use of general-purposedevices like microcontrollers and FPGA’s for application specificusages and control. The use of general-purpose microcontrollersand FPGA’s will make the hardware miniaturised and cost effective,which is an essential requirement for telemedicine application[21]. With the innovative approaches, it was possible to develophighly configurable, scalable and flexible FPGA based ultrasoundsystems [14,22]. The development of these interfaces helped inthe miniaturization of the hardware, thus enabling the hardwareto be used for telemedicine applications [1,23,24]. The FPGA basedimplementation has helped in the hardware to be operated at highframe rates of the order of 8000 [25,26].

One important conclusion arrived from the study after usingdifferent types of interfaces was that it is always preferable touse one type of interfacing across multiple devices. In this study

of microcontroller interface with FPGA’s and ADC’s, the best optionwill be to go for serial interface compatible with ADC for all typesof devices. This will have the following pros and cons. The micro-controller program becomes simple as single interface logic canbe used for all types of devices. This will also reduce the numberof microcontroller pins used. This will further reduce the numberof FPGA pins required for control also. However, the FPGA programwill be very complex and FPGA will require more storage space.But same FPGA interface code can be used for both the FPGA’s.

While developing the different interfaces the main aspect ofconsideration was the ease of programming. As a future step, allthe interfaces can be made common so that the microcontrollerprogram further simplifies even though there would be more com-plications in the FPGA program algorithms. This could furtherimprove the design architecture.

Acknowledgment

The authors thank Department of Science and Technology,Government of India for providing financial support for thisproject.

J. Jean Rossario Raj et al. / Engineering Science and Technology, an International Journal 19 (2016) 1416–1423 1423

References

[1] J. Raj, S. Rahman, S. Anand, Interfacing high frame rate data through ethernetwithout loss for tele-medical applications, in: 2015 International Conferenceon Signal Processing and Communication (ICSC), IEEE, New Delhi, 2015, pp.51–55, http://dx.doi.org/10.1109/ICSPCom.7150618.

[2] J.J.R. Raj, S. Rahman, S. Anand, Acquisition of lossless data in transient windowthrough Ethernet in high frame rate machines, in: 2015 2nd InternationalConference on Computing for Sustainable Global Development (INDIACom),IEEE, New Delhi, 2015, pp. 591–596.

[3] X.R. Zhao, F.Y. Ye, X.F. Qian, H.Y. Fu, W. Jin, Remote monitoring system forcommunication base based on short message, TELKOMNIKA Indones. J. Electr.Eng. 12 (2014) 459–467.

[4] B.-E. Byambasuren, M. Oyun-Erdene, S.-Y. Nam, D.-H. Kim, S.-M. Han, Design ofUSB-based high rate data communication for transcranial Doppler ultrasoundsystem, Int. J. Control Autom. 5 (2012) 97–106.

[5] J.R. Raj, S. Rahman, S. Anand, Microcontroller USB interfacing with MATLABGUI for low cost medical ultrasound scanners, Eng. Sci. Technol. Int. J. 19(2016) 964–969.

[6] A. Al-Dhaher, Integrating hardware and software for the development ofmicrocontroller-based systems, Microprocess. Microsyst. 25 (2001) 317–328,http://dx.doi.org/10.1016/S0141-9331(01)00124-7.

[7] S. Padmanaban, E. Kabalci, A. Iqbal, H. Abu-Rub, O. Ojo, Control strategy andhardware implementation for DC–DC boost power circuit based onproportional–integral compensator for high voltage application, Eng. Sci.Technol. Int. J. 18 (2015) 163–170, http://dx.doi.org/10.1016/j.jestch.2014.11.005.

[8] D.T. Martinez, T.U. Ganiron Jr., C.S. Lacsamana, Development of hardwareinterfacing system for visual C++, Int. J. Adv. Appl. Sci. 2 (2013) 201–204.

[9] M. Gökdag, A.T. Sözer, H. Abdullah, A web-based remote monitoring of solarenergy measurements and data storage system design for renewable energycenter of Karabuk University, Eng. Sci. Technol. Int. J. 16 (2013).

[10] F. Vahid, L. Tauro, An object-oriented communication library for hardware–software codesign, in: Proceedings of the Fifth International Workshop onHardware/Software Codesign, 1997. (CODES/CASHE’97), IEEE, 1997, pp. 81–86.

[11] J. Blahuta, T. Soukup, P. Cermák, D. Novák, M. Vecerek, Semi-automaticultrasound medical image recognition for diseases classification in neurology,in: Advances in Intelligent Analysis of Medical Data and Decision SupportSystems, Springer, 2013, pp. 125–133.

[12] N. Li, J. Guo, H.S. Nie, W. Yi, H.J. Liu, H. Xu, Design of embedded bio-impedanceanalyzer based on digital auto balancing bridge method, in: Applied Mechanicsand Materials, Trans Tech Publ, 2012, pp. 396–401. doi: 10.4028/www.scientific.net/AMM.135-136.396.

[13] J.J.R. Raj, S. Rahman, A. Sneh, Electronic hardware design for ultrasoundtransient elastography, Int. J. Eng. Sci. Technol. 4 (2012) 3700–3704.

[14] H.J. Hewener, H.-J. Welsch, H. Fonfara, F. Motzki, S.H. Tretbar, Highly scalableand flexible FPGA based platform for advanced ultrasound research, in: 2012IEEE International Ultrasonics Symposium (IUS), IEEE, 2012, pp. 2075–2080.

[15] L.L. Li, J.Y.He,Y.P. Zhao, J.H.Yang,Designofmicrocontroller standardSPI interface,in: Applied Mechanics and Materials, Trans Tech Publ, 2014, pp. 563–568.

[16] B. Mondal, M. Meetei, J. Das, C.R. Chaudhuri, H. Saha, Quantitative recognitionof flammable and toxic gases with artificial neural network using metal oxidegas sensors in embedded platform, Eng. Sci. Technol. Int. J. 18 (2015) 229–234,http://dx.doi.org/10.1016/j.jestch.2014.12.010.

[17] E.D. Moreno, F.D. Pereira, A modular multicore architecture in FPGAs forembedded critical applications, in: 2015 Ninth International Conference onComplex, Intelligent, and Software Intensive Systems (CISIS), IEEE, 2015, pp.364–371.

[18] M. Mielke, S. Hardt, A. Grünewald, R. Brück, FPGA implementation of anevolutionary algorithm based charge management for electric vehicles, in:2012 Proceedings of the 19th International Conference Mixed Design ofIntegrated Circuits and Systems (MIXDES), IEEE, 2012, pp. 559–563.

[19] S. Hauck, The roles of FPGAs in reprogrammable systems, Proc. IEEE 86 (1998)615–638, http://dx.doi.org/10.1109/5.663540.

[20] V. Vasudevan, P. Govindan, J. Saniie, Dynamically reconfigurable analog front-end for ultrasonic imaging applications, in: 2014 IEEE InternationalUltrasonics Symposium (IUS), IEEE, 2014, pp. 1924–1927.

[21] A. Chandra, S. Chattopadhyay, Design of hardware efficient FIR filter: a reviewof the state-of-the-art approaches, Eng. Sci. Technol. Int. J. (2015).

[22] E. Boni, L. Bassi, A. Dallai, F. Guidi, A. Ramalli, S. Ricci, J. Housden, P. Tortoli, Areconfigurable and programmable FPGA-based system for nonstandardultrasound methods, IEEE Trans. Ultrason. Ferroelectr. Freq. Control 59(2012) 1378–1385, http://dx.doi.org/10.1109/TUFFC.2012.2338.

[23] G.-D. Kim, C. Yoon, S.-B. Kye, Y. Lee, J. Kang, Y. Yoo, T.-K. Song, A single FPGA-based portable ultrasound imaging system for point-of-care applications, IEEETrans. Ultrason. Ferroelectr. Freq. Control 59 (2012) 1386–1394, http://dx.doi.org/10.1109/TUFFC.2012.2339.

[24] J.J.R. Raj, S. Rahman, S. Anand, Acquisition of high frame rate ultrasound datathrough Ethernet for telemedicine applications, Int. J. Basic Appl. Biol. 2 (2014)28–33.

[25] J.J.R. Raj, S. Rahman, S. Anand, An embedded system for elasticitymeasurement using ultrasound waves, in: Proceedings of DIGNATE 2014:ETEECT 2014, New Delhi, 2014, pp. 38–43.

[26] J.J.R. Raj, S. Rahman, S. Anand, Application of a novel software algorithm forinformation reduction in high frame rate ultrasonography, Int. J. Comput. Appl.Technol. Res. 3 (2014) 729–733, http://dx.doi.org/10.7753/ijcatr0311.1016.