8085 microprocessor architecture
DESCRIPTION
8085 Microprocessor Architecture. Accumulator Arithmetic and logic Unit General purpose register Program counter Stack pointer Temporary register Flags Instruction register and Decoder Timing and Control unit Interrupt control Serial Input/output control - PowerPoint PPT PresentationTRANSCRIPT
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8085 Microprocessor Architecture
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8085 Microprocessor Architecture
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AccumulatorArithmetic and logic UnitGeneral purpose registerProgram counterStack pointerTemporary registerFlagsInstruction register and DecoderTiming and Control unitInterrupt controlSerial Input/output controlAddress buffer and Address-Data bufferAddress bus and Data busIncrementer/Decrementer Address Latch
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Intel 8085 CPU Block Diagram
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ALU
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Registers
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Stack Pointer (16)Program Counter (16)
D (8) E (8)B (8) C (8)
Accumulator (A) (8) Flags (F) (8)
H (8) L (8)
1.General PurposeRegisters
3.SpecialPurposeRegisters
4.Sixteen Bit
Registers
2.Temporary Registers(Temp Data, W & Z)
Instruction Registers
16 8 Address
Data
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General purpose Registers
Six general purpose 8-bit registers: B, C, D, E, H, L
They can also be combined as register pairs to perform
16-bit operations: BC, DE, HLRegisters are programmable (Data load,
Move etc.)5
B (8) C (8)16
Data Pointer or Memory Pointer (M)
High order register
Low order register
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Temporary RegistersTemporary data Register The ALU has two inputs. One is Accumulator & other from Temp data Register Ex : ADD B ( A A+B ) W & Z (16) Ex : CALL, XCHG ( HL DE) Note
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First B is transferred to
Temp then add with A
First DE transferred to WZ then exchange
with HLThe programmer Can not access this temp
Registers
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Special purpose Registers
1.Accumulator (A) Single 8-bit register that is part of the
ALU Used in
Arithmetic/logic operations Load store As well as I/O operation
2. Instruction Registers (Discuss later) 7
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Special purpose Registers3.Flag
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S Z AC P CY
S = After the execution of an arithmetic operation, if bit 7 of the
result is 1, then sign flag is set. ( 1 Negative 0 Positive)
Z = Bit is set if ALU operation results a zero in the Accumulator
AC = Bit is set, when a carry is generated by bit 3 & passed on bit 4.
P = Parity bit is set when the result has even number of 1s.
CY = carry is set when result generates a carry. Also a borrow flag.
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Example : ADD B (A)A8H (B)EDH CY 95H (A)
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S Z AC P CY
1 0 1 0 1 0 0 01 1 1 0 1 1 0 1
1 0 0 1 0 1 0 11
1 0 1 1 1
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Program counter & Stack Pointer
PC acts as a pointer to the NEXT instruction depends on upon nature of instruction ( 1 or 2 or 3 Bytes)PC automatically increments to point to the next memory during the execution of the present instruction. ( In Jump or CALL , PC changes to address of subprogram)
Stack is reserved area of the memory ( Temporary information storage - LIFO algorithm)After every stack operation SP points to next available location of the stack (Recent Entry)
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ALU (Arithmetic & Logic Unit) To perform arithmetic operations like Addition & Subtraction To perform logical operations like
ANDOR NOT (Complement)
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Instruction Register & Decoder
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The processor first fetches the opcode of instruction from memory & stores opcode in the instructions registers , it is then sent to instruction decoder
The Instruction decoder decodes the it & accordingly gives for further processing depending on nature of instructions
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Address buffer & Address/Data bufferAddress Buffer8 bit unidirectional bufferThe address bits are always sent from the MPU to peripheral devices, not reverseUsed to drive external High order address bus (A8-A15)
Address Buffer & Address/Data Buffer8 bit Bidirectional bufferThe data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPUUsed to drive multiplexed address/data bus
i.e Low order address bus (A0-A7) & data bus (D0-D7)13
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Bus: A shared group of wires used for communicating signals among devices
•Address Bus : The device and the location within the device that is being accessed
Total 216 = 65,536 (64k) Memory Locations
Address Locations: 0000H– FFFFH• Data Bus : The data value being communicated
Data Range: 00H – FFH • Control Bus : Describes the action on the address & data
buses
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Incrementer/ Decrementer Address Latch
This 16 bit Register is used to increment or decrement the contents of the PC or SP as a part of execution instructions related to them
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Interrupt ControlWhen the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to ( Special Routine or Sub program) an Interrupt Service Routine (ISR) to respond to the incoming interrupt Five Interrupt inputs & one Acknowledge signal
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INTA
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Serial I/O ControlIt provides two lines SOD & SID for Serial Communication 1.SOD (Serial Output Data) used to send Data serially 2.SID (Serial Input Data) used to Receive Data serially
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Timing & Control /circuitry Timing and control unit is a very important unit as it synchronizes the registers and flow of data through various registers and other units
Control Signals : READY, RD, WR, ALEStatus Signals : S0, S1, IO/ MDMA Signals : HOLD, HLDARESET Signals : RESET IN, RESET OUT
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Intel 8085 Pin Configuration
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Classifications of Pins 8085 has 40 PIN IC1. POWER SUPPLY & FREQUENCY Signals2. DATA Bus & ADDRESS Bus 3. CONTROL & STATUS Signals4. INTERRUPT Signals5. SERIAL I/O Signals6. DMA Signals7. RESET Signals
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Power Supply & Frequency Signals• VCC : +5 Power Supply• Vss : Ground Reference• X1 and X2 : Determine the Clock
Frequency• CLOCK OUT : Half the crystal or
Oscillator Frequency (Used as a system clock for other devices)
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X1 CLK OUTX2
6 MHz
3 MHz
+5 V
GND
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Data Bus & Address Bus8085 μp consists of 16pins use as Address Bus & 8 pins use
as Data Bus
Divide into 2 part : A8 – A15 (Upper) : AD0 – AD7 (Lower)
A8 – A15 : Unidirectional, known as ‘High Order Address’AD0 – AD7 : Bidirectional and Dual purpose (Address and Data are Multiplexed)
A0– A7 Low Order Address D0 – D7 Data Bus
The method to change from address bus to data bus known as “Bus MultiplexingBus Multiplexing” (Adv : Reduces the Number of Pins)
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High -order Address Bus( 8 bits)
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Low -order Address Bus(8 bits) & Data Bus(8 bits)
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ALE : Address Latch Enable RD & WR : Read & Write OperationIO/M : I/O Operation or Memory OperationS0 & S1 : Machine Cycle ProgressREADY : Peripheral is ready or not for Data
transfer
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Control & Status Signals
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ALE used to Demultiplex Address/Data bus
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A8-A15
LatchAD7-AD0
D7- D0
A0- A7
ALE
ALE –Active high output used to latch the lower 8 address bits A0 – A7
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RD (Active low) To indicate that the I/O or memory selected is to be read and data are available on the bus
WR (Active low ) This is to indicate that the data available on the bus are to be written to memory or I/O
IO/M To differentiate I/O or memory operations‘0’ - indicates a memory operation‘1’-indicates an I/O operation
S0 & S1 Status signals, similar to IO/M29
Control & Status Signals
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IO/M
RD
WR
MEMR
MEMWR
IOWR
IOWR
RD WR IO/M Operation0 0 0 Never Exists
(RD,WR do not go low simultaneously)
-0 0 1 -0 1 0 Memory Read MEMR0 1 1 I/O Device Read IOR1 0 0 Memory Write MEMW1 0 1 I/O Device Write IOW1 1 0 - -1 1 1 - -
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Interrupt & DMA Signals
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Serial I/O Control SID (Serial Input Data) used to Receive or accept Data serially bit by bit from the external device
SOD (Serial Output Data) used to Transmit or send Data serially bit by bit to the external device
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Reset SignalsRESET IN an active low input signal
1.Set Program Counter to Zero PC=0000H(μp will reset)2.Reset interrupt & HLDA Flip-flops3.Tri states the address, data &control bus4. Affects the contents of internal registers randomly
RESET OUT to indicate that the μp was reset (RESET IN =0 ) It also used to reset external devices.
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