8/14-pin, 8-bit flash microcontroller...rc4 6 5 ——c2out —cwg1b ioc y rc5 5 4 ———ccp1...

PIC12(L)F1612/16(L)F16138/14-Pin, 8-Bit Flash Microcontroller

DescriptionPIC12(L)F1612/16(L)F1613 microcontrollers deliver on-chip features that are unique to the design for embedded controlof small motors and general purpose applications in 8/14-pin count packages. Features like 10-bit A/D, CCP, 24-bit SMTand Zero-Cross Detection offer an excellent solution to the variety of applications. The product family also has a CRC+memory scan and Windowed WDT to support safety-critical systems in home appliances, white goods and other endequipment.

Core Features• C Compiler Optimized RISC Architecture• Only 49 Instructions• Operating Speed:

- DC – 32 MHz clock input- 125 ns minimum instruction cycle

• Interrupt Capability• 16-Level Deep Hardware Stack• One 8-Bit Timer• One 16-bit Timers• Low Current Power-on Reset (POR)• Configurable Power-up Timer (PWRT)• Brown-out Reset (BOR) with Selectable Trip Point• Windowed Watchdog Timer (WWDT):

- Variable prescaler selection- Variable window size selection- All sources configurable in hardware or

software

Memory• 2 KW Flash Program Memory• 256 Bytes Data SRAM• Direct, Indirect and Relative Addressing modes• High-Endurance Flash Data Memory (HEF):

- 128 B of nonvolatile data storage- 100K erase/write cycles

Operating Characteristics• Operating Voltage Range:

- 1.8V to 3.6V (PIC12LF1612/16F1613)- 2.3V to 5.5V (PIC12F1612/16F1613)

• Temperature Range:- Industrial: -40°C to 85°C- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features• Sleep mode: 50 nA @ 1.8V, typical • Watchdog Timer: 500 nA @ 1.8V, typical • Secondary Oscillator: 500 nA @ 32 kHz• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical

Digital Peripherals• Complementary Waveform Generator (CWG):

- Rising and falling edge dead-band control- Full-bridge, half-bridge, 1-channel drive- Multiple signal sources

• Two Capture/Compare/PWM (CCP) modules• Two Signal Measurement Timers (SMT):

- 24-bit timer/counter with prescaler- Multiple gate and clock inputs

• 8-Bit Timers (TMR2+HLT/4/6):- Up to 3 Timer2/4/6 with Hardware Limit Timer

(HLT)- Monitors Fault Conditions: Stall, Stop, etc.- Multiple modes- 8-bit timer/counter with prescaler- 8-bit period register and postscaler- Asynchronous H/W Reset sources

• Cyclic Redundancy Check with Memory Scan (CRC/SCAN):- Software configurable

2014-2017 Microchip Technology Inc. DS40001737C-page 1

PIC12(L)F1612/16(L)F1613

• Up to 11 I/O Pins and One Input-only Pin:

- Individually programmable pull-ups- Slew rate control- Interrupt-on-change with edge-select

Intelligent Analog Peripherals• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 8 external channels- Conversion available during Sleep

• Up to Two Comparators (COMP):- Low-Power/High-Speed mode - Up to three external inverting inputs- Fixed Voltage Reference at non-inverting

input(s) - Comparator outputs externally accessible

• 8-Bit Digital-to-Analog Converter (DAC):- 8-bit resolution, rail-to-rail- Positive Reference Selection

• Voltage Reference:- Fixed Voltage Reference (FVR): 1.024V,

2.048V and 4.096V output levels• Zero-Cross Detect (ZCD):

- Detect when AC signal on pin crosses ground

• Two High-Current Drive Pins:- 100mA @ 5V

Clocking Structure• 16 MHz Internal Oscillator:

- ±1% at calibration- Selectable frequency range from 32 MHz to

31 kHz• 31 kHz Low-Power Internal Oscillator• 4x Phase-Locked Loop (PLL):

- For up to 32 MHz internal operation• External Oscillator Block with:

- Three external clock modes up to 32 MHz


2014-2017 M

icrochip Technology Inc.D

S40001737C

-page 3

PIC12(L)F1612/16(L)F1613

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nt I/

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PI 0 N 0 0PI 0 N 0 0PI 2 Y 1 1PI 2 Y 1 1PI 2 Y 1 1PI 2 Y 1 1NoDa

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BLE 1: PIC12/16(L)F161X FAMILY TYPES

Device

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eet I

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ory

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ory

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es)

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nce

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ith H

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tors

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(ch)

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ss D

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bit P

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C12(L)F1612 (A) 2048 3.5 256 128 6 4 1 0 Y 1 1 4 1 2/0 1 0 Y 0C16(L)F1613 (A) 2048 3.5 256 128 12 4 1 0 Y 2 2 8 1 2/0 1 0 Y 0C16(L)F1614 (B) 4096 7 512 128 12 4 3 1 Y 2 2 8 1 2/2 1 2 Y 1C16(L)F1615 (C) 8192 14 1024 128 12 4 3 1 Y 2 2 8 1 2/2 1 4 Y 1C16(L)F1618 (B) 4096 7 512 128 18 4 3 1 Y 2 2 12 1 2/2 1 2 Y 1C16(L)F1619 (C) 8192 14 1024 128 18 4 3 1 Y 2 2 12 1 2/2 1 4 Y 1te 1: Debugging Methods: (I) – Integrated on Chip; (H) – via ICD Header; E – using Emulation Productta Sheet Index:

A. DS40001737 PIC12(L)F1612/16(L)F1613 Data Sheet, 8/14-Pin, 8-bit Flash Microcontrollers B. DS40001769 PIC16(L)F1614/8 Data Sheet, 14/20-Pin, 8-bit Flash MicrocontrollersC. DS40001770 PIC16(L)F1615/9 Data Sheet, 14/20-Pin, 8-bit Flash Microcontrollers

ote: For other small form-factor package availability and marking information, please visithttp://www.microchip.com/packaging or contact your local sales office.

http://www.microchip.com/wwwproducts/Devices.aspx?product=PIC12F1612http://www.microchip.com/wwwproducts/Devices.aspx?product=PIC16F1613

PIC12(L)F1612/16(L)F1613

PIN DIAGRAMS

TABLE 2: PACKAGESPackages PDIP SOIC DFN UDFN TSSOP QFN UQFN SSOP

PIC12(L)F1612 PIC16(L)F1613

Note: Pin details are subject to change.

8-pin PDIP, SOIC, DFN, UDFN

1

234

8765

VDDRA5

RA4

RA3

VSSRA0

RA1

RA2

14-pin PDIP, SOIC, TSSOP

1

234

14131211

56

7

1098

VDDRA5RA4

MCLR/VPP/RA3RC5RC4RC3

VSSRA0/ICSPDAT

RA1/ICSPCLKRA2

RC0RC1

RC2

16-pin QFN, UQFN

7 8

23

1

11

12

5

910

13141516

6

4

RA5RA4

RA3/MCLR/VPP

RC

4R

C3

RC

1R

C2

RC0

RA0

RA2RA1

Vss

VD

D

NC

RC5

NC


PIC12(L)F1612/16(L)F1613

PIN ALLOCATION TABLES

TABLE 3: 8-PIN ALLOCATION TABLE (PIC12(L)F1612)

I/O

8-Pi

n PD

IP, S

OIC

, DFN

, UD

FN

A/D

Ref

eren

ce

Com

para

tor

Tim

ers

CC

P

CW

G

ZCD

Inte

rrup

t

SMT

Pull-

up

Bas

ic

RA0 7 AN0 DAC1OUT1 C1IN+ — CCP2 CWG1B — IOC — Y ICSPDAT

RA1 6 AN1 VREF+ C1IN0- — — — ZCD1OUT IOC — Y ICSPCLK

RA2 5 AN2 — C1OUT T0CKI CCP1 CWG1ACWG1IN

ZCD1IN INTIOC

SMTSIG2 Y —

RA3 4 — — — T1G(1)T6IN

— — — IOC SMTWIN2 Y MCLR/VPP

RA4 3 AN3 — C1IN1- T1G — CWG1B(1) — IOC SMTSIG1 Y CLKOUT

RA5 2 — — — T1CKIT2IN

CCP1(1) CWG1A(1) — IOC SMTWIN1 Y CLKIN

VDD 1 — — — — — — — — — — VDD

VSS 8 — — — — — — — — — — VSS

Note 1: Alternate pin function selected with the APFCON register.

TABLE 4: 14/16-PIN ALLOCATION TABLE (PIC16(L)F1613)

I/O

14-P

in P

DIP

, SO

IC, T

SSO

P

16-P

in Q

FN, U

QFN

A/D

Ref

eren

ce

Com

para

tor

Tim

ers

CC

P

CW

G

ZCD

Inte

rrup

t

SMT

Pull-

up

Bas

ic

RA0 13 12 AN0 DAC1OUT1 C1IN+ — — — — IOC — Y ICSPDAT

RA1 12 11 AN1 VREF+ C1IN0-C2IN0-

— — — ZCD1OUT IOC — Y ICSPCLK

RA2 11 10 AN2 — C1OUT T0CKIT4IN

— CWG1IN ZCD1IN INTIOC

— Y —

RA3 4 3 — — — T1G(1)T6IN

— — — IOC SMTWIN2 Y MCLR/VPP

RA4 3 2 AN3 — — T1G — — — IOC SMTSIG1 Y CLKOUT

RA5 2 1 — — — T1CKIT2IN

CCP2(1) — — IOC SMTWIN1 Y CLKIN

RC0 10 9 AN4 — C2IN+ — — — — IOC — Y —

RC1 9 8 AN5 — C1IN1-C2IN1-

T4IN — — — IOC SMTSIG2 Y —

RC2 8 7 AN6 — C1IN2-C2IN2-

— — CWG1D — IOC — Y —

RC3 7 6 AN7 — C1IN3-C2IN3-

— CCP2 CWG1C — IOC — Y —

RC4 6 5 — — C2OUT — — CWG1B — IOC — Y —

RC5 5 4 — — — — CCP1 CWG1A — IOC — Y —

VDD 1 16 — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — VSS

Note 1: Alternate pin function selected with the APFCON register.


PIC12(L)F1612/16(L)F1613

TABLE OF CONTENTS1.0 Device Overview .......................................................................................................................................................................... 82.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 153.0 Memory Organization ................................................................................................................................................................. 174.0 Device Configuration .................................................................................................................................................................. 515.0 Oscillator Module........................................................................................................................................................................ 586.0 Resets ........................................................................................................................................................................................ 697.0 Interrupts .................................................................................................................................................................................... 778.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 929.0 Windowed Watchdog Timer (WDT)............................................................................................................................................ 9510.0 Flash Program Memory Control ............................................................................................................................................... 10311.0 Cyclic Redundancy Check (CRC) Module ............................................................................................................................... 11912.0 I/O Ports ................................................................................................................................................................................... 13113.0 Interrupt-On-Change ................................................................................................................................................................ 14614.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 15115.0 Temperature Indicator Module ................................................................................................................................................. 15416.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 15617.0 8-bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 17018.0 Comparator Module.................................................................................................................................................................. 17419.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 18220.0 Timer0 Module ......................................................................................................................................................................... 18821.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 19122.0 Timer2/4/6 Module ................................................................................................................................................................... 20323.0 Capture/Compare/PWM Modules ............................................................................................................................................ 22324.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 23725.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 26326.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 30627.0 Instruction Set Summary .......................................................................................................................................................... 30828.0 Electrical Specifications............................................................................................................................................................ 32229.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 34630.0 Development Support............................................................................................................................................................... 36531.0 Packaging Information.............................................................................................................................................................. 369Appendix A: Data Sheet Revision History ......................................................................................................................................... 393


PIC12(L)F1612/16(L)F1613

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Website; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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mailto:[email protected]://www.microchip.comhttp://www.microchip.com

PIC12(L)F1612/16(L)F1613

1.0 DEVICE OVERVIEWThe PIC12(L)F1612/16(L)F1613 are described within thisdata sheet. The block diagram of these devices areshown in Figure 1-1, the available peripherals are shownin Table 1-1, and the pin out descriptions are shown inTables 1-2 and 1-3.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC

12(L

)F16

12

PIC

16(L

)F16

13

Analog-to-Digital Converter (ADC) ● ●Complementary Wave Generator (CWG) ● ●Cyclic Redundancy Check (CRC) ● ●Digital-to-Analog Converter (DAC) ● ●Fixed Voltage Reference (FVR) ● ●Temperature Indicator ● ●Windowed Watchdog Timer (WDT) ● ●Zero Cross Detection (ZCD) ● ●Capture/Compare/PWM (CCP) Modules

CCP1 ● ●CCP2 ● ●

ComparatorsC1 ● ●C2 ●

Signal Measurement Timer (SMT)SMT1 ● ●SMT2 ● ●

TimersTimer0 ● ●Timer1 ● ●Timer2 ● ●Timer4 ● ●Timer6 ● ●


PIC12(L)F1612/16(L)F1613

1.1 Register and Bit Naming Conventions

1.1.1 REGISTER NAMESWhen there are multiple instances of the sameperipheral in a device, the peripheral control registerswill be depicted as the concatenation of a peripheralidentifier, peripheral instance, and control identifier.The control registers section will show just oneinstance of all the register names with an ‘x’ in the placeof the peripheral instance number. This namingconvention may also be applied to peripherals whenthere is only one instance of that peripheral in thedevice to maintain compatibility with other devices inthe family that contain more than one.

1.1.2 BIT NAMESThere are two variants for bit names:

• Short name: Bit function abbreviation• Long name: Peripheral abbreviation + short name

1.1.2.1 Short Bit NamesShort bit names are an abbreviation for the bit function.For example, some peripherals are enabled with theEN bit. The bit names shown in the registers are theshort name variant.

Short bit names are useful when accessing bits in Cprograms. The general format for accessing bits by theshort name is RegisterNamebits.ShortName. Forexample, the enable bit, EN, in the COG1CON0 regis-ter can be set in C programs with the instructionCOG1CON0bits.EN = 1.Short names are generally not useful in assemblyprograms because the same name may be used bydifferent peripherals in different bit positions. When thisoccurs, during the include file generation, all instancesof that short bit name are appended with an underscoreplus the name of the register in which the bit resides toavoid naming contentions.

1.1.2.2 Long Bit NamesLong bit names are constructed by adding a peripheralabbreviation prefix to the short name. The prefix isunique to the peripheral, thereby making every long bitname unique. The long bit name for the COG1 enablebit is the COG1 prefix, G1, appended with the enablebit short name, EN, resulting in the unique bit nameG1EN.

Long bit names are useful in both C and assembly pro-grams. For example, in C the COG1CON0 enable bitcan be set with the G1EN = 1 instruction. In assembly,this bit can be set with the BSF COG1CON0,G1ENinstruction.

1.1.2.3 Bit FieldsBit fields are two or more adjacent bits in the sameregister. Bit fields adhere only to the short bit namingconvention. For example, the three Least Significantbits of the COG1CON0 register contain the modecontrol bits. The short name for this field is MD. Thereis no long bit name variant. Bit field access is onlypossible in C programs. The following exampledemonstrates a C program instruction for setting theCOG1 to the Push-Pull mode:

COG1CON0bits.MD = 0x5;Individual bits in a bit field can also be accessed withlong and short bit names. Each bit is the field nameappended with the number of the bit position within thefield. For example, the Most Significant mode bit hasthe short bit name MD2 and the long bit name isG1MD2. The following two examples demonstrateassembly program sequences for setting the COG1 toPush-Pull mode:

Example 1:MOVLW ~(1

PIC12(L)F1612/16(L)F1613

FIGURE 1-1: PIC12(L)F1612/16(L)F1613 BLOCK DIAGRAMRev. 10-000039F

5/23/2014

CLKOUT

CLKIN

RAM

CPU

(Note 3)

TimingGeneration

INTRC Oscillator

MCLR

ProgramFlash Memory

FVRADC10-bitTemp

IndicatorTMR0TMR1TMR2

CCP1CCP2ZCD1CWG1

PORTA

DACC1

CRC

TMR4TMR6 C2

SMT2 SMT1

PORTC

(4)

(4)

Scanner

Note 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals available on specific devices.3: See Figure 2-1.4: PIC16(L)F1613 only.


PIC12(L)F1612/16(L)F1613

TABLE 1-2: PIC12(L)F1612 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/AN0/C1IN+/DAC1OUT1/CCP2/CWG1B(1)/ICSPDAT

RA0 TTL/ST CMOS/OD General purpose I/O.AN0 AN — ADC Channel input.

C1IN+ AN — Comparator positive input.DAC1OUT1 — AN Digital-to-Analog Converter output.

CCP2 TTL/ST CMOS/OD Capture/Compare/PWM2.CWG1B — CMOS/OD CWG complementary output B.

ICSPDAT ST CMOS ICSP™ Data I/O.RA1/AN1/VREF+/C1IN0-/ZCD1OUT/ICSPCLK


VREF+ AN — Voltage Reference input.C1IN0- AN — Comparator negative input.

ZCD1OUT — CMOS Zero-Cross Detect output.ICSPCLK ST — ICSP Programming Clock.

RA2/AN2/C1OUT/T0CKI/T4IN/CCP1(1)/CWG1A(1)/CWG1IN/ZCD1IN/INT/SMTSIG2


C1OUT — CMOS/OD Comparator output.T0CKI TTL/ST — Timer0 clock input.T4IN TTL/ST — Timer4 input.CCP1 TTL/ST CMOS/OD Capture/Compare/PWM1.

CWG1A — CMOS/OD CWG complementary output A.CWG1IN TTL/ST — CWG complementary input.ZCD1IN AN — Zero-Cross Detect input.

INT TTL/ST — External interrupt.SMTSIG2 TTL/ST — SMT2 signal input.

RA3/VPP/T1G(1)/T6IN/SMTWIN2/MCLR

RA3 TTL/ST — General purpose input with IOC and WPU.VPP HV — Programming voltage.T1G TTL/ST — Timer1 Gate input.T6IN TTL/ST — Timer6 input.

SMTWIN2 TTL/ST — SMT2 window input.MCLR TTL/ST — Master Clear with internal pull-up.

RA4/AN3/C1IN1-/T1G(1)/CWG1B(1)/SMTSIG1/CLKOUT


C1IN1- AN — Comparator negative input.T1G TTL/ST — Timer1 Gate input.

CWG1B — CMOS/OD CWG complementary output B.SMTSIG1 TTL/ST — SMT1 signal input.CLKOUT — CMOS FOSC/4 output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV = High Voltage XTAL = Crystal levels

Note 1: Alternate pin function selected with the APFCON register (Register 12-1).


PIC12(L)F1612/16(L)F1613

RA5/CLKIN/T1CKI/T2IN/CCP1(1)/CWG1A(1)/SMTWIN1

RA5 TTL/ST CMOS/OD General purpose I/O.CLKIN CMOS — External clock input (EC mode).T1CKI TTL/ST — Timer1 clock input.T2IN TTL/ST — Timer2 input.CCP1 TTL/ST CMOS/OD Capture/Compare/PWM1.

CWG1A — CMOS/OD CWG complementary output A.SMTWIN1 TTL/ST — SMT1 window input.

VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.

TABLE 1-2: PIC12(L)F1612 PINOUT DESCRIPTION (CONTINUED)





PIC12(L)F1612/16(L)F1613

TABLE 1-3: PIC16(L)F1613 PINOUT DESCRIPTION


RA0/AN0/C1IN+/DAC1OUT1/ICSPDAT


C1IN+ AN — Comparator positive input.DAC1OUT1 — AN Digital-to-Analog Converter output.ICSPDAT ST CMOS ICSP™ Data I/O.

RA1/AN1/VREF+/C1IN0-/C2IN0-/ZCD1OUT/ICSPCLK


VREF+ AN — Voltage Reference input.C1IN0- AN — Comparator negative input.C2IN0- AN — Comparator negative input.

ZCD1OUT — CMOS Zero-Cross Detect output.ICSPCLK ST — ICSP Programming Clock.

RA2/AN2/C1OUT/T0CKI/CWG1IN/ZCD1IN/INT


C1OUT — CMOS/OD Comparator output.T0CKI TTL/ST — Timer0 clock input.

CWG1IN TTL/ST — CWG complementary input.ZCD1IN AN — Zero-Cross Detect input.

INT TTL/ST — External interrupt.RA3/VPP/T1G(1)/T6IN/SMTWIN2/MCLR

RA3 TTL/ST — General purpose input with IOC and WPU.VPP HV — Programming voltage.T1G TTL/ST — Timer1 Gate input.T6IN TTL/ST — Timer6 input.

SMTWIN2 TTL/ST — SMT2 window input.MCLR TTL/ST — Master Clear with internal pull-up.

RA4/AN3/T1G(1)/SMTSIG1/CLKOUT

RA4 TTL/ST CMOS/OD General purpose I/O.AN3 AN — ADC Channel input.T1G TTL/ST — Timer1 Gate input.

SMTSIG1 TTL/ST — SMT1 signal input.CLKOUT — CMOS FOSC/4 output.

RA5/CLKIN/T1CKI/T2IN/CCP2(1)/SMTWIN1

RA5 TTL/ST CMOS/OD General purpose I/O.CLKIN CMOS — External clock input (EC mode).T1CKI TTL/ST — Timer1 clock input.T2IN TTL/ST — Timer2 input.CCP2 TTL/ST CMOS/OD Capture/Compare/PWM2.

SMTWIN1 TTL/ST — SMT1 window input.

RC0/AN4/C2IN+ RC0 TTL/ST CMOS/OD General purpose I/O.AN4 AN — ADC Channel input.

C2IN+ AN — Comparator positive input.Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV = High Voltage XTAL = Crystal levels



PIC12(L)F1612/16(L)F1613

RC1/AN5/C1IN1-/C2IN1-/T4IN/SMTSIG2

RC1 TTL/ST CMOS/OD General purpose I/O.AN5 AN — ADC Channel input.

C1IN1- AN — Comparator negative input.C2IN1- AN — Comparator negative input.T4IN TTL/ST — Timer4 input.

SMTSIG2 TTL/ST — SMT2 signal input.RC2/AN6/C1IN2-/C2IN2-/CWG1D

RC2 TTL/ST CMOS/OD General purpose I/O.AN6 AN — ADC Channel input.

C1IN2- AN — Comparator negative input.C2IN2- AN — Comparator negative input.

CWG1D — CMOS/OD CWG complementary output D.RC3/AN7/C1IN3-/C2IN3-/CCP2(1)/CWG1C

RC3 TTL/ST — General purpose input with IOC and WPU.AN7 AN — ADC Channel input.

C1IN3- AN — Comparator negative input.C2IN3- AN — Comparator negative input.CCP2 TTL/ST CMOS/OD Capture/Compare/PWM2.

CWG1C — CMOS/OD CWG complementary output C.RC4/C2OUT/CWG1B RC4 TTL/ST CMOS/OD General purpose I/O.

C2OUT — CMOS/OD Comparator output.CWG1B — CMOS/OD CWG complementary output B.

RC5/CCP1/CWG1A RC5 TTL/ST CMOS/OD General purpose I/O.CCP1 TTL/ST CMOS/OD Capture/Compare/PWM1.

CWG1A — CMOS/OD CWG complementary output A.VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.

TABLE 1-3: PIC16(L)F1613 PINOUT DESCRIPTION (CONTINUED)





PIC12(L)F1612/16(L)F1613

2.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, andRelative Addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.

• Automatic Interrupt Context Saving• 16-level Stack with Overflow and Underflow• File Select Registers• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

1515

15

15

8

8

8

1214

75

3

Program Counter

MUX

Addr MUX

16-Level Stack(15-bit)

Program MemoryRead (PMR)

Instruction Reg

Configuration

FSR0 Reg

FSR1 Reg

BSR Reg

STATUS Reg

RAM

W Reg

Power-upTimer

Power-onReset

WatchdogTimer

Brown-outReset

InstructionDecode and

Control

TimingGeneration

InternalOscillator

Block

ALU

FlashProgramMemoryM

UX

Data Bus

ProgramBus

Direct AddrIndirect

Addr

RAM Addr

CLKIN

CLKOUT

VDD VSS

Rev. 10-000055A7/30/2013

1212


PIC12(L)F1612/16(L)F1613

2.1 Automatic Interrupt Context

SavingDuring interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 7.5 “Automatic Context Saving”,for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bitswide and 16 words deep. A Stack Overflow or Under-flow will set the appropriate bit (STKOVF or STKUNF)in the PCON register, and if enabled, will cause a soft-ware Reset. See section Section 3.5 “Stack” for moredetails.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.6 “Indirect Addressing” for more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. See Section27.0 “Instruction Set Summary” for more details.


PIC12(L)F1612/16(L)F1613

3.0 MEMORY ORGANIZATIONThese devices contain the following types of memory:

• Program Memory- Configuration Words- Device ID- User ID- Flash Program Memory

• Data Memory- Core Registers- Special Function Registers- General Purpose RAM- Common RAM

The following features are associated with access andcontrol of program memory and data memory:

• PCL and PCLATH• Stack• Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing a 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the interrupt vector is at 0004h (SeeFigure 3-1).

3.2 High-Endurance FlashThis device has a 128-byte section of high-enduranceProgram Flash Memory (PFM) in lieu of dataEEPROM. This area is especially well suited fornonvolatile data storage that is expected to beupdated frequently over the life of the end product.See Section 10.2 “Flash Program MemoryOverview” for more information on writing data toPFM. See Section 3.2.1.2 “Indirect Read with FSR”for more information about using the FSR registers toread byte data stored in PFM.

Device Program Memory Space (Words)Last Program Memory

Address

High-Endurance Flash Memory Address

Range(1)

PIC12(L)F1612/16(L)F1613 2,048 07FFh 0780h-07FFhNote 1: High-endurance Flash applies to low byte of each address in the range.


PIC12(L)F1612/16(L)F1613

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FORPIC12(L)F1612/16(L)F1613

3.2.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants inprogram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.2.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table verysimple to implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available, so the older table readmethod must be used.

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC

Interrupt Vector

Page 0

Rollover to Page 0

Rollover to Page 0

0000h

0004h0005h

07FFh0800h

7FFFh

CALL, CALLW RETURN, RETLWInterrupt, RETFIE

On-chipProgramMemory

15

Rev. 10-000040C7/30/2013

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function;… LOTS OF CODE…MOVLW DATA_INDEXcall constants;… THE CONSTANT IS IN W


PIC12(L)F1612/16(L)F1613

3.2.1.2 Indirect Read with FSRThe program memory can be accessed as data by set-ting bit 7 of the FSRxH register and reading the match-ing INDFx register. The MOVIW instruction will place thelower eight bits of the addressed word in the W register.Writes to the program memory cannot be performed viathe INDF registers. Instructions that access the pro-gram memory via the FSR require one extra instructioncycle to complete. Example 3-2 demonstrates access-ing the program memory via an FSR.

The HIGH operator will set bit if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

constantsDW DATA0 ;First constantDW DATA1 ;Second constantDW DATA2DW DATA3

my_function;… LOTS OF CODE…MOVLW DATA_INDEXADDLW LOW constantsMOVWF FSR1LMOVLW HIGH constants;MSb sets

automaticallyMOVWF FSR1HBTFSC STATUS, C ;carry from ADDLW?INCF FSR1h, f ;yesMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W


PIC12(L)F1612/16(L)F1613

3.3 Data Memory OrganizationThe data memory is partitioned in 32 memory bankswith 128 bytes in a bank. Each bank consists of(Figure 3-2):

• 12 core registers• 20 Special Function Registers (SFR)• Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM

The active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as ‘0’. All data memory can beaccessed either directly (via instructions that use the

file registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.6 “IndirectAddressing” for more information.Data memory uses a 12-bit address. The upper five bitsof the address define the Bank address and the lowerseven bits select the registers/RAM in that bank.

3.3.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x80h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-1. For detailed

TABLE 3-1: CORE REGISTERS

Addresses BANKxx00h or x80h INDF0x01h or x81h INDF1x02h or x82h PCLx03h or x83h STATUSx04h or x84h FSR0Lx05h or x85h FSR0Hx06h or x86h FSR1Lx07h or x87h FSR1Hx08h or x88h BSRx09h or x89h WREGx0Ah or x8Ah PCLATHx0Bh or x8Bh INTCON


PIC12(L)F1612/16(L)F1613

3.3.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU• the Reset status

The STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras ‘000u u1uu’ (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section27.0 “Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.


PIC12(L)F1612/16(L)F1613

3.3.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in the appro-priate peripheral chapter of this data sheet.

3.3.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.3.1 Linear Access to GPRThe general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify accessto large memory structures. See Section 3.6.2 “LinearData Memory” for more information.

3.3.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

3.3.5 DEVICE MEMORY MAPSThe memory maps are shown in Table 3-2 throughTable 3-7.

FIGURE 3-2: BANKED MEMORY PARTITIONING

Memory Region7-bit Bank Offset

00h

0Bh0Ch

1Fh20h

6Fh

7Fh

70h

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

General Purpose RAM(80 bytes maximum)

Common RAM(16 bytes)

Rev. 10-000041A7/30/2013


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PIC12(L)F1612/16(L)F1613

TABANK 6 BANK 7

00 0hCore Registers

(Table 3-1)

380hCore Registers

(Table 3-1)

00 Bh 38Bh00 Ch SLRCONA 38Ch INLVLA00 Dh — 38Dh —00 Eh — 38Eh —00 Fh — 38Fh —01 0h — 390h —01 1h — 391h IOCAP01 2h — 392h IOCAN01 3h — 393h IOCAF01 4h — 394h —01 5h — 395h —01 6h — 396h —01 7h — 397h —01 8h — 398h —01 9h — 399h —01 Ah — 39Ah —01 Bh — 39Bh —01 Ch — 39Ch —01 Dh — 39Dh —01 Eh — 39Eh —01 Fh — 39Fh —02 0h

UnimplementedRead as ‘0’

3A0h


06 Fh 3EFh07 0h

Common RAM(Accesses70h – 7Fh)

3F0hCommon RAM

(Accesses70h – 7Fh)

07 Fh 3FFh

Le

BLE 3-2: PIC12(L)F1612 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

0hCore Registers

(Table 3-1)

080hCore Registers

(Table 3-1)

100hCore Registers

(Table 3-1)

180hCore Registers

(Table 3-1)

200hCore Registers

(Table 3-1)

280hCore Registers

(Table 3-1)

30

Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 300h — 090h — 110h — 190h — 210h — 290h — 311h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h CCP1RL 312h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h CCP1RH 313h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h CCP1CON 314h PIR4 094h PIE4 114h — 194h PMDATH 214h — 294h CCP1CAP 315h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 316h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 317h TMR1H 097h — 117h FVRCON 197h VREGCON 217h — 297h — 318h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCP2RL 319h T1GCON 099h OSCCON 119h DAC1CON1 199h — 219h — 299h CCP2RH 31Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah — 21Ah — 29Ah CCP2CON 31Bh PR2 09Bh ADRESL 11Bh — 19Bh — 21Bh — 29Bh CCP2CAP 31Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch — 21Ch — 29Ch — 31Dh T2HLT 09Dh ADCON0 11Dh APFCON 19Dh — 21Dh — 29Dh — 31Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh — 21Eh — 29Eh CCPTMRS 31Fh T2RST 09Fh ADCON2 11Fh — 19Fh — 21Fh — 29Fh — 310h

GeneralPurposeRegister80 Bytes

0A0h


120h


1A0h


220h


2A0h


32

0EFhFh 16Fh 1EFh 26Fh 2EFh 360h

Common RAM

0F0hCommon RAM


170hCommon RAM


1F0hCommon RAM


270hCommon RAM


2F0hCommon RAM


37

Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37

gend: = Unimplemented data memory locations, read as ‘0’.

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PIC12(L)F1612/16(L)F1613

TABANK 6 BANK 7

00 0hCore Registers

(Table 3-1)

380hCore Registers

(Table 3-1)

00 Bh 38Bh00 Ch SLRCONA 38Ch INLVLA00 Dh — 38Dh —00 Eh SLRCONC 38Eh INLVLC00 Fh — 38Fh —01 0h — 390h —01 1h — 391h IOCAP01 2h — 392h IOCAN01 3h — 393h IOCAF01 4h — 394h —01 5h — 395h —01 6h — 396h —01 7h — 397h IOCCP01 8h — 398h IOCCN01 9h — 399h IOCCF01 Ah — 39Ah —01 Bh — 39Bh —01 Ch — 39Ch —01 Dh — 39Dh —01 Eh — 39Eh —01 Fh — 39Fh —02 0h


3A0h


06 Fh 3EFh07 0h

Common RAM(Accesses70h – 7Fh)

3F0hCommon RAM


07 Fh 3FFh

Le

BLE 3-3: PIC16(L)F1613 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

0hCore Registers

(Table 3-1)

080hCore Registers

(Table 3-1)

100hCore Registers

(Table 3-1)

180hCore Registers

(Table 3-1)

200hCore Registers

(Table 3-1)

280hCore Registers

(Table 3-1)

30

Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 300h — 090h — 110h — 190h — 210h — 290h — 311h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h CCPR1L 312h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h CCPR1H 313h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h — 293h CCP1CON 314h PIR4 094h PIE4 114h CM2CON1 194h PMDATH 214h — 294h CCP1CAP 315h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 316h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 317h TMR1H 097h — 117h FVRCON 197h VREGCON 217h — 297h — 318h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 319h T1GCON 099h OSCCON 119h DAC1CON1 199h — 219h — 299h CCPR2H 31Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah — 21Ah — 29Ah CCP2CON 31Bh PR2 09Bh ADRESL 11Bh — 19Bh — 21Bh — 29Bh CCP2CAP 31Ch T2CON 09Ch ADRESH 11Ch ZCD1CON 19Ch — 21Ch — 29Ch — 31Dh T2HLT 09Dh ADCON0 11Dh APFCON 19Dh — 21Dh — 29Dh — 31Eh T2CLKCON 09Eh ADCON1 11Eh — 19Eh — 21Eh — 29Eh CCPTMRS 31Fh T2RST 09Fh ADCON2 11Fh — 19Fh — 21Fh — 29Fh — 310h


0A0h


120h


1A0h


220h


2A0h


32

0EFhFh 16Fh 1EFh 26Fh 2EFh 360h

Common RAM

0F0hCommon RAM


170hCommon RAM


1F0hCommon RAM


270hCommon RAM


2F0hCommon RAM


37



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PIC12(L)F1612/16(L)F1613

TABANK 14 BANK 15

40

40

0h

Bh

Core Registers (Table 3-1)

780h

78Bh


40 Ch — 78Ch —40 Dh — 78Dh —40 Eh — 78Eh —40 Fh — 78Fh —41 0h — 790h —41 1h WDTCON0 791h CRCDATL41 2h WDTCON1 792h CRCDATH41 3h WDTPSL 793h CRCACCL41 4h WDTPSH 794h CRCACCH41 5h WDTTMR 795h CRCSHIFTL41 6h — 796h CRCSHIFTH41 7h — 797h CRCXORL41 8h SCANLADRL 798h CRCXORH41 9h SCANLADRH 799h CRCCON041 Ah SCANHADRL 79Ah CRCCON141 Bh SCANHADRH 79Bh —41 Ch SCANCON0 79Ch —41 Dh SCANTRIG 79Dh —41 Eh — 79Eh —41 Fh — 79Fh —42 0h


7A0h


46 Fh 7EFh47 0h

Accesses70h – 7Fh

7F0hAccesses70h – 7Fh

47 Fh 7FFh

BANK 22 BANK 2380

80

0h

Bh


B80h

B8Bh


80 ChUnimplemented

Read as ‘0’

B8ChUnimplemented

Read as ‘0’86 Fh BEFh87 0h

Accesses70h – 7Fh

BF0hAccesses70h – 7Fh

87 Fh BFFhLe

BLE 3-4: PIC12(L)F1612/16(L)F1613 MEMORY MAP, BANK 8-23BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13

0h

Bh


480h

48Bh


500h

50Bh


580h

58Bh


600h

60Bh


680h

68Bh


70

70Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 700h — 490h — 510h — 590h — 610h — 690h — 711h — 491h — 511h — 591h — 611h — 691h CWG1DBR 712h — 492h — 512h — 592h — 612h — 692h CWG1DBF 713h TMR4 493h — 513h — 593h — 613h — 693h CWG1AS0 714h PR4 494h — 514h — 594h — 614h — 694h CWG1AS1 715h T4CON 495h — 515h — 595h — 615h — 695h CWG1OCON0 716h T4HLT 496h — 516h — 596h — 616h — 696h CWG1CON0 717h T4CLKCON 497h — 517h — 597h — 617h — 697h CWG1CON1 718h T4RST 498h — 518h — 598h — 618h — 698h CWG1OCON1 719h — 499h — 519h — 599h — 619h — 699h CWG1CLKCON 71Ah TMR6 49Ah — 51Ah — 59Ah — 61Ah — 69Ah CWG1ISM 71Bh PR6 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Ch T6CON 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Dh T6HLT 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Eh T6CLKCON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Fh T6RST 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 710h


4A0h


520h


5A0h


620h


6A0h


72

Fh 4EFh 56Fh 5EFh 66Fh 6EFh 760h

Accesses70h – 7Fh


570hAccesses70h – 7Fh




77


BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 210h

Bh

Core Registers (Table 3-1 )

880h

88Bh


900h

90Bh


980h

98Bh


A00h

A0Bh


A80h

A8Bh


B0

B0Ch


88ChUnimplemented

Read as ‘0’

90ChUnimplemented

Read as ‘0’

98ChUnimplemented

Read as ‘0’

A0ChUnimplemented

Read as ‘0’

A8ChUnimplemented

Read as ‘0’

B0

Fh 8EFh 96Fh 9EFh A6Fh AEFh B60h

Accesses70h – 7Fh




A70hAccesses70h – 7Fh

AF0hAccesses70h – 7Fh

B7

Fh 8FFh 97Fh 9FFh A7Fh AFFh B7gend: = Unimplemented data memory locations, read as ‘0’.

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PIC12(L)F1612/16(L)F1613

TA

Le

BANK 30 BANK 31C

C

00h

Bh


F80h

F8Bh


C Ch — F8Ch

See Table 3-7 for register mapping

details

C Dh — F8DhC Eh — F8EhC Fh — F8FhC 10h — F90hC 11h — F91hC 12h — F92hC 13h — F93hC 14h — F94hC 15h — F95hC 16h — F96hC 17h — F97hC 18h — F98hC 19h — F99hC Ah — F9AhC Bh — F9BhC Ch — F9ChC Dh — F9DhC Eh — F9EhC Fh — F9FhC 20h


FA0h

C Fh FEFhC 70h

Accesses70h – 7Fh

FF0hAccesses70h – 7Fh

C Fh FFFh

BLE 3-5: PIC12(L)F1612/16(L)F1613 MEMORY MAP, BANK 24-31


BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 2900h

0Bh


C80h

C8Bh


D00h

D0Bh


D80h

D8Bh


E00h

E0Bh


E80h

E8Bh


F

F00Ch — C8Ch — D0Ch — D8Ch

See Table 3-6 for register mapping

details

E0Ch — E8Ch — F00Dh — C8Dh — D0Dh — D8Dh E0Dh — E8Dh — F00Eh — C8Eh — D0Eh — D8Eh E0Eh — E8Eh — F00Fh — C8Fh — D0Fh — D8Fh E0Fh — E8Fh — F010h — C90h — D10h — D90h E10h — E90h — F11h — C91h — D11h — D91h E11h — E91h — F12h — C92h — D12h — D92h E12h — E92h — F13h — C93h — D13h — D93h E13h — E93h — F14h — C94h — D14h — D94h E14h — E94h — F15h — C95h — D15h — D95h E15h — E95h — F16h — C96h — D16h — D96h E16h — E96h — F17h — C97h — D17h — D97h E17h — E97h — F18h — C98h — D18h — D98h E18h — E98h — F19h — C99h — D19h — D99h E19h — E99h — F1Ah — C9Ah — D1Ah — D9Ah E1Ah — E9Ah — F11Bh — C9Bh — D1Bh — D9Bh E1Bh — E9Bh — F11Ch — C9Ch — D1Ch — D9Ch E1Ch — E9Ch — F11Dh — C9Dh — D1Dh — D9Dh E1Dh — E9Dh — F11Eh — C9Eh — D1Eh — D9Eh E1Eh — E9Eh — F11Fh — C9Fh — D1Fh — D9Fh E1Fh — E9Fh — F120h


CA0h


D20h


DA0h E20h


EA0h


F

6Fh CEFh D6Fh DEFh E6Fh EEFh F670h

Accesses70h – 7Fh

CF0hAccesses70h – 7Fh

D70hAccesses70h – 7Fh

DF0hAccesses70h – 7Fh

E70hAccesses70h – 7Fh

EF0hAccesses70h – 7Fh

F

FFh CFFh D7Fh DFFh E7Fh EFFh F7

PIC12(L)F1612/16(L)F1613

TABLE 3-6: PIC12(L)F1612/16(L)F1613

MEMORY MAP, BANK 27 TABLE 3-7: PIC12(L)F1612/16(L)F1613

MEMORY MAP, BANK 31

Bank 27D8Ch SMT1TMRLD8Dh SMT1TMRHD8Eh SMT1TMRUD8Fh SMT1CPRLD90h SMT1CPRHD91h SMT1CPRUD92h SMT1CPWLD93h SMT1CPWHD94h SMT1CPWUD95h SMT1PRLD96h SMT1PRHD97h SMT1PRUD98h SMT1CON0D99h SMT1CON1D9Ah SMT1STATD9Bh SMT1CLKD9Ch SMT1SIGD9Dh SMT1WIND9Eh SMT2TMRLD9Fh SMT2TMRHDA0h SMT2TMRUDA1h SMT2CPRLDA2h SMT2CPRHDA3h SMT2CPRUDA4h SMT2CPWLDA5h SMT2CPWHDA6h SMT2CPWUDA7h SMT2PRLDA8h SMT2PRHDA9h SMT2PRUDAAh SMT2CON0DABh SMT2CON1DACh SMT2STATDADh SMT2CLKDAEh SMT2SIGDAFh SMT2WINDB0h

—DEFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Bank 31F8Ch

FE3h


FE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh —FEDh STKPTRFEEh TOSLFEFh TOSH

Legend: = Unimplemented data memory locations,read as ‘0’.


PIC12(L)F1612/16(L)F1613

3.3.6 CORE FUNCTION REGISTERS

SUMMARYThe Core Function registers listed in Table 3-8 can beaddressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue on all other Resets

Bank 0-31x00h or x80h INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x01h or x81h INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x02h or x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h or x83h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu

x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h or x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h or x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h or x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h or x88h BSR — — — BSR ---0 0000 ---0 0000

x09h or x89h WREG Working Register 0000 0000 uuuu uuuu

x0Ah or x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh or x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.


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TA

A Bit 0 Value onPOR, BORValue on all other Resets

B00 RA0 --xx xxxx --xx xxxx00 — —00 RC0 --xx xxxx --xx xxxx00 — —01 — —01 TMR1IF 00-- -000 00-- -00001 CCP2IF -00- -000 -00- -00001 — --00 ---- --00 ----01 SMT1IF 0000 0000 0000 000001 xxxx xxxx uuuu uuuu01 xxxx xxxx uuuu uuuu01 xxxx xxxx uuuu uuuu01 TMR1ON 0000 -0-0 uuuu -u-u01 0000 0x00 uuuu uxuu

01 0000 0000 0000 000001 1111 1111 1111 111101 0000 0000 0000 000001 000- 0000 000- 000001 ---- -000 ---- -00001 ---- 0000 ---- 0000Le ented, read as ‘0’.No

BLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

ddr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

ank 0Ch PORTA — — RA5 RA4 RA3 RA2 RA1Dh — UnimplementedEh PORTC(4) — — RC5 RC4 RC3 RC2 RC1Fh — Unimplemented0h — Unimplemented1h PIR1 TMR1GIF ADIF — — — CCP1IF TMR2IF2h PIR2 — C2IF(4) C1IF — — TMR6IF TMR4IF3h PIR3 — — CWGIF ZCDIF — — —4h PIR4 SCANIF CRCIF SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF5h TMR0 Holding Register for the 8-bit Timer0 Count6h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count7h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count8h T1CON TMR1CS T1CKPS — T1SYNC —9h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONET1GVAL T1GSS

Ah TMR2 Timer2 Module RegisterBh PR2 Timer2 Period RegisterCh T2CON ON CKPS OUTPSDh T2HLT PSYNC CKPOL CKSYNC — MODEEh T2CLKCON — — — — — T2CSFh T2RST — — — — RSELgend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemte 1: PIC12F1612/16F1613 only.

2: Unimplemented, read as ‘1’.3: PIC12(L)F1612 only.4: PIC16(L)F1613 only.

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B08 TRISA0 --11 1111 --11 111108 — —08 TRISC0 --11 1111 --11 111108 — —09 — —09 TMR1IE 00-- -000 00-- -00009 CCP2IE -00- -000 -00- -00009 — --00 ---- --00 ----09 SMT1IE 0000 0000 0000 000009 1111 1111 1111 111109 BOR 00-1 11qq qq-q qquu09 — —09 --00 0000 --00 000009 1:0> 0011 1-00 0011 1-0009 HFIOFS -0-0 0000 -q-q qqqq09 xxxx xxxx uuuu uuuu09 xxxx xxxx uuuu uuuu09 ADON -000 0000 -000 000009 F 0000 --00 0000 --0009 — 0000 ---- 0000 ----

TA


Le ented, read as ‘0’.No

ank 1Ch TRISA — — TRISA5 TRISA4 —(2) TRISA2 TRISA1Dh — UnimplementedEh TRISC(4) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1Fh — Unimplemented0h — Unimplemented1h PIE1 TMR1GIE ADIE — — — CCP1IE TMR2IE2h PIE2 — C2IE(4) C1IE — — TMR6IE TMR4IE3h PIE3 — — CWGIE ZCDIE — — —4h PIE4 SCANIE CRCIE SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE5h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS6h PCON STKOVF STKUNF WDTWV RWDT RMCLR RI POR7h — Unimplemented8h OSCTUNE — — TUN9h OSCCON SPLLEN IRCF — SCS<Ah OSCSTAT — PLLR — HFIOFR HFIOFL MFIOFR LFIOFRBh ADRESL ADC Result Register LowCh ADRESH ADC Result Register HighDh ADCON0 — CHS GO/DONEEh ADCON1 ADFM ADCS — — ADPREFh ADCON2 TRIGSEL — — —

BLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)


gend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemte 1: PIC12F1612/16F1613 only.


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B10 LATA0 --xx -xxx --uu -uuu10 — —10 LATC0 --xx xxxx --uu uuuu10 — —11 — —11 C1SYNC 0000 -100 0000 -10011 0000 -000 0000 -00011 C2SYNC 0000 -100 0000 -10011 0000 -000 0000 -00011 MC1OUT ---- --00 ---- --0011 BORRDY 10-- ---q uu-- ---u11 0q00 0000 0q00 000011 — 0-0- 00-- 0-0- 00--11 0000 0000 0000 000011 — —11 — —11 ZCD1INTN 0000 --00 0000 --0011 CCP1SEL(3) -00- 0-00 -00- 0-0011 — —11 — —

TA



ank 2Ch LATA — — LATA5 LATA4 — LATA2 LATA1Dh — UnimplementedEh LATC(4) — — LATC5 LATC4 LATC3 LATC2 LATC1Fh — Unimplemented0h — Unimplemented1h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS2h CM1CON1 C1INTP C1INTN C1PCH — C1NCH3h CM2CON0(4) C2ON C2OUT C2OE C2POL — C2SP C2HYS4h CM2CON1(4) C2INTP C2INTN C2PCH — C2NCH5h CMOUT — — — — — — MC2OUT(4)

6h BORCON SBOREN BORFS — — — — —7h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR8h DAC1CON0 DAC1EN — DAC1OE1 — DAC1PSS —9h DAC1CON1 DAC1RAh — UnimplementedBh — UnimplementedCh ZCD1CON ZCD1EN ZCD1OE ZCD1OUT ZCD1POL — — ZCD1INTPDh APFCON — CWGASEL(3) CWGBSEL(3) — T1GSEL — CCP2SEL(4)

Eh — UnimplementedFh — Unimplemented





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B18 ANSA0 ---1 -111 ---1 -11118 — —18 ANSC0 ---- 1111 ---- 111118 — —19 — —19 0000 0000 0000 000019 1000 0000 1000 000019 xxxx xxxx uuuu uuuu19 --xx xxxx --uu uuuu19 RD 1000 x000 1000 q00019 0000 0000 0000 000019 Reserved ---- --01 ---- --01

1

1— —

B20 WPUA0 --11 1111 --11 111120 — —20 WPUC0 --11 1111 --11 1111

2

2— —

TA



ank 3Ch ANSELA — — — ANSA4 — ANSA2 ANSA1Dh — UnimplementedEh ANSELC(4) — — — — ANSC3 ANSC2 ANSC1Fh — Unimplemented0h — Unimplemented1h PMADRL Flash Program Memory Address Register Low Byte2h PMADRH —(2) Flash Program Memory Address Register High Byte3h PMDATL Flash Program Memory Read Data Register Low Byte4h PMDATH — — Flash Program Memory Read Data Register High Byte5h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR6h PMCON2 Flash Program Memory Control Register 2 7h VREGCON(1) — — — — — — VREGPM98hto9Fh

— Unimplemented

ank 4Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1Dh — UnimplementedEh WPUC(4) — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC10Fhto1Fh

— Unimplemented





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B28 ODA0 --00 -000 --00 -00028 — —28 ODC0 --00 0000 --00 000028 — —29 — —29 xxxx xxxx uuuu uuuu29 xxxx xxxx uuuu uuuu29 0000 0000 0000 000029 1:0> ---- --00 ---- --00

2

2— —

29 xxxx xxxx uuuu uuuu29 xxxx xxxx uuuu uuuu29 0000 0000 0000 000029 1:0> ---- --00 ---- --0029 — —29 — —29 L ---- 0000 ---- 000029 — — B30 SLRA0 --00 -000 --00 -00030 — —30 SLRC0 --00 0000 --00 000030 —31

— —

TA



ank 5Ch ODCONA — — ODA5 ODA4 — ODA2 ODA1Dh — UnimplementedEh ODCONC(4) — — ODC5 ODC4 ODC3 ODC2 ODC1Fh — Unimplemented0h — Unimplemented1h CCP1RL Capture/Compare/PWM 1 Register (LSB)2h CCP1RH Capture/Compare/PWM 1 Register (MSB)3h CCP1CON EN OE OUT FMT MODE4h CCP1CAP — — — — — — CTS<95h—97h

— Unimplemented

8h CCP2RL Capture/Compare/PWM 2 Register (LSB)9h CCP2RH Capture/Compare/PWM 2 Register (MSB)Ah CCP2CON EN OE OUT FMT MODEBh CCP2CAP — — — — — — CTS<Ch — UnimplementedDh — UnimplementedEh CCPTMRS — — — — C2TSEL C1TSEFh — Unimplementedank 6

Ch SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1Dh — UnimplementedEh SLRCONC(4) — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1Fh

Fh— Unimplemented





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B38 INLVLA0 --11 1111 --11 111138 — —38 INLVLC0 --11 1111 --11 111130 — —39 — —39 IOCAP0 --00 0000 --00 000039 IOCAN0 --00 0000 --00 000039 IOCAF0 --00 0000 --00 000039 — —39 — —39 — —39 IOCCP0 --00 0000 --00 000039 IOCCN0 --00 0000 --00 000039 IOCCF0 --00 0000 --00 0000

3

3— —

TA



ank 7Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1Dh — UnimplementedEh INLVLC(4) — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1Fh — Unimplemented0h — Unimplemented1h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP12h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN13h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF14h — Unimplemented5h — Unimplemented6h — Unimplemented7h IOCCP(4) — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP18h IOCCN(4) — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN19h IOCCF(4) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF19Ahto9Fh

— Unimplemented





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B4

4— —

41 0000 0000 0000 000041 1111 1111 1111 111141 0000 0000 0000 000041 000- 0000 000- 000041 ---- -000 ---- -00041 ---- 0000 ---- 000041 — —41 0000 0000 0000 000041 1111 1111 1111 111141 0000 0000 0000 000041 000- 0000 000- 000041 ---- -000 ---- -00041 ---- 0000 ---- 0000 B

4

4— —

B5

5— —

B5

5— —

TA



ank 80Chto12h

— Unimplemented

3h TMR4 Timer4 Module Register4h PR4 Timer4 Period Register5h T4CON ON CKPS OUTPS6h T4HLT PSYNC CKPOL CKSYNC — MODE7h T4CLKCON — — — — — T4CS8h T4RST — — — — RSEL9h — UnimplementedAh TMR6 Timer6 Module RegisterBh PR6 Timer6 Period RegisterCh T6CON ON CKPS OUTPSDh T6HLT PSYNC CKPOL CKSYNC — MODEEh T6CLKCON — — — — — T6CSFh T6RST — — — — RSELank 9

8Chto9Fh

— Unimplemented

ank 100Chto1Fh

— Unimplemented

ank 118Chto9Fh

— Unimplemented





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B6

6— —

B6

6— —

69 --00 0000 --00 000069 --xx xxxx --xx xxxx69 — 0000 00-- 0000 00--69 INAS -000 -000 -000 -00069 STRA 0000 0000 0000 000069 00-- -000 00-- -00069 POLA --x- 0000 --x- 000069 OEA ---- 0000 ---- 000069 CS ---- ---0 ---- ---069 ---- -000 ---- -000

6

6— —

TA



ank 120Chto1Fh

— Unimplemented

ank 138Chto90h

— Unimplemented

1h CWG1DBR — — DBR2h CWG1DBF — — DBF3h CWG1AS0 SHUTDOWN REN LSBD LSAC —4h CWG1AS1 — TMR6AS TMR4AS TMR2AS — C2AS(4) C1AS5h CWG1OCON0 OVRD OVRC OVRB OVRA STRD STRC STRB6h CWG1CON0 EN LD — — — MODE7h CWG1CON1 — — IN — POLD POLC POLB8h CWG1OCON1 — — — — OED OEC OEB9h CWG1CLKCON — — — — — — —Ah CWG1ISM — — — — — IS9BhtoEFh

— Unimplemented





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B7

7— —

71 SEN --qq qqqq --qq qqqq71 -qqq -qqq -qqq -qqq71 0000 0000 0000 000071 0000 0000 0000 000071 17:16> 0000 0000 0000 000071 — —71 — —71 0000 0000 0000 000071 0000 0000 0000 000071 1111 1111 1111 111171 1111 1111 1111 111171 0000 0-00 0000 0-0071 ---- --00 ---- --0071 — —71 — —

TA



ank 140Chto10h

— Unimplemented

1h WDTCON0 — — WDTPS2h WDTCON1 — WDTCS — WINDOW3h WDTPSL PSCNT4h WDTPSH PSCNT5h WDTTMR WDTTMR STATE PSCNT<6h — Unimplemented7h — Unimplemented8h SCANLADRL LADR9h SCANLADRH LADRAh SCANHADRL HADRBh SCANHADRH HADRCh SCANCON0 EN SCANGO BUSY INVALID INTM — MODEDh SCANTRIG — — TSELEh — UnimplementedFh — Unimplemented





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B7

7— —

79 xxxx xxxx xxxx xxxx79 xxxx xxxx xxxx xxxx79 0000 0000 0000 000079 0000 0000 0000 000079 0000 0000 0000 000079 0000 0000 0000 000079 — xxxx xxx- xxxx xxx-79 xxxx xxxx xxxx xxxx79 FULL 0000 --00 0000 -0079 0000 0000 0000 0000

7

7— —

Bx0x8 —x1x9

— —

TA



ank 158Chto90h

— Unimplemented

1h CRCDATL DATA2h CRCDATH DATA3h CRCACCL ACC4h CRCACCH ACC5h CRCSHIFTL SHIFT6h CRCSHIFTH SHIFT7h CRCXORL XOR8h CRCXORH XOR9h CRCCON0 EN CRCGO BUSY ACCM — — SHIFTMAh CRCCON1 DLEN PLEN9Bhto9Fh

— Unimplemented

ank 16-26Ch/Ch

Fh/Fh

— Unimplemented





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BD

D— —

D8 0000 0000 0000 0000D8 0000 0000 0000 0000D8 0000 0000 0000 0000D8 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 xxxx xxxx xxxx xxxxD9 S 0-00 0000 0-00 0000D9 00-- 0000 00-- 0000D9 AS 000- -000 000- -000D9 ---- -000 ---- -000D9 ---- 0000 ---- 0000D9 ---- -000 ---- -000D9 0000 0000 0000 0000D9 0000 0000 0000 0000DA 0000 0000 0000 0000DA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxx

TA



ank 2780hto8Bh

— Unimplemented

Ch SMT1TMRL SMT1TMRDh SMT1TMRH SMT1TMREh SMT1TMRU SMT1TMRFh SMT1CPRL SMT1CPR0h SMT1CPRH SMT1CPR1h SMT1CPRU SMT1CPR2h SMT1CPWL SMT1CPW3h SMT1CPWH SMT1CPW4h SMT1CPWU SMT1CPW5h SMT1PRL SMT1PR6h SMT1PRH SMT1PR7h SMT1PRU SMT1PR8h SMT1CON0 EN — STP WPOL SPOL CPOL SMTxP9h SMT1CON1 SMTxGO REPEAT — — MODEAh SMT1STAT CPRUP CPWUP RST — — TS WSBh SMT1CLK — — — — — CSELCh SMT1SIG — — — — SSELDh SMT1WIN — — — — — WSELEh SMT2TMRL SMT2TMRFh SMT2TMRH SMT2TMR0h SMT2TMRU SMT2TMR1h SMT2CPRL SMT2CPR2h SMT2CPRH SMT2CPR3h SMT2CPRU SMT2CPR4h SMT2CPWL SMT2CPW





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BDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA S 0-00 0000 0-00 0000DA 00-- 0000 00-- 0000DA AS 000- -000 000- -000DA ---- -000 ---- -000DA ---- 0000 ---- 0000DA ---- -000 ---- -000

TA



ank 27 (Continued)5h SMT2CPWH SMTxCPW6h SMT2CPWU SMTxCPW7h SMT2PRL SMTxPR8h SMT2PRH SMTxPR9h SMT2PRU SMTxPRAh SMT2CON0 EN — STP WPOL SPOL CPOL SMTxPBh SMT2CON1 SMTxGO REPEAT — — MODECh SMT2STAT CPRUP CPWUP RST — — TS WSDh SMT2CLK — — — — — CSELEh SMT2SIG — — — — SSELFh SMT2WIN — — — — — WSEL





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BDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA S 0-00 0000 0-00 0000DA 00-- 0000 00-- 0000DA AS 000- -000 000- -000DA ---- -000 ---- -000DA ---- 0000 ---- 0000DA ---- -000 ---- -000DA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA S 0-00 0000 0-00 0000DA 00-- 0000 00-- 0000DA AS 000- -000 000- -000DA ---- -000 ---- -000DA ---- 0000 ---- 0000DA ---- -000 ---- -000DA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxxDA xxxx xxxx xxxx xxxx

TA



anks 285h SMT2CPWH SMTxCPW6h SMT2CPWU SMTxCPW7h SMT2PRL SMTxPR8h SMT2PRH SMTxPR9h SMT2PRU SMTxPRAh SMT2CON0 EN — STP WPOL SPOL CPOL SMTxPBh SMT2CON1 SMTxGO REPEAT — — MODECh SMT2STAT CPRUP CPWUP RST — — TS WSDh SMT2CLK — — — — — CSELEh SMT2SIG — — — — SSELFh SMT2WIN — — — — — WSEL5h SMT2CPWH SMTxCPW6h SMT2CPWU SMTxCPW7h SMT2PRL SMTxPR8h SMT2PRH SMTxPR9h SMT2PRU SMTxPRAh SMT2CON0 EN — STP WPOL SPOL CPOL SMTxPBh SMT2CON1 SMTxGO REPEAT — — MODECh SMT2STAT CPRUP CPWUP RST — — TS WSDh SMT2CLK — — — — — CSELEh SMT2SIG — — — — SSELFh SMT2WIN — — — — — WSEL5h SMT2CPWH SMTxCPW6h SMT2CPWU SMTxCPW7h SMT2PRL SMTxPR





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Bx0x8 —x1x9

— —

TA



ank 29-30Ch/Ch

Fh/Fh

— Unimplemented





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BF8 —FE

— —

FE C_SHAD ---- -xxx ---- -uuu

FE xxxx xxxx uuuu uuuu

FE ---x xxxx ---u uuuu

FE -xxx xxxx uuuu uuuu





FE — —FE ---1 1111 ---1 1111FE xxxx xxxx uuuu uuuuFE -xxx xxxx -uuu uuuu

TA



ank 31Ch

3h

— Unimplemented

4h STATUS_SHAD

— — — — — Z_SHAD DC_SHAD

5h WREG_SHAD

Working Register Shadow

6h BSR_SHAD

— — — Bank Select Register Shadow

7h PCLATH_SHAD

— Program Counter Latch High Register Shadow

8h FSR0L_SHAD

Indirect Data Memory Address 0 Low Pointer Shadow

9h FSR0H_SHAD

Indirect Data Memory Address 0 High Pointer Shadow

Ah FSR1L_SHAD

Indirect Data Memory Address 1 Low Pointer Shadow

Bh FSR1H_SHAD

Indirect Data Memory Address 1 High Pointer Shadow

Ch — UnimplementedDh STKPTR — — — Current Stack Pointer

Eh TOSL Top-of-Stack Low byte

Fh TOSH — Top-of-Stack High byte





PIC12(L)F1612/16(L)F1613

3.4 PCL and PCLATHThe Program Counter (PC) is 15 bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The high byte (PC) is not directlyreadable or writable and comes from PCLATH. On anyReset, the PC is cleared. Figure 3-3 shows the fivesituations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS

3.4.1 MODIFYING PCLExecuting any instruction with the PCL register as thedestination simultaneously causes the ProgramCounter PC bits (PCH) to be replaced by thecontents of the PCLATH register. This allows the entirecontents of the program counter to be changed bywriting the desired upper seven bits to the PCLATHregister. When the lower eight bits are written to thePCL register, all 15 bits of the program counter willchange to the values contained in the PCLATH registerand those being written to the PCL register.

3.4.2 COMPUTED GOTOA computed GOTO is accomplished by adding an offset tothe program counter (ADDWF PCL). When performing atable read using a computed GOTO method, care shouldbe exercised if the table location crosses a PCL memoryboundary (each 256-byte block). Refer to ApplicationNote AN556, “Implementing a Table Read” (DS00556).

3.4.3 COMPUTED FUNCTION CALLSA computed function CALL allows programs to maintaintables of functions and provide another way to executestate machines or look-up tables. When performing atable read using a computed function CALL, careshould be exercised if the table location crosses a PCLmemory boundary (each 256-byte block).

If using the CALL instruction, the PCH and PCLregisters are loaded with the operand of the CALLinstruction. PCH is loaded with PCLATH.

The CALLW instruction enables computed calls by com-bining PCLATH and W to form the destination address.A computed CALLW is accomplished by loading the Wregister with the desired address and executing CALLW.The PCL register is loaded with the value of W andPCH is loaded with PCLATH.

3.4.4 BRANCHINGThe branching instructions add an offset to the PC.This allows relocatable code and code that crossespage boundaries. There are two forms of branching,BRW and BRA. The PC will have incremented to fetchthe next instruction in both cases. When using eitherbranching instruction, a PCL memory boundary may becrossed.

If using BRW, load the W register with the desiredunsigned address and execute BRW. The entire PC willbe loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,the signed value of the operand of the BRA instruction.

7 86

14

0

0

4 11

0

6 0

14

7 86 0

014

15

014

15

014

PCL

PCL

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

PC

PC

PC

PC

PC

PCLATH

PCLATH

PCLATH

Instructionwith PCL asDestination

GOTO, CALL

CALLW

BRW

BRA

ALU result

OPCODE

W

PC + W

PC + OPCODE

Rev. 10-000042A7/30/2013


PIC12(L)F1612/16(L)F1613

3.5 StackAll devices have a 16-level x 15-bit wide hardwarestack (refer to Figures 3-4 through 3-7). The stackspace is not part of either program or data space. ThePC is PUSHed onto the stack when CALL or CALLWinstructions are executed or an interrupt causes abranch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH isnot affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVRENbit is programmed to ‘0’ (Configuration Words). Thismeans that after the stack has been PUSHed sixteentimes, the seventeenth PUSH overwrites the value thatwas stored from the first PUSH. The eighteenth PUSHoverwrites the second PUSH (and so on). TheSTKOVF and STKUNF flag bits will be set on an Over-flow/Underflow, regardless of whether the Reset isenabled.

3.5.1 ACCESSING THE STACKThe stack is available through the TOSH, TOSL andSTKPTR registers. STKPTR is the current value of theStack Pointer. TOSH:TOSL register pair points to theTOP of the stack. Both registers are read/writable. TOSis split into TOSH and TOSL due to the 15-bit size of thePC. To access the stack, adjust the value of STKPTR,which will position TOSH:TOSL, then read/write toTOSH:TOSL. STKPTR is five bits to allow detection ofoverflow and underflow.

During normal program operation, CALL, CALLW andInterrupts will increment STKPTR while RETLW,RETURN, and RETFIE will decrement STKPTR. At anytime STKPTR can be inspected to see how much stackis left. The STKPTR always points at the currently usedplace on the stack. Therefore, a CALL or CALLW willincrement the STKPTR and then write the PC, and areturn will unload the PC and then decrement theSTKPTR.

Reference Figure 3-4 through Figure 3-7 for examplesof accessing the stack.

FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1

Note 1: There are no instructions/mnemonicscalled PUSH or POP. These are actionsthat occur from the execution of theCALL, CALLW, RETURN, RETLW andRETFIE instructions or the vectoring toan interrupt address.

Note: Care should be taken when modifying theSTKPTR while interrupts are enabled.

STKPTR = 0x1FStack Reset Disabled(STVREN = 0)

Stack Reset Enabled(STVREN = 1)

Initial Stack Configuration:

After Reset, the stack is empty. Theempty stack is initialized so the StackPointer is pointing at 0x1F. If the StackOverflow/Underflow Reset is enabled, theTOSH/TOSL register will return ‘0’. If theStack Overflow/Underflow Reset isdisabled, the TOSH/TOSL register willreturn the contents of stack address0x0F.

0x0000 STKPTR = 0x1F

TOSH:TOSL 0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

0x1FTOSH:TOSL

Rev. 10-000043A7/30/2013


PIC12(L)F1612/16(L)F1613



STKPTR = 0x00Return Address

This figure shows the stack configurationafter the first CALL or a single interrupt.If a RETURN instruction is executed, thereturn address will be placed in theProgram Counter and the Stack Pointerdecremented to the empty state (0x1F).

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00TOSH:TOSL

Rev. 10-000043B7/30/2013

STKPTR = 0x06

After seven CALLs or six CALLs and aninterrupt, the stack looks like the figure onthe left. A series of RETURN instructions willrepeatedly place the return addresses intothe Program Counter and pop the stack.

Return Address

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

8/14-pin, 8-bit flash microcontroller...rc4 6 5 ——c2out —cwg1b ioc y rc5 5 4 ———ccp1...

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