EE Dept., SJSU 9/6/98 VHDL.1 Fundamental of VHDL Design for FPGA All rights reserved /chp

EE Dept., SJSU 9/6/98 VHDL.2 Fundamental of VHDL Design for FPGA All rights reserved /chp

AgendaAgenda Chapter 1: Who is in attendant? What is VHDL?

Chapter 2: VHDL Design w/ Max+PlusII

Chapter 3: ABCs of VHDL

Chapter 4: Introduction to Data Types

Chapter 5: Processes

Chapter 6: Basic syntax

Chapter 7: Attributes & Data types

Chapter 8: Signals & Signal Assignments

Chapter 9: Concurrent Assignments

Chapter 10: Summary

EE Dept., SJSU 9/6/98 VHDL.3 Fundamental of VHDL Design for FPGA All rights reserved /chp

Chapter 1 - Who is inChapter 1 - Who is inAttendance?Attendance?

Designers to perform digital design withVHDL

Target to Altera FPGA using MaxPlusII asa design tool

Possess little or no VHDL background,however, familiar to C programming language

Intermediate digital design knowledge, e.g.,comfortable with sync/async digital design

EE Dept., SJSU 9/6/98 VHDL.4 Fundamental of VHDL Design for FPGA All rights reserved /chp

Chapter 1 - What is VHDL?Chapter 1 - What is VHDL? Acronym for VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language.

Design language for digital & VLSI systems

Developed by IEEE Analysis/Standard group & approvedby IEEE Standards Boards in 1987 (IEEE Standard 1076-1987) - Newer standard is available: IEEE1076-1993

Supports behavioral, dataflow, and structural modelingfeatures.

Top-down hierarchical modeling.

Powerful features: technology independence, logicsynthesis, test vector generation, and design verification.

EE Dept., SJSU 9/6/98 VHDL.5 Fundamental of VHDL Design for FPGA All rights reserved /chp

Architectural DesignArchitectural Design

Architectural Designin VHDL is portable among VHDL compilers

SynthesisMany different synthesis tools produce gate levelschematics from VHDL

ManufactureThe manufacturing design tools are targeted specifically for one silicon technology, e.g.,FPGA, gate arrays, custom ICSilicon Chip Prototype

EE Dept., SJSU 9/6/98 VHDL.6 Fundamental of VHDL Design for FPGA All rights reserved /chp

Chapter 2Chapter 2Designing with VHDLDesigning with VHDL

inin MaxPlusII MaxPlusII Environment Environment (1) (1) Step1: An algorithm is coded in VHDL,

ex: lab1.vhd (MaxPlusII=>TextEditor)

Step2: Define MaxPlusII project lab1.vhd &VHDL syntax check(FILE=>Project=>Save&Check)

Step4: MaxPlusII complete compilation ifno syntax error ( press START button)

EE Dept., SJSU 9/6/98 VHDL.7 Fundamental of VHDL Design for FPGA All rights reserved /chp

Define a project

EE Dept., SJSU 9/6/98 VHDL.8 Fundamental of VHDL Design for FPGA All rights reserved /chp

Get Help ???Get Help ???

EE Dept., SJSU 9/6/98 VHDL.9 Fundamental of VHDL Design for FPGA All rights reserved /chp

Simulation for Zero-DelaySimulation for Zero-DelayEvents (FunctionalEvents (Functional Sim Sim.).)

(not in student version)(not in student version)

Select FunctionalSNF Extractor, recompile& simulateNote: only 3 boxes

EE Dept., SJSU 9/6/98 VHDL.10 Fundamental of VHDL Design for FPGA All rights reserved /chp

Designing with VHDLDesigning with VHDLinin MaxPlusII MaxPlusII Environment (2) Environment (2)

Step5: Define simulation waveform(MaxPlusII=>WaveformEditor)

Step6: Simulate (MaxPlusII=>Simulator orFile=>Project=>Save&Simulate)

Step7: Timing Analyze(MaxPlusII=>TimingAnalyzer)

May require iterations until all designspecifications are satisfied

EE Dept., SJSU 9/6/98 VHDL.11 Fundamental of VHDL Design for FPGA All rights reserved /chp

Chapter 3 - ABCs of VHDLChapter 3 - ABCs of VHDL Hardware Behavior & Structure

Two basic questions about hardware:

How does it behave?

What does it consist of? HW behavior: function & timing

HW structure: component, port & signals

In VHDL, a component is represented by the Design Entity

A port is the components connection to the outside

A signal is a connection between components

EE Dept., SJSU 9/6/98 VHDL.12 Fundamental of VHDL Design for FPGA All rights reserved /chp

Design EntityDesign Entity

entity LAB1 is

port(

A, B, C : in BIT;

Z : out BIT

);

end LAB1;

architecture INTERNAL of LAB1 is

begin

Z

EE Dept., SJSU 9/6/98 VHDL.13 Fundamental of VHDL Design for FPGA All rights reserved /chp

EntityEntity

The syntax is: ::=

entity ENTITY_NAME is

end ENTITY_NAME ;

Example

entity LAB1 is

port(

A, B, C : in BIT;

Z : out BIT

);

end LAB1;

ABC

Z

EE Dept., SJSU 9/6/98 VHDL.14 Fundamental of VHDL Design for FPGA All rights reserved /chp

ArchitectureArchitecture

The syntax is: ::=

architecture ARCH_NAME ofENTITY_NAME is

[architecture_declarative_part]

begin

[architecture_statement_part]

end ARCH_NAME

Example:

architecture INTERNAL of LAB1 is

begin

Z

EE Dept., SJSU 9/6/98 VHDL.15 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(1)3 Styles of Design Description(1)

ENTITY LAB1

architecture AR1of LAB1 is

architecture AR2of LAB1 is

architecture AR3of LAB1 is

behavior data flow structure

EE Dept., SJSU 9/6/98 VHDL.16 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(2)3 Styles of Design Description(2)

Behavioral description specifies thearchitecture in an algorithmic way like acomputer program

The Data Flow description utilizes theconcurrent statements

Structural description definesinterconnections of components (previouslycompiled design units)

EE Dept., SJSU 9/6/98 VHDL.17 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(3)3 Styles of Design Description(3)Behavioral DescriptionBehavioral Description

Example:architecture AR1 of COMPARE is

begin

process( A, B)

begin

if (A = B) then

C

EE Dept., SJSU 9/6/98 VHDL.18 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(4)3 Styles of Design Description(4)Structural DescriptionStructural Description

Example: (XORGATE & NOTGATE are previously compiled design units)architecture STRUC of COMPARE issignal I: bit;

component XORGATE port(X, Y: in bit; Z: out bit);end component;

component NOTGATE port(X: in bit; Z: out bit);end component;

beginU1: XORGATE port map( A, B, I);U2: NOTGATE port map(I, C);

end STRUC;

XY Z X Z

I CA

B

EE Dept., SJSU 9/6/98 VHDL.19 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(5)3 Styles of Design Description(5)Data Flow (Concurrent) Description (1)Data Flow (Concurrent) Description (1)

This is a new & abstract idea, so bepatient :-)

Concurrent statements are executed with nodefined order

Concurrent statements are also used forstructural descriptions

They synthesize combinational circuitry

EE Dept., SJSU 9/6/98 VHDL.20 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Styles of Design Description(6)3 Styles of Design Description(6)Data Flow (Concurrent) Description (2)Data Flow (Concurrent) Description (2)

Example:

A

EE Dept., SJSU 9/6/98 VHDL.21 Fundamental of VHDL Design for FPGA All rights reserved /chp

VHDL LibrariesVHDL Libraries A library is a directory of files associated

with previously compiled units

The default library is called WORK,referring to the current working directory

4 main libraries: altera: primitives & TTL 74xxx family

ieee: see VHDL packages (p.21)

std: defines types & text I/O

vital (not popular)

EE Dept., SJSU 9/6/98 VHDL.22 Fundamental of VHDL Design for FPGA All rights reserved /chp

VHDL Packages (1)VHDL Packages (1)

Altera provides several packages for usewith MaxPlusII. They are in sub-dir\maxplus2\max2vhdl.

A package is used to store commonlyreferenced TYPES, CONSTANTs,FUNCTIONs, PROCEDUREs, orCOMPONENTs.

EE Dept., SJSU 9/6/98 VHDL.23 Fundamental of VHDL Design for FPGA All rights reserved /chp

VHDL Packages (2)VHDL Packages (2) Syntax:library LIBRARY_NAME

use LIBRARY_NAME.PACKAGE_NAME.ITEM_NAME

Example:LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY lab2a ISPORT (op1, op2 : IN UNSIGNED(7 downto 0);

result : OUT INTEGER);END lab2a;

ARCHITECTURE adder_maxpld OF lab2a ISBEGIN

result

EE Dept., SJSU 9/6/98 VHDL.24 Fundamental of VHDL Design for FPGA All rights reserved /chp

VHDL Packages (3)VHDL Packages (3)File: Package: Library: Contents:

maxplus2.vhd maxplus2 altera MAX+PLUS II logic functions supportedby VHDL.

std1164.vhd std_logic_1164 ieee Standard for describing interconnectiondata types for VHDL

std1164b.vhd modeling, and the STD_LOGIC and STD_LOGIC_VECTOR types.

arith.vhd std_logic_arith ieee SIGNED and UNSIGNED types, arithmetic and comparison

arithb.vhd functions for use with SIGNED and UNSIGNED types, and the conversionfunctions CONV_INTEGER, CONV_SIGNED, and CONV_UNSIGNED.