A 0.7V Time-based Inductor for Fully IntegratedLow Bandwidth Filter Applications

Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu,Ahmed Elmallah, Romesh Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu

University of Illinois at Urbana-Champaign, Urbana, IL, 61801, USA

Abstract—A time-based gyrator is presented to implement ac-tive inductors in an area efficient manner. Using a ring oscillatorto integrate the input voltage and a switched transconductor toinject current into the input node, the proposed gyrator achievesinductive input impedance without using either large resistorsor capacitors. Realizing the gyrator in this manner makes itamenable for technology scaling. Fabricated in 65 nm CMOSprocess, the inductor operates from a 0.7 V supply voltage andconsumes 528 µW. Measurement results show inductance valuesin the range of 150 µH to 1.5 mH can be achieved.

Index Terms–active inductor, gyrator, VCO, time-domainsignal processing, ring oscillator

I. INTRODUCTION

Technology scaling over the past several decades has helpedto greatly reduce active device dimensions. However, scalinghas not necessarily resulted in similar scaling of passive circuitelements such as the resistor, capacitor, and the inductor,which typically occupy a significant fraction of total chiparea [1]. While resistors and capacitors may have enjoyedsome scaling benefits, density of inductors has by and largeremained the same and as a result they continue to take uplarge fractions of die area. In view of this, the focus of thispaper is to explore active inductor topologies that facilitaterealization of very large inductances without using eitherlarge resistors or capacitors. Specifically, we focus on low-Q inductor applications such as filtering as opposed to powerconversion applications that require very high Q inductors.

Active inductor can be implemented using a gyrator [2],as depicted in Fig. 1(a). It consists of an integrator formed byGMF-C that acts on the input voltage, Vin, and a transconduc-tor GMB, that converts the integrator output voltage to current,Iin. The impedance presented by this circuit is inductive asillustrated by the below equation:

ZG =VIN

IIN=

sC

GMFGMB−→ L̂ =

C

GMFGMB(1)

Ideally, this technique can be used to implement a widerange of inductance values with significantly less area com-pared to a passive inductor. However, in practice, implement-ing large inductance poses many design challenges. First, verylarge capacitor or a very small transconductance is neededto increase inductance. Because minimum transconductanceis limited by the smallest bias current that can be generatedreliably, inductors used in very low bandwidth applicationssuch as EEG, EMG, or EKG signal acquisition systems [3],

(a) (b)

GMF

GMB

C RO,FRO,B

Vin

inI

Vin

α

s

GMB

inI

Fig. 1. (a) Classical gyrator based active inductor and (b) block-levelimplementation of the active inductor.

[4] would require large capacitors and would end up occupyingsignificant area.

Second, finite output impedance RO,F, of the transconductormakes the integrator lossy and the integrator behaves as anamplifier for frequencies below 1/RO,FC [5]. Increasing RO,F

in scaled processes is difficult. Third, linearity of transconduc-tors is severely compromised under low supply voltage, whichlimits useful linear range of the inductor. It is important to notethat despite the appearance of a loop, it suffers from concernssuch as saturation of the integrator.

In view of these challenges, we seek to explore alternateimplementations of the gyrator. We propose to replace GM-C integrator in a classical gyrator with a time-based inte-grator that is immune to many of the aforementioned designchallenges. Using a voltage-controlled ring oscillator (VCO)as the integrator allows to achieve infinite DC gain (losslessintegration) and take full benefit of technology scaling [6].

II. PROPOSED INDUCTOR

A simplified block diagram of the proposed time-basedinductor is shown in Fig. 2. It is composed of two multi-phasevoltage controlled oscillators (VCOIN, VCOREF), a bank ofphase detectors and switched transconductors. Because inputcontrol voltage of the VCO changes its frequency, VCO actsas an ideal voltage to phase integrator [7]. Denoting voltage-to-frequency gain of the VCO by KVCO, integrator transferfunction, HVCO(s), equals:

H(s) =ΦVCO(s)

VIN(s)=

KVCO

s(2)

Therefore, a VCO can be used in the feed-forward path (seeFig. 2) in place of the GM-C integrator to implement a gyrator.

Fig. 2. Block diagram of the proposed active inductor.

To this end, VCOIN output phase is converted to a pulse-width modulated signal by a phase detector (PD) by comparingVCOIN phase with that of VCOREF. Assuming free-runningfrequencies of both the VCOs are equal, pulse width of thePD output is proportional to the phase of VCOIN and can berepresented as:

VPWM =

∫VIN(τ)dτ =

VINKVCOKPD

s(3)

A switched transconductor converts 2-level PD output intocurrent which is then injected into the input node, to makethe input impedance inductive as expressed by the the belowequations:

IGM =VinKVCOKPDGM

s(4)

Vin

IGM

= sL −→ L =1

KVCOKPDGM(5)

Plotting Eq. 5 as shown in Fig. 3, reveals the possibil-ity of realizing large inductors without either using largecapacitors or very small transconductors. While driving thetransconductor with a 2-level PD output makes them inherentlylinear, it also introduces undesirable spurious tones in thevicinity of multiples of FVCO [8]. We seek to suppress thesetones by a using a multi-phase ring oscillator. By taking Mphases out of VCOREF and VCOIN, we generate an M levelVPWM signal, which results in pushing the spurious tonesto M · FVCO,IN [7], where they can be easily filtered. M-level VPWM signal is generated by comparing M phases ofVCOIN with corresponding M phases of VCOREF using Mphase detectors. The M PWM signals are fed to M switchedtransconductors whose outputs are shorted to perform thedesired current summation.

The proposed time-based gyrator suffers from a lower boundon FIN. To elucidate this, consider the case when a sinusoidalsignal with an amplitude of VIN and frequency FIN is appliedat the input. The resulting amplitude of the induced phaseswing equals:

∆ΦIN =VINKVCO

FIN≤ 2π (6)

Fig. 3. Transconductance range compared to maximum inductance for variousKVCO values.

Fig. 4. Required KVCO values for minimum input frequencies across variousinput swings to ensure distortion free performance.

Fig. 5. Phase detector output waveforms, showing the effect of phase detectorsaturation.

∆ΦIN must be smaller than the PD input range, which is2π in our implementation. Exceeding this range will saturatethe PD and the gyrator loses its inductive behavior. Thisrelationship is shown in Fig. 4 for various input amplitude

and frequencies.We have thus far assumed free running frequencies of

VCOIN and VCOREF to be equal. However, in practice, itis difficult to guarantee this in the presence of mismatches.Any offset between FREF and FIN will cause the phaseto accumulate indefinitely, eventually saturating the phasedetector (see Fig. 5). To mitigate this, we propose to frequencylock the two oscillators using a a low bandwidth phase-lockedloop (PLL).

PLL can also be used to alleviate the PD saturation issuedescribed above by setting the PLL bandwidth slightly largerthan the minimum encountered FIN in a given application.When FIN is within the PLL bandwidth, VCOIN ceases tobehave like an integrator resulting in Iin being proportional toVin (ref. Fig. 1(b)). Thus, for signals with frequencies withinthe PLL bandwidth the proposed topology behaves like aresistor. However, when FIN falls outside the PLL’s bandwidth,VCOIN starts to behave as an integrator up until ≈ FVCO/10and the proposed topology behaves like a lossless inductor.

III. BUILDING BLOCKS

A. VCO and phase detector

The VCO is implemented using a 11-stage ring oscillator.Single-ended delay stages are used to minimize area andpower. The number of stages are decided based on the re-quirement to push the PWM tones to at least a decade higher,which requires a minimum of 10 equally spaced phases. Sincea single-ended VCO requires odd number of stages, 11 delaycells are used. Each of the delay stages are implemented asa cascade of 3 inverters and an AC-coupled buffer is used toincrease the swing to full-scale before driving the PD.

Each VCO is tuned through two digitally-controllable cur-rent sources. One source sets the DC bias current to adjust thecenter frequency of the oscillator, while the other source iscontrolled by VIN. Both inputs are tunable by setting a digitalword that controls the number of active fingers for each currentsource. Both the center frequency and KVCO are tunable byover an order of magnitude. The same VCO is used for boththe input and reference oscillators. The reference oscillatoruses a control voltage generated by the PLL instead of VIN.

Outputs of VCOIN and VCOREF are fed to two-state PDsimplemented using two cross-coupled D flip-flops and anXOR-gate as shown in Fig. 6(a). The PD output, VPWM,is proportional to the phase-error, ∆Φ = ΦIN − ΦREF andperiodic with period 2π as shown in Fig. 6(b), resulting ina PD gain of KPD = 0.7/2π V/rad.

B. Switched-GM Cell

Fig. 7 shows the schematic of the switched GM cell. Itconsists of two 4-bit digitally programmable current sourcesI1 and I2, current-steering switches M1 to M4, and cascodecurrent-mirrors M5 to M8. The current-steering switches arecontrolled by the PWM signal VPWM and VPWM. Current-steering is preferred over on-off current sources (ref. Fig. 2)to minimize the current glitch at the output. The strength ofthe GM cell is not only tunable by a 4-bit digital word but

D

D Q

Q

ΦIN

ΦREF

VPWM

VPWM

+Π Φ

(a) (b)

−Π

0.7 V

Fig. 6. Two-state phase detector (a) schematic and (b) transfer characteristic.

I 1

M 1 M 2VPWMVPWM

I 2

M 3 M 4

M 5

M

M

M

VCASC

6

7

8

I GM

VPWMVPWM

Fig. 7. Switched GM cell schematic.

Fig. 8. Schematic of Type-I PLL used to provide bias voltage for referenceoscillator.

also by changing the bias voltage controlling I1 and I2. Thedevices are sized for a peak current of approximately 50 µAper cell. All GM cells have their outputs tied together to forma current summer.

C. Low bandwidth PLL

Fig. 8 shows the type-I PLL used in the proposed archi-tecture to overcome the phase wrapping problem described inSection II. We use a NAND-based phase-frequency detector(PFD) to measure phase error. The corresponding UP andDN signals drive a charge-pump, which is implemented usingthe same switched GM cell described in Section III-B. Theresistor has an externally applied common mode voltage,which combined with the charge-pump current, generates thecontrol voltage driving the PMOS of VCOREF. This sets thefrequency of the reference oscillator equal to the commonmode input oscillator frequency.

Fig. 9. Die photo.

We deliberately use a type-I PLL whose bandwidth is set tothe lowest frequency that the inductor can maintain saturation-free performance. This allows the inductor to “degrade grace-fully”, as the impedance goes from inductive to resistive as thefrequency lowers. We also do not want true phase tracking, asthat would prevent any integration from the input to output ofthe forward path, as the input and reference phases would belocked. While use of a type-II PLL would allow us to havelower bandwidth with the same loop gain, it would come atthe cost of large area. We note that if multiple inductors wererequired on the same chip, for example in applications thatuse filter banks, only a single PLL is required.

IV. MEASUREMENT RESULTS

The time-based active inductor is implemented in 65 nmCMOS technology and occupies an active area of 0.017 mm2.A die micrograph is shown in Fig. 9. The power consumptionat a center frequency of 180 MHz is 528 µW under no loadcondition, of which the time-domain circuitry (two VCOs andPLL) consume 514 µW. The digital control circuits consume 4µW, and the GM cell bias circuits consume 10 µW of power.

Inductor’s performance is measured by putting it in a passiveRLC filter. Demonstrated here is an inductance of 480 µHwith an operating frequency of 180 MHz. Operating at thisfrequency range, the inductor performs as expected for aninput frequency range of 500 kHz to 20 MHz. The inputvoltage swing seen by the inductor is 70 mVpp. A simulatedtransfer function is compared with the measured results in Fig.10. Measurement results show inductance values in the rangeof 150 µH to 1.5 mH can be achieved.

V. CONCLUSION

A time-based gyrator is presented to implement activeinductors in an area efficient manner. Using a ring oscillatorto integrate the input voltage and a switched transconductorto inject current into the input node, the proposed gyratorachieves inductive input impedance without using either largeresistors or capacitors. Realizing the gyrator in this manner

Fig. 10. Measurement and simulated magnitude response of a passive RLCfilter using the proposed inductor of 480 µH.

makes it amenable for technology scaling. Fabricated in 65nm CMOS process, the inductor operates from a 0.7 V supplyvoltage and consumes 528 µW. Measurement results showinductance values in the range of 150 µH to 1.5 mH canbe achieved. We note that our implementation realizes onlya one-port (grounded) inductor, and realizing a true two-portfloating inductor is the future scope of our work.

ACKNOWLEDGMENT

We thank Analog Devices for financial support and BerkeleyDesign Automation for providing the Analog Fast Spice (AFS)simulator.

REFERENCES

[1] P. Kinget, “Scaling analog circuits into deep nanoscale CMOS: Obstaclesand ways to overcome them”, Custom Integrated Circuits Conference(CICC) 2015 IEEE, pp. 1-8, 2015.

[2] T. N. Rao, P. Gary, and R. W. Newcomb, “Equivalent Inductance andQ of a Capacitor-Loaded Gyrator,” IEEE Journal of Solid-State Circuits,vol. 2, no. 1, pp. 32 - 33, Mar. 1967.

[3] Y. Sundarasaradula and A. Thanachayanont, “A 1-V, 6-nW programmable4 th-order bandpass filter for biomedical applications,” in New Circuitsand Systems Conference, 2015 IEEE 13th International, 2015, pp. 1 - 4.

[4] L. Pylarinos and K. Phang, “Low-voltage programmable g m-C filter forhearing aids using dynamic gate biasing,” Digest of Technical Papers.ISSCC, 2005, pp. 1984 - 1987.

[5] Y. Tsividis, M. Banu and J. Khoury, “Continuous-time MOSFET-C filtersin VLSI,” in IEEE Transactions on Circuits and Systems, vol. 33, no. 2,pp. 125-140, Feb 1986.

[6] B. Drost, M. Talegaonkar, and P. K. Hanumolu, “Analog Filter DesignUsing Ring Oscillator Integrators,” IEEE Journal of Solid-State Circuits,vol. 47, no. 12, pp. 3120 - 3129, Dec. 2012.

[7] M. Park, M. H. Perrott, “”A 78 dB SNDR 87 mW 20 MHz bandwidthcontinuous-time ∆Σ ADC with VCO-based integrator and quantizerimplemented in 0.13 µm CMOS”, IEEE J. Solid-State Circuits, vol. 44,no. 12, pp. 3344-3358, 2009.

[8] A. Iwata, N. Sakimura, M. Nagata and T. Morie, “The architecture of deltasigma analog-to-digital converters using a voltage-controlled oscillatoras a multibit quantizer,” IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, vol. 46, no. 7, pp. 941-945, Jul1999.