IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 66, NO. 7, JULY 2019 1119

A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOSPipelined SAR ADC Based on Energy-Efficient

Switching and Shared Ring AmplifierJun-Sang Park , Tai-Ji An , Student Member, IEEE, Gil-Cho Ahn , and Seung-Hoon Lee, Member, IEEE

Abstract—This brief presents an ultra-low-power two-channel12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC)for use in next-generation mobile communications systems.The proposed ADC employs a two-stage pipelined successive-approximation register (SAR) ADC architecture, where the SARADC at each stage determines 5b and 8b, respectively. In thefirst-stage 5b SAR ADC, the switching power consumption issignificantly reduced due to the switching operation by onlya separate digital-to-analog converter (DAC) with a small unitcapacitance, which generates the comparator decision threshold.When this setup is applied to an actual system, the referencevoltage driver of the system is less burdened. Furthermore, theSAR ADC employs a custom-encapsulated capacitor to improvethe limited linearity of a DAC caused by parasitic capacitance.A residue amplifier employs an ultra-low power ring amplifierstructure. The amplifier is shared by each channel to reducenot only the power consumption and die area but also chan-nel mismatches. The prototype ADC in a 28-nm CMOS processdemonstrates a measured differential non-linearity and integralnon-linearity within 1.50 LSB and 2.85 LSB at 12b, respec-tively, with a maximum signal-to-noise-and-distortion ratio anda spurious-free dynamic range of 58.0 dB and 73.7 dB at140 MS/s, respectively. The ADC occupies an active die area of0.202 mm2 and consumes 1.1 mW at a 0.8-V supply voltage,corresponding to a figure of merit of 12.1 fJ/conversion-step.

Index Terms—Analog-to-digital converter (ADC), low power,pipeline, ring amplifier, successive-approximation register (SAR).

I. INTRODUCTION

S INCE the rise of smartphones and tablet PCs, mobiledata traffic has grown explosively. Indeed, with the

upcoming growth of even more advanced smart mobile ter-minals and communications technology, mobile data trafficis expected to accelerate even further moving forward. Tomeet these demands for mobile data traffic, various high-performance communications devices— such as wireless giga-bit alliance (WiGig), worldwide interoperability for microwaveaccess (WiMAX), wireless local area network (WLAN) and

Manuscript received June 19, 2018; revised September 13, 2018; acceptedOctober 16, 2018. Date of publication November 8, 2018; date of cur-rent version June 26, 2019. This work was supported in part by IDECof KAIST, in part by the Ministry of Trade, Industry and Energy andKorea Semiconductor Research Consortium Program for the Developmentof the Future Semiconductor Device under Grant 10080488, and in part byMSIT through the ITRC Program supervised by the IITP under Grant IITP-2018-0-01421. This brief was recommended by Associate Editor J. S. Walling.(Corresponding author: Gil-Cho Ahn.)

The authors are with the Department of Electronic Engineering, SogangUniversity, Seoul 04107, South Korea (e-mail: gcahn@sogang.ac.kr).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSII.2018.2880288

high-speed digital receiver—have increasingly sought outanalog-to-digital converters (ADCs) that can gaurantee bothhigh-speed and high-resolution performance, while maintain-ing low-power consumption and small chip area [1].

With the advancement of process technology, intenseattention has been paid to the development of low-powersuccessive-approximation register (SAR) ADCs based on dig-ital circuits for use in high-speed, high-resolution applications.However, resolution performance is limited by capacitor mis-match and comparator noise, and reference voltage driversconsume much more power than SAR ADCs, making itdifficult to efficiently apply to actual systems [2], [3]. Toovercome the limitations of high-resolution SAR ADCs,research is being conducted on calibrating capacitor mismatch.However, such calibrations require additional time and data.Furthermore, given that mobile systems frequently remainin standby mode to minimize power consumption, this cal-ibration scheme is considered unsuitable for mobile-systemapplications [1], [4], [5].

Recently, research on a pipelined SAR ADC structure,which is able to supplement the major limitations of SARADCs and apply the advantages of pipeline ADCs, is beingconducted extensively [6], [7]. Research on ring amplifiers,capable of significantly reducing power consumption withoutthe use of additional calibration circuits, is drawing substan-tial attention [8], [9]. Having said that, little research has beenpaid to the high-speed and multi-channel operation of ringamplifiers.

The proposed 12b 140 MS/s 28-nm CMOS pipelinedSAR ADC employs a two-channel time-interleaved structureto facilitate high-speed operation. In addition, a two-stagepipeline ADC structure is applied where 5b and 8b areprocessed in each stage. The first-stage 5b SAR ADC isdesigned to reduce switching power consumption. During SARoperation, only a separate digital-to-analog converter (DAC)with a small unit capacitance, which is used to generatethe comparator decision threshold, is involved in the switch-ing operation. This technique makes it possible to designa reference voltage driver with low power consumption for sys-tem applications. Furthermore, a custom-encapsulated capac-itor is employed to improve the limited linearity causedby the adjacent capacitor connections without the need foradditional calibration schemes. With regards to the residueamplifier which is the largest power consuming part ofa typical pipeline ADC, an ultra-low power ring ampli-fier structure is applied. This amplifier is shared by eachchannel of the two-channel structure so that the high-speedoperation requirements are alleviated and the performancedegradation resulting from inter-channel mismatches isimproved.

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1120 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 66, NO. 7, JULY 2019

Fig. 1. Proposed 12b 140 MS/s 28-nm CMOS ADC.

This brief is organized as follows. The overall architec-ture and operation of the proposed ADC are described inSection II. In Section III, the detailed circuit techniques for theproposed ADC implementation are illustrated. The fabricatedand measured results of the prototype ADC are summarizedin Section IV and the conclusion is given in Section V.

II. ADC ARCHITECTURE

The overall structure of the proposed two-channel 12b140 MS/s pipelined SAR ADC based on energy-efficient DACswitching and shared ring amplifier is illustrated in Fig. 1. Theproposed ADC consists of a first-stage 5b SAR ADC, a residueamplifier, a second-stage 8b SAR ADC, a clock generator, anda digital correction logic and decimator.

The first-stage 5b SAR ADC has two different types ofDACs: a two-channel DAC (SIG DAC) which samples andholds input signals and transfers the residue voltages; anda separate DAC (REF DAC) which generates the compara-tor decision threshold [10]. Here, the unit capacitance of theSIG DAC is selected to be 30fF based on its input signal range(1.4VP-P) and kT/C noise. For the REF DAC, 5fF is selectedbased on its signal attenuation and capacitor matching require-ment. The proposed energy-efficient DAC switching methodallows only the REF DAC, paired with a small unit capaci-tance of 5fF, to perform the high-speed switching operations,reducing the overall switching power consumption. By doingso, it is possible to alleviate the design requirements for ref-erence voltage drivers and to make the ADC more suitablefor actual system applications. In addition, the 5b SAR ADCsshare a single comparator which has two pairs of differentialinput stages during SAR operation, improving offset mismatchand power consumption while decreasing chip area.

With regard to a residue amplifier which is the largest powerconsuming part of a typical pipelined SAR ADC, an ultra-lowpower ring amplifier structure is applied to significantly reducepower consumption [9]. This amplifier is shared by each chan-nel of the two-channel structure, reducing the performancedegradation caused by offset and gain mismatches.

With regards to the second-stage 8b SAR ADC, thecommon-mode voltage (VCM)-based switching method isemployed so that a most significant bit (MSB) capacitor,which occupies the largest area in the DAC, is no longernecessary [2]. Furthermore, a C and R-2R hybrid DAC struc-ture is applied to decide the last three significant bits (LSBs)in the DAC, which serves to further reduce the number ofcapacitors [11].

Fig. 2. Timing diagram for the proposed ADC.

The major block operation timing for the proposed 12b140 MS/s ADC based on the energy-efficient DAC switchingmethod and shared ring amplifier is summarized in Fig. 2.

Each channel of the SIG DAC of the first-stage 5b SARADC samples input signals during the one-half cycle of themain clock of 140 MHz (Q1), and performs a holding opera-tion during the subsequent half cycle (Q2). Here, while the SIGDAC performs a holding operation, the REF DAC sequentiallygenerates the comparator decision threshold and conducts SARoperation for the 5b digital code conversion. Upon the com-pletion of SAR operation, each channel of the SIG DAC, inturn, transfers to a residue amplifier the residue voltage thatcorrespond to the resulting converted 5b digital codes duringthe clock cycle of 140 MHz (Q1+Q2). The transffered signalis amplified by the residue amplifier while each channel of thesecond-stage 8b SAR ADC samples alternately the amplifiedresidue voltage.

III. CIRCUIT IMPLEMENTATION

A. Energy-Efficient Switching With Separate Reference DAC

The first-stage 5b SAR ADC based on energy-efficient DACswitching, as shown in Fig. 3, consists of two SIG DACs anda REF DAC. Here, the DACs are characterized by a binary-weighted capacitor structure, and the unit capacitance is 30fFand 5fF, respectively. For the SIG DAC, the input signalsare applied to the bottom plate of the SIG DAC’s capacitorduring the sampling operation, while the VCM is applied dur-ing the holding operation. During the amplification operation,the reference voltage (VREF) combination that correspondsto the converted 5b digital codes is applied. For the REFDAC, the VREF combination generated under the VCM-basedswitching method is applied to the capacitor’s bottom plateduring SAR operation, and the top plate sequentially gener-ates and transfers to the comparator the decision threshold thatis required during the comparison operation.

Previous research papers on SAR ADCs studied casesin which the SIG DAC and REF DAC were used sepa-rately, but the two DACs were designed to ensure inter-DACmatching [10]. In contrast, the proposed pipeline structureallows a margin for inter-DAC matching within the digi-tal correction range equal to 1/2 LSB of the bits deter-mined in the first stage. Meanwhile, the SIG DAC and REFDAC require 12b and 5b accuracy, respectively, similarly toa multiplying DAC and a sub-ADC used in a conventionalpipeline ADC. Therefore, it is possible to apply different num-bers of capacitors and different unit capacitances for each

PARK et al.: 12.1 fJ/CONV.-STEP 12b 140 MS/s 28-nm CMOS PIPELINED SAR ADC 1121

Fig. 3. First-stage 5b SAR ADC with energy-efficient DAC switchingscheme.

Fig. 4. (a) Comparator used in the first-stage 5b SAR ADC and (b) operationexample (D=‘11000’).

DAC. However, a gain mismatch can occur due to the differ-ence of each DAC output parasitic capacitance. To minimizethe gain mismatch of two DACs, the 5fF unit capacitance ofthe REF DAC is determined to be the desirable value consid-ering the parasitic components of both DAC outputs and thetotal capacitance of the SIG DAC.

In the proposed ADC, the achievable maximum first-stageresolution was simulated and verified to be 5b considering theadjustable gain mismatch range of two DACs and its errorcorrectable range.

The comparator, which serves to perform the SAR opera-tion of the first-stage SAR ADC and thus requires only 5baccuracy, is designed to have a double tail structure with twopairs of differential input stages, as shown in Fig. 4(a) [12].These input stages receive respective signals from the SIGDAC and REF DAC. In Fig. 4(b), an example of the sam-pling and conversion operations is shown. Here, input signalsare sampled by the SIG DAC and held on both the INT andINC. Simultaneously, the REF DAC sequentially generates thecomparator decision threshold according to the digital codedetermined by the SAR operation, and the decision thresholdis applied to both the REFT and REFC.

Fig. 5 compares the switching energies of the proposedenergy-efficient DAC switching method and the conventionalVCM-based switching applied to a capacitor array with thesame structure as the SIG DAC. In the proposed switchingmethod, the overall capacitance of the high-speed operating

Fig. 5. Switching energy comparison of the proposed scheme with the VCM-based switching applied to the SIG DAC structure.

REF DAC is one-twelfth that of the SIG DAC. Therefore, theaverage switching energy is reduced by 92%. When appliedto an actual system, such technique will be able to also reducethe power consumption and chip area of its reference voltagedrivers.

B. Highly Linear Custom-Encapsulated SAR Capacitors

In the present study, the first-stage SIG DAC and REF DACemploy a custom-encapsulated capacitor structure to reducethe parasitic capacitance between the top plate and bottomplate, which degrades linearity when the capacitor array isarranged, as shown in Fig. 6 [13]. As such, it is possible tominimize the parasitic capacitance and ensure high linearitywithout the need for additional calibration schemes.

Top views of the proposed capacitor are shown inFig. 6(a), (b). In the encapsulated capacitor structure, M6 andM5-3 are arranged such that they serve as the top plate andbottom plate in turn, achieving the required capacitance [14].The outermost layers of the capacitor are designed such thatthe bottom plates shield the entirety of the encapsulated capac-itors. In the case of M6, the top plate of one capacitor canbe connected to those of its adjacent capacitors (up, down,left and right) by opening part of the bottom plate of eachcapacitor’s outermost layer. In addition, as shown in the ABcross section in Fig. 6(c), M2 and M7 serve as bottom plates,shielding the top and bottom parts of the capacitor. When thecapacitors are arranged as shown in the side view in Fig. 6(d),the top plates of the adjacent capacitors are connected via M6,while the bottom plates are connected via M1.

The proposed shielding capacitor structure makes it possibleto achieve the required capacitance and alleviate the linearitydegradation caused by the parasitic capacitance occurring fromthe connections between adjacent capacitors. Based on thisstructure, the unit capacitors of 30fF and 5fF are produced byadjusting the length of the metal parts, and each of them isapplied to the SIG DAC and REF DAC.

C. Ultra-Low Power Ring Amplifier With Minimized Offsetand Gain Mismatches Between Channels

To significantly reduce power consumption, a ring ampli-fier structure, as shown in Fig. 7, is applied to the residueamplifier of the proposed ADC [9]. The two-channel structureof the proposed ADC reduces the settling time requirementof the ring amplifier to a single clock cycle of 140 MHz,thus facilitating high-speed operation. This ring amplifier isshared by each channel of the two-channel structure so thatperformance degradations from the offset and gain mismatchesbetween each channel are reduced, as are power consumption

1122 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 66, NO. 7, JULY 2019

Fig. 6. Highly linear custom-encapsulated capacitors: (a) top view of M6,(b) top view of M5-3, (c) AB cross section, and (d) side view.

Fig. 7. Shared very low-power ring amplifier.

and chip area. The proposed ring amplifier has three-stageinverter circuits of differential structure. The first stage iscomposed of two pairs of inverter circuits, which receive theresidue voltages of each channel in the first-stage 5b SARADC, respectively [15]. The two pairs of inverter circuits inthe first stage repeat the amplification operation and reset oper-ation in turn during the single clock cycle of 140 MHz. Thesecond-stage and third-stage inverter pairs are connected dur-ing the amplification operation of the first stage, and performamplification operations continuously.

IV. PROTOTYPE ADC MEASUREMENTS

The prototype 12b 140 MS/s ADC is implemented in a 28-nm CMOS technology. The ADC occupies an active diearea of 0.202 mm2 and its overall layout and die photo areshown in Fig. 8. It consumes 1.1 mW at 140 MS/s with

Fig. 8. Layout and die photo of the prototype 12b 140 MS/s 28-nm CMOSADC.

Fig. 9. ADC power breakdown.

Fig. 10. Measured DNL and INL of the prototype ADC.

Fig. 11. Measured FFT spectrum of the proposed ADC (1/7 fs downsampled): (a) fin = 1.1 MHz and (b) fin = 70.1 MHz.

a 0.8-V supply voltage. Fig. 9 shows the power breakdownof the ADC.

The measured differential non-linearity (DNL) and inte-gral non-linearity (INL) are within 1.50 LSB and 2.85 LSB,respectively, as shown in Fig. 10.

The measured FFT spectrums at 140 MS/s with 1.1 MHzand 70.1 MHz sinusoidal inputs are shown in Figs. 11(a)and (b), where there is no harmonic tone at fs/2 of

PARK et al.: 12.1 fJ/CONV.-STEP 12b 140 MS/s 28-nm CMOS PIPELINED SAR ADC 1123

Fig. 12. Measured SFDR and SNDR performance of the prototype ADCversus (a) fs and (b) fin.

Fig. 13. Measured SNDR versus power supply voltage.

TABLE IPERFORMANCE COMPARISON OF RECENTLY REPORTED ADCS

140 MS/s. This means that the offset and gain mismatchesbetween two channels are effectively eliminated by the vari-ous analog circuit sharing techniques applied. The signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamicrange (SFDR), as illustrated in Fig. 12(a), are measured withsampling rates ranging from 20 MS/s to 140 MS/s at a differ-ential input frequency of 1.1 MHz. When the sampling rateincreases to 140 MS/s, the SNDR and SFDR are maintainedabove 58.0 dB and 73.7 dB, respectively. Fig. 12(b) shows theSNDR and SFDR variations with increasing input frequenciesat a sampling rate of 140MS/s. When the input frequency isincreased to the Nyquist frequency, the measured SNDR andSFDR remain at above 52.6 dB and 65.7 dB, respectively.The measured SNDR as shown in Fig. 13 with a 1.1 MHzinput frequency at 140 MS/s remains higher than 57.3 dBover a power supply voltage range from 0.7-V to 0.9-V.

Our analysis of the somewhat poor static and dynamic per-formances shows that the required second-stage 8b SAR ADCperformances could not be met due to a layout problem inthe reference voltage line. These performance degradations areirrelevant to the proposed techniques in the previous section,and the revised version is being built.

Table I shows a comparison between the proposed prototypeADC and recently reported ADCs of similar specifications.

A figure of merits (FoM), defined as (1), of the proposedADC are 12.1 and 22.5 fJ/conversion-step for 1.1 MHzand Nyquist inputs, respectively, which are compared to therecently reported ADCs of similar specifications.

FoM = POWER

fs × 2ENOB. (1)

V. CONCLUSION

A prototype ADC based on an energy-efficient DACswitching method and ultra-low power ring amplifier is pro-posed in the present study. These proposed techniques havebeen found to significantly reduce power consumption. Inaddition, the application of a custom-encapsulated capacitorstructure makes it possible to reduce the linearity degradationcaused by parasitic components when the capacitor arrayis arranged. The measured results show the proposed ADCconsumes 1.1 mW at a supply voltage of 0.8-V, and themaximum SNDR and SFDR at an operation rate of 140 MS/sare 58.0 dB and 73.7 dB, respectively.

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