a 2.4 ghz cmos low noise amplifier using an inter-stage matching inductor

8/10/2019 A 2.4 GHz CMOS Low Noise Amplifier Using an Inter-stage Matching Inductor

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A 2.4GHz CMOS Low Noise Amplifierusing an Inter-sta.ge Matching Inductor

Hong-Sun Kim, Xiaopeng Li, and Mohammed Ismail, Fellow IEEEDepar tment of Electrical Engineering

The Ohio State University

Columbus, OH 43210 USA{kimho , ixp, ismail} @ee.eng Ohio-st at e.edu

Abstract-A 2.4GHz CMOS Low Noise Ampli-fier LNA) design is presented in this paper. A con-ventional cascode LNA struc ture is used with an nter-stage matching inductor. Th e two transistors of thecascode structure are considered as two individualstages. The off-chip inter-stage m atching inductor isinserted between two stages. Using this meth od, over-all gain can be increased and the noise figure of theLNA can be decreased.

I. INTRODUCTION

Fast growth of personal communication market highlydemands to produce low cost and low power transceiversfor wireless applications [l]. A Low Noise Amplifier(LNA)is the most critical block to determine sensitivity of a com-munication system [2]. Conventionally GaAs and Bipolartechnologies are used t o implement the LNAs [3][4][5]

Thanks t o development of CMOS technology, it is pos-sible to implement GHz R and microwave circuits withsub-micron CMOS technologies. Th e CMOS technology

has a merit to be combined with digital circuitries. Thus ,CMOS LNAs have been extensively investigated in several

The cascode structure has been widely used for LNAdesigns because it is easy to satisfy both noise and powergain requirements [8]. However, the matching betweenthe common-source stage and the common gate stage isoften less emphasized in the analysis of the cascode topol-ogy. In order to achieve good isolation, the output of thecommon-source stage should be considered carefully. Thispaper shows the importance of the mathing between twostages. By inserting an inter-st age matching inductor, theperformance will be improved significantly.

The design procedure of the cascode LNA using aninter-stage matching inductor will be presented in the firstsection. A 2.4GHz LNA is exampled using the presentedprocedure in the section 1. Finally the last section sum-merizes the performance of the LNA and concludes thepaper.

papers PI[71PI.

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Figure 1. A Simplified LNA structure with aninter-stage inductor

A simplified LNA structure with an inter-stage induc-tor is shown in Figure 1 . An inter-stage inductor(l,)is added between the common-source stage and thecommon-gate stage. Th e inter-stage inductor, t he outputinductor(l,,t), and the output capacitance(COut) are thee.xternal components. The input and output impedanceare both ::wed to be 50R.

- - - Cout

Win0

iI

Zin2zin 1Figure 2 . Two-Stage Design Strategy

-4pplying small signal analysis of t he common-gatestage, the LNA can be divided into two stages(Figure2). Because of high isolation of the common-gate stagebetween input and outpu t, the o utput matching networkcan be designed separately. Let us consider the inputmatching network of transistor 111 first. By neglecting

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Miller effect of gate-drain capacitance(C,dl) of MI theinput impedance of Ml can b e given by [a]

where gml and Cgsl re the transconductance and the

gate- source capacitance of MI respectively. L and L arethe gate input inductor and source degeneration inductor.In order to match the input impedance(R,), the real partof the equation (1) should be matched to R and theimaginary part of the equation (1) should be cancelledout. These matching criteria gives

and1

where W is the operating frequency.MOS transistor Noise Figure equation can written by

PI

where y is in the long channel theory. It is known thatthe value is higher than in the sub-micron technol-ogy [9]. Under the condition that the drain current isconstant, we can write the transconductance of the tran-sistor Ml(gml) to be J ~ I D , L L C ~ ~ W ~ / L ~ .he Cssl anbe also written by W1 LIC oz. When we differentiate theequation (4) in terms of W 1 we can find out the opti-mum size of the trans istor M I to generate minimum noisefigure, which is given by

5)12 WoRsLiCoz'

1,min =

The obtained value from the above equation does notmatch the designed size of the transistor because the par-asitic gate resistance R, and t he parasit ic overlap capac-itances are neglected. However, the ob tained value fromthe equation 5 ) can be used as an initial value for thesize of the MI transistor. Accurate simulation is requiredto obtain good noise figure, isolation, and s tabil ity factorsimultaneously.

The second step is to design the common-gate stage.The common-gate input impedance can be given by

6)1Zin2 =gm2 + w c g s 2

In the traditional cascode LNA design no matching hasbeen considered between the common-source stage andthe common-gate stage . Thi s is not desirable for themaximum power transfer. Loss of power directly affects

the noise performance of the LNA. Since both the in-put impedance of the common-gate stage and the out-put impedance of the common-source stage are capaci-tive, a series off-chip inductor La is included to improvethe matching. Since the gain is improved by adding theadditional inductor, the Miller capacitance effect will bemore significant in the first stage. Again, accurate sim-ulation should be required to adjust the input matchingnetwork of the LNA. Because of good power transfer inthe common gate stage, the overall noise figure will bedecreased.

The final procedure of the LNA design is to determinethe out put matching network. The stability and the lin-earity should be considered carefully at this stage. If theperformance is not satis factory, we may go back to thefirst st age t o optimize th e LNA performance.

111. A 2.4GHz LNA DESIGN

C b i a s L ~

] a

Figure 3. 2.4GHz LNA with Bias Circuitry

Figure 3 shows the complete 2.4GHz LNA using theinter -stage matching induc tor. Rbl , RbZ, M 3 and M4provide the biasing of the LNA. The resistor Rbl sets thecurrent of the bias circuitry, which generates the bias volt-age at the gate of the transistor M I . The resistor Rb2prevents the input signal from flowing into the bias cir-cuitry. The capacitance C b i a s provides the AC ground atthe gate of the transistor M2. Th e value. of shouldbe large enough so that the capacitance does not affectthe LNA performance too much. Lout and Gout form theoutput matching network.

L, and L, are implemented by combination of on-chipspiral inductors and bond-wire inductors. Because L, andL are realized by on-chip spiral inductors, the parasiticresistance will affect the noise performance significantly.The value of L, is chosen about 2 n H , which can be eas-ily implemented by a high Q bond wire inductor com-bining with an on-chip spiral inductor. According to the

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equation 3), the M I transis tor size(W1) is chosen 600pm.We can obtain the optimized load impedance of the firststage(&). From the obtained the value of Z 2 wecan determine the size of the transistor M z W z ) ,whichis 500pm.

La is implemented by an off-chip inductor which givesus several advantages. First we can avoid large parasitic

capacitance. Second, it is good for noise performance.Using the theory of Miller capacitance, La can introducea negative resistance at the input port , which can improvethe noise performance. Third, we can have some flexibilitywhich enables us to t une the circuit after fabrication.

Figure 4 shows simulat ion results of 5'11, the power gain,and the noise figure versus frequency by sweeping the val-ues of La. For the range of 0 - 5 n H La he power gainis improved by 4dB, and noise figure is decreased from3.4dB to 2.5dB. When we increase La we notice that theinput reflection coefficient becomes worse. This is becausethe negative resistance by the Miller capacitance of Cgdipartially decreases the input resistance. Considering all

the three parameters together, 5nH would be the bestchoice for the La.

IV. CONCLUSION

The procedure of R F Low Noise Amplifier is presentedin this pape r. As an example, a 2.4GHz Low Noise Am-plier is designed and simulated. The result of the LNAis summerized in the table 1. The inter-stage matchinginductor is added to the basic cascode LNA structure. Us-ing the inter-stage off-chip inductor, we can achieve high

gain as well as good noise figure.

10

55................+ +

.... ... . +.>..?. ?.. .+ . .+ . ..., c . *...,. . + . . + ..+..

L:=ZSnHi,S.OnH

L,=7.5nH

L,=lOnH

2 4 2 41 2.42 2 43 2 44 2 45 2 48 2 47 2 48Requency GHI)

20

i J. . . . .

. a x I ; i *j l * I P .

. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .I * a ~ . . x. j .:.

I

0 0 0 9 0 0

~ . . . . . . .

+ + + + + +. . . . . . . . . . . .

0 0 0 0

+ + + +

0 0

L,S.OnHL,=7.5nHL,=lOnH

+ + - + + + + +

26

I24 241 242 243 2 4 4 245 2 4 6 2 4 7 2 4 8

requency GHz)

Figure 4. 2.4GHz LNA Results(a) Sll vs. Frequency, (b) Power Gain vs Frequency,

c) Noise Figure vs. Freqilency

Table 1. 2.4 G-Hz LNA Simulation Resul ts Summary1-Process 0.5um CMOS

Supply Voltage I 3vFreqiiency Range 2.4 - 2.48GHz

-10dB2.4dB

4 1

Nciise Figure

ACKNOWLEDGMENT

The authors acknowledge Texas Instruments Inc., Dal-las, TX for supporting this work, and also thank Prof.Filanovsky for h.is valuable suggestions.

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REFERENCES

[I] T. Mank u, Microwave CMOS-devices a nd circuit s, Proc. ofthe IEEE 19 98 Custo m Integmted Circuits Conference, pp.59-66.

[ 2 ] B. K. KO and K. Lee, A New Simultaneous Noise and In-put Power Matching Technique for Monolithic LNAs UsingCascode Feedback, IEEE Ran. on Microwave Theory andTechniques, vo1.45, No.9, pp.1627-1630, Sept . 1997.

[3] E. Heaney, F McGrath, P. OSulIivan, and C. Kermarrec, Ul-tra Low Power Low Noise Amplifiers for Wireless Communi-cations, G a A s Symposium pp.49-51, October 1993.

[4] R. G. Meyer and W. D. Mack, A 1-GHz BiCMOS RF Front-End IC, IEEE Journal of Solid State Circuits, vo1.29, No.3,

[5] R. G. Meyer, W. D. Mack, and J. Hageraats, A 2.5-GHzBiCMOS TYansceiver for Wireless LNAs, IEEE Journal ofSolid State Circuits, vo1.32, No.12, pp.2097-2104, Dec. 1997.

[6] A . Rofougaran, J. Chang, M. Rofougaran, and A. Abidi, AlGHz CMOS RF Front-End IC for a Direct-Conversion Wire-less Receiver, IEEE Journal of Solid State Circuits, vo1.31,

[7] A. Karanicolas, A 2.7V SOOMHz CMOS LNA and Mixer,IEEE Journal of Solid State Circuits, vo1.31, No.12, pp.1939-1944, Dec. 1996.

8j D . Shaeffer and T. H. Lee, A 1.5V, 1.5GHz CMOS Low

Noise Amplifier, IEEE Journal of Solid State Circuits, vo1.32,No.5, pp.745-759, May 1997.[9] A. A . Abidi, High-Frequency Noise Measurements on FETs

with Small Dimensions, IEEE Tkan. on Electron Devices,

pp.350-355, March 1994.

N0.7, pp.881-889, Jul y 1996.

VOI.ED-33, N0.11, pp.1801-1805, NOV. 1986.

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a 2.4 ghz cmos low noise amplifier using an inter-stage matching inductor

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