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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2016.16.3.274 ISSN(Online) 2233-4866

Manuscript received Jul. 13, 2015; accepted Mar. 3, 2016 College of Information and Communication Engineering, Sungkyunkwan University Corresponding Author : Kang-Yoon Lee HYPERLINK "mailto:[email protected]"[email protected]

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-

Interleaved Flash-SAR ADC in 0.13 µm CMOS

Sunghun Cho, DongSoo Lee, Juri Lee, Hyung-Gu Park, YoungGun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Cheon-Seok Park, and Kang–Yoon Lee

Abstract—This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm2. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA. Index Terms—VCSEL driver, automatic power calibration, automatic magnitude calibration, Flash-SAR ADC, multi-rate

I. INTRODUCTION

The increase in the demand for high-speed access networks has led to the recognition of a low-cost passive optical network (PON). Recently, the time and wavelength division multiplexing (TWDM) PON and

point-to-point wavelength-division multiplexing (PtP-WDM) architecture with centralized vertical-cavity surface-emitting laser (VCSEL) at the optical line terminal (OLT) has emerged as an attractive solution for low-cost implementation.

For low cost optical communication application with the data rate of over several Gbps, the CMOS technology can provide a high level of integration and be adopted in the analog VCSEL driver. In particular, the VCSEL driver needs to perform the power and magnitude calibration in a very short time with low power.

In this paper, VCSEL driver structure that can do the fast output power control through the digital calibration and minimize the power consumption is proposed. Also, it can be widely applied to various optical communication systems.

Fig. 1 shows the next generation PON2 (NG-PON2) system utilizing WDM and time division multiplexing (TDM) methods to assign a private wavelength between the OLT and optical network unit (ONU). It needs to

1

N

Fig. 1. NG-PON2 System.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 275

support the PtP-WDM and TWDM-PON through a time division system [1, 2].

The aim of the system is to achieve low power consumption and low chip cost utilizing the newly highlighted VCSEL driver related technology available in terms of size, efficiency, and cost.

As shown in Fig. 1, the transmitter requires the burst mode data transmission capability for the TWMD-PON system in the upstream direction. Thus, the VCSEL driver needs to implement the continuous and burst modes for PtP-WDM and TWDM-PON systems, respectively.

At the PtP mode, the output power of the VCSEL driver should be remain constant with respect to the variations in the process, voltage, and temperature (PVT). The automatic power and magnitude calibration are implemented for the constant output power. External monitoring photo diodes (MPDs) are adopted to monitor the output power of the VCSEL diode in the conventional automatic power and magnitude calibration, which increases the system cost and area [4, 5].

On the other hand, the VCSEL driver with the fast settling time is necessary at the burst mode. In this paper, an automatic power, magnitude, and calibration (APMC) method is proposed to support the continuous and burst modes without the expensive external MPDs.

For the fast settling time of several hundred nano-seconds, the high-speed, fine resolution 10-bit time-interleaved Flash-SAR ADC is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption.

Furthermore, the power consumption is optimized depending on the data rate by the proposed APMC method. It automatically determines the optimal current of the VCSEL driver to implement the multi-rate VCSEL driver.

This paper is organized as follows. Section II and III describes the architecture and building blocks including VCSEL driver core, automatic power and magnitude calibration and ADC, respectively. Section IV shows the experimental results from implementation of a 0.13 μm CMOS and section V concludes the paper.

II. ARCHITECTURE OF VCSEL DRIVER

Table 1 shows the requirements of the 10-Gb/s 4-

channel VCSEL driver. The -3 dB bandwidth and gain need to be over 8.5 GHz and 10 dB, respectively. The output power current should be controlled from 5 mA to 20 mA with the fine resolution of 0.1 mA.

The output power of the VCSEL diode is strongly sensitive to temperature and aging. Therefore, the output current through the VCSEL diode must be controlled to keep the constant output power. The automatic power control (APC) and automatic magnitude control (AMC) loop can be implemented to control the output power. In order to monitor the optical output power and extinction ratio of the VCSEL diode, external monitoring photo diode (MPD) and internal high-speed circuit are required [6]. In this scheme, the current through the MPD is detected by the internal transimpedance amplifier (TIA), which increases the die area, cost, and power consumption. Thus, the APC/AMC loop without the TIA and external MPD is proposed in this paper.

Fig. 2 shows a block diagram of the proposed 10-Gb/s VCSEL driver. It comprises a pre-driver, the main driver and an APC/AMC loop. The APC/AMC loop consists of a common mode detector (CD) and peak detector (PD), multiplexers (MUXs), control finite state machine (FSM), a tuning controller, comparator (Comp.) and 10 bit ADC which is composed of a 4-bit flash and 6-bit SAR. The operations for APC and AMC are performed digitally by the tuning controller. Thus, it can reduce the settling time and die area compared with the conventional analog controlled APC and AMC loop [10, 13]. In addition, the proposed APC/AMC control block architecture uses one 10-bit ADC and tuning controller per 2-channel in the time interleaved way. Thus, the current consumption and area are greatly reduced. The common mode (CM) voltage and voltage swing at the output of the VCSEL diode are detected by the CD and PD for the APC/AMC

Table 1. Specification of VCEL Driver

Parameter Requirement Maximum Data rate 10-Gb/s

Bandwidth (@3 dB) & Gain 8.5 GHz, 10 dB Numbers of channel 4

Technology 0.13 μm CMOS Supply Voltage 1.2 V/ 3.3 V

Modulation/Bias current 5 ~20 mA Output Current Control Resolution 0.1 mA/step

Jitterp-p 20 ps Burst /PtP Mode settling time 30 ns/700 ns

276 SUNGHUN CHO et al : A 4-CHANNEL MULTI-RATE VCSEL DRIVER WITH AUTOMATIC POWER, MAGNITUDE …

loop. The 10-bit ADC converts the CM voltage and amplitude into digital codes, and the tuning controller determines DIG_APC<9:0> and DIG_AMC<9:0>, based on the digital information with a TDM method, respectively. The control resolution of APC and AMC can be fine due to the high resolution, high speed 10-bit ADC. The tuning controller determines whether the sampling is the CM or PD. The FSM is a sequential digital circuit state change. The control FSM selects 0 or 1 of MUX in accordance with the timing, and the CD or PD out values is the input of 10-bit ADC. The converted 10-bit digital code from the ADC and reference 10-bit code compare each other and operate the APC/AMC loop, which is close to the reference value via the tuning controller.

The proposed VCSEL driver can support both the PtP and burst modes. At the PtP mode, the data is transmitted continuously with the constant power by the APC and AMC loop. As the operating time of the VCSEL driver increases, the temperature of the VCSEL diode will rise and the current through it will be reduced. Thus, The APC and AMC loop should compensate for the current variations. When switching to the burst mode through serial peripheral interface (SPI) control, it needs to

change the mode in a very short time to achieve the faster settling time.

Burst mode is used to achieve the high data rate by transmitting the data into four channels simultaneously. In the burst mode, the APC and AMC loops are turned off and the DIG_APC <9:0> and DIG_AMC <9:0> values are kept as the previously calibrated values in the PtP mode. Therefore, the additional calibration is not needed and the data can be transmitted with a minimum settling time. It is important to minimize the settling time for efficient up-stream transmission.

Fig. 3 shows the timing diagram of the proposed VCSEL driver. The overall timing diagram in PtP mode switches to burst mode. ‘Ton’ refers to the time for the VCSEL diode to turn on. When the burst EN signal is received, the VCSEL diode turns on in burst mode. After the signal detection time for detecting the signal of the VCSEL diode, the data is transmitted at high speed.

Burst mode does not give enough time for APC/AMC 10-bits to recalibrate, since a short settling time is required.

Therefore, the APC and AMC loop are turned off while maintaining the APC/AMC bits calibrated in PtP mode. Toff denotes the time that the VCSEL driver turns off.

DIG

_APC

<9:

0>1C

h

CD

10b

it <

9:0>

or

PD

10b

it <

9:0>

MU

X_SE

L1

MU

X_SE

L2

DIG

_AM

C <

9:0>

1Ch

REF

_CLK

AD

C_E

OC

AM

C R

ef,

APC R

ef

APC1_

CAL

APC2_

CAL

AM

C1_

CAL

AM

C2_

CAL

APC/AMC Loop

Fig. 2. Top block diagram of VCSEL driver.


III. CIRCUIT DESCRIPTION

1. VCSEL Driver Core Fig. 4 is a schematic of the VCSEL driver core

composed of a pre driver and main driver. The pre driver and main driver are designed with a

1.2 V device and 3.3 V device, respectively to achieve the maximum data rate of 10 Gbps optimizing the power consumption. The pre driver increases the speed as much as possible and the main driver achieves a sufficiently

large voltage swing. However, when designing the pre driver stage and main driver with 1.2 V devices and 3.3 V devices, respectively, the input metal–oxide–semiconductor field-effect transistors (MOSFETs) of the main driver cannot be fully turned on. Therefore, the supply voltage of 2.5 V is applied to the pre driver instead of 1.2 V.

However, since the 1.2 V devices cannot withstand the supply voltage of 2.5 V, cascode devices, M4 and M5, are stacked above the input transistors, M1 and M2, to reduce the voltage across the input transistors.

Fig. 3. Timing diagram of proposed VCSEL driver.

M2M1

VDD = 2.5V

R2

VB1

R3

M3

VDD = 3.3V

Data In

M8M7

M9

M11

VB1 VB1

M10

M12 M13

VCSEL Driver Out

1.2V Device

R1

M7

VB1 VB1

M6

M8 M9

3.3V Device

M5M4

APC DIG_APC<9:0>

AMC

DIG_AMC<9:0>

External VDD = 3.3V

C2C1

L2

L1

Multi rate Cont.<1:0>

Bias Cont.<1:0>

Negative Impedance Circuit

Negative Impedance Circuit

Data Inb

Pre Driver Main Driver

Multi rate Cont.<1:0>

Pre Driver Out

Pre Driver Outb

Fig. 4. Schematic of VCSEL driver core.


The VCSEL driver core is designed with a two-stage architecture composed of the pre driver and main driver to increase the bandwidth. A negative impedance circuits (NIC) and inductor peaking using L1 and L2 are proposed in the main driver for a sufficiently wide bandwidth by compensating for the parasitic capacitance loading at each stage as much as possible. Thus, the NIC are placed between the pre driver and main driver as well as at the last stage to compensate for the parasitic capacitances. The impedance of the NIC can be calculated as Eq. (1). If the gate-drain capacitance of M6 and M7 are neglected, the impedance seen on the drain side is explained as:

( )m gs c

NICc m gs

g s C 2C1ZsC g sC

+ += -

- (1)

where ZNIC, gm, Cgs and Cc represent the negative impedance, transconductance of M6 and M7, and coupling capacitance, respectively. Also, this is applied to M10 and M11 [4]. Using inductors L1 and L2, the overall bandwidth of the VCSEL driver core can be increased by the peaking in the magnitude response around the signal bandwidth [3, 11]. Also, balancing the differential signals is achieved by using a dummy load, R3.

The main driver provides sufficient current to the VCSEL diode, guaranteeing enough bandwidth. The supply current and transistor sizes of the main driver are optimized in order to minimize the parasitic capacitances.

In order to optimize the power consumption for the required data rates, the variable current source and resistor array controlled by Multi_Rate_Cont<1:0> are implemented in the pre driver.

2. Automatic Power and Magnitude Calibration

The APC and AMC loops in Fig. 2 are used to

automatically control the output power of the VCSEL driver. The proposed APC and AMC control block uses one 10-bit ADC and tuning controller per 2-channel with a TDM method, reducing the current consumption and area. The output of the VCSEL driver can be detected using a CD and peak PD. The CD and PD sense the common mode voltage and swing of the VCSEL driver CM, respectively.

The sensed value from the CD and PD are transferred to the 10-bit ADC through the MUX. Depending on the

MUX_SEL signal, the 10-bit ADC converts the output of the CD and PD value into the digital code, respectively. Finally, the tuning controller determines the 10-bit values, DIG_APC<9:0> and DIG_AMC<9:0> for APC and AMC of the VCSEL driver.

Fig. 5 shows the timing diagram of the APC and AMC controller block. After the initialization by the RESET signal, the APC and AMC processes are started. The tuning controller determines the timings for the digital signals such as MUX_SEL1, MUX_SEL2 and ADC_SOC, etc. through the control FSM. The detected voltages at the duration of MUX_SEL1, MUX_SEL2 are converted into the corresponding digital codes by the triggering of the ADC_SOC signal. The ADC_EOC signal is generated when the output codes of the ADC are available, triggering the AMC1_CAL, AMC2_CAL, APC1_CAL, and APC2_CAL for the APC and AMC calibration.

3. ADC

Fig. 6(a)-(c) show the overall block diagram of the 10-

bit time-interleaved flash SAR ADC (10-bit ADC), 6-bit SAR ADC and output merge block, respectively.

Fig. 6(a) and (b) show the overall block diagram of the 10-bit time-interleaved flash SAR ADC and detailed 6-bit SAR ADC block, respectively.

Among the many types of ADCs, the SAR ADC is used widely because of its advantages of low power consumption and simplicity. However, its conversion speed is limited by the drastic increase of the capacitor value in the high-resolution application. On the other

Fig. 5. Timing diagram of APC and AMC Controller.


hand, the flash ADC, having the highest conversion speed among many types of ADCs, has great power consumption and a substantial chip area.

Thus, a 10-bit time-interleaved flash SAR ADC architecture with the low power of an SAR ADC and the fast conversion speed of the flash ADC is proposed in the paper. In addition, the shared multiplying DAC (MDAC) is added to minimize the increase in the capacitance

value. The proposed time-interleaved flash-SAR ADC consists of a sample and hold, 4-bit flash ADC, MDAC, time-interleaved 6-bit SAR ADC, MUX, and output merge block.

Fig. 6(c) shows the block diagram of the Output Merge Block of the MSB 4-bit and LSB 6-bit. This block combines the MSB 4-bit and LSB 6-bit value through the Flip-Flops and MUXs, respectively. The MSB and LSB bits are processed by using the SOC signals (SOC<6:1>) and EOC signals (EOC<6:1>) from the Time Interleaving Controller as the clocks of the Flip-Flops and selection signals of the MUXs, respectively.

After the flash ADC decides the MSB 4-bit codes from 4-bit Flash ADC, these codes can be used in MDAC. Using these MSBs, the coefficient k is decided from 0 to 15/16, and calculated with an analog input VIN.

Lastly, by multiplying the residue value by 24, the MDAC output is generated in accordance with Eq. (2).

IN REFMDAC_OUT 24(V - K V )= × (2) After the MDAC OUT is made, it is delivered to the

input of the 6-channel SAR ADC and used to determine the remaining LSB 6-bit.

Fig. 7 shows the timing diagram of the proposed 10-bit time-interleaved flash SAR ADC. The duty cycles of the REF_CLK/2 and the start of the conversion (ADC_SOC) signal are 50% and 25%, respectively, with a frequency of 10 MHz.

When the ADC_SOC is high, the sample and hold circuit in the ADC samples the analog input signal, VIN. On the other hand, when the ADC_SOC is low, the Sample & Hold circuit maintains the sampled signal VIN, and the front-end 4-bit flash ADC determines 4-bit MSBs.

The MDAC takes these 4 bits and sampled analog input signal to generate the residue. After the residue process, the back-end 6-bit SAR ADC takes the output voltage of the MDAC and starts its conversion, which determines the 6-bit LSBs. At the same time, the front-end 4-bit flash ADC samples the new analog input voltage. The latency of this architecture is seven clock cycles. Therefore, the output code of the 4-bit flash ADC should be maintained for six clock cycles and merged with the output code of the back-end 6-bit SAR ADC.

SOC

<6:1

>

EOC

<6:1

>

(a)

(b)

FLA

SH_S

AR

1~6

<3:0

>

(c)

Fig. 6. (a) Block diagram of 10-bit Time-Interleaved Flash SAR ADC, (b) block diagram of 6-bit SAR ADC, (c) block diagram of Output Merge Block.


IV. MEASUREMENT RESULTS

Fig. 8 shows the chip photograph pattern of the proposed 4-channel VCSEL driver. The die area is 4.2 mm2. The pad pitch of the input and output is 250 um to connect the external 4-channel VCSEL diode.

Fig. 9 shows the measurement environment. The high- speed oscilloscope (DSA71254C), arbitrary waveform generator (AWG7122B), power supply, and network analyzer are used for the measurement. The SPI is controlled by the PC and supply voltage is provided by the power supply.

Fig. 10 shows the measurement result of S22 at VCSEL driver output. The S22 is less than -10 dB from DC to 5 GHz. To maintain the minimum return loss, the output impedance of the driver is matched with that of the VCSEL diode.

Fig. 11 shows the measurement result of the small signal gain of the driver with respect to the data rate of the input signal.

The small input signal is applied to the input of the VCSEL driver and the driver output is measured using the AWG7122B. The small signal gain is about 10 dB with the 3 dB bandwidth of 11 Gbps. There is the

inductor peaking around the data rate of 12 Gbps. Fig. 12 shows the measured jitter of the proposed

VCSEL driver. Through the AMC/APC calibration, the peak-to-peak jitter is as small as 4.6214 ps, which is

Fig. 7. Timing diagram of the proposed 10-bit time-interleaved Flash SAR ADC.

10 bit ADC1

Digital Logic 1,2OSC 2.5VLDO

BIASGEN

SPI1.2VLDO P

re &

Mai

n D

rive

r 1

CD&PD1

10 bit ADC2

Data In/Inb

VCSEL DriverOut

CD&PD2 CD&PD3 CD&PD4

Pre

& M

ain D

rive

r 2

Pre

& M

ain D

rive

r 3

Pre

& M

ain D

rive

r 4

Fig. 8. The chip photograph.

Arbitrary Waveform Generator

Test Board

High Speed Oscilloscope

Supply SPI PC

Input Output

Fig. 9. The measurement environment.


about 23% of the required spec., 20 ps, in Table 1 at 10 Gbps.

Fig. 13(a)-(c) show the measured waveforms of the APC/AMC digital tuning controller, measured output voltage waveforms before and after the APC/AMC calibration, and measured output voltage waveforms with respect to the APC/AMC reference bits, respectively.

Fig. 13(a) shows the measured waveforms of the

APC/AMC digital tuning controller. It shows that the number of ADC_EOC pulses is 11 since the first ADC_EOC signal is neglected in the digital tuning controller considering the initial settling times of PD and CD. After the APC/AMC is completed, the APC/AMC lock signal goes to high and APC/AMC <9:0> is maintained.

Fig. 13(b) shows measured output voltage waveforms before and after the APC/AMC calibration. Initially, before the APC/AMC calibration, the output swing is 82 mVpk-pk, whereas it is increased to 355.2 mVpk-pk after the APC/AMC calibration. The required value can be determined by APC/AMC reference bit, which is “0010000000” in Fig. 13(b).

Fig. 13(c) shows the measured output voltage waveforms of APC and AMC when the APC/AMC reference bits are changed. When the APC/AMC <9:0>

Fig. 10. The measurement result of S22 at VCSEL driver output.

0

2

4

6

8

10

12

Data rate ( Gbps )

Inductor Peaking

7 8 9 10 11 12

Fig. 11. The measurement result of VCSEL driver small signal gain.

4.6214ps

Jitter Histogram

MIN:-2.1358ps

MAX:2.4856ps

( Time )

Fig. 12. Measured jitter of the proposed VCSEL driver.

ADC_EOC

APC/AMC Lock

(a)

< Before APC/AMC Calibration >

82mVpk-pk

< After APC/AMC Calibration >APC/AMC <9:0> Ref = 0010000000

355.2mVpk-pk

(b)

< APC/AMC <9:0> Ref = 1111111111>

439.2mVpk-pk

< APC/AMC <9:0> Ref = 0000000001>

49.2mVpk-pk

(c)

Fig. 13. (a) Measured waveforms of the APC/AMC digital tuning controller, (b) Measured output voltage waveforms before and after APC/AMC calibration, (c) Measured output voltage waveforms with respect to the APC/AMC reference bits.


reference is “1111111111”, the maximum output voltage swing is 439.2 mVpk-pk. On the other hand, the minimum output voltage swing is 49.2 mVpk-pk, when the APC/AMC reference is changed to “0000000001”. Since the peak detector in the APC/AMC loop detects the bottom voltage of the output, the output voltage swing increases as the APC/AMC reference code is decreased.

Fig. 14(a) and (b) show the measurement results for the differential nonlinearity (DNL) and integral nonlinearity (INL). The peak DNL and INL are -0.706 / 0.899 LSB and -1.004 / 1.063 LSB, respectively. Also,

Fig. 14(c) shows the FFT spectrum with a sampling rate of 10-MS/s. The measured SNDR and ENOB are 57.857 dB and 9.318 bits, respectively.

Fig. 15(a) and (b) show the measured output current range and resolution of the VCSEL driver with respect to the DIG_APC<9:0> and DIG_AMC<9:0>, respectively.

Fig. 15(a) presents the measured modulation current range of the AMC is 5 ~ 20 mA and the current resolution is 0.0146 mA. The resolution can be calculated using Eq. (3). Fig. 15(b) shows the CM voltage according to the APC<9:0> control.

10

20 - 5 (mA) 0.0146 mA2 1

=-

(3)

Since the output current and common voltage ranges

of the driver are wide, it is applicable to a variety of VCSEL diode type.

Fig. 16 shows the measured output current and voltage swing of the pre driver with respect to the data rate when DIG_APC/AMC <9:0> is “1000000000”.

As the data rate decreases, the output current of the pre

(a)

(b)

0

-20

-40

-60

-80

-100

-120

fs = 10 MS/sfin = 4.8 MHz

SNDR = 57.857 dBENOB = 9.318 bits

fin

Frequency (MHz)0 1 2 3 4 5

(c)

Fig. 14. Measured (a) INL, (b) DNL of flash-SAR ADC, (c) SNDR and ENOB.

(a)

(b)

Fig. 15. Measured output current range and resolution of the VCSEL driver with respect to the (a) AMC<9:0>, (b) APC<9:0>.


driver can be reduced, maintaining the output voltage swing. The proposed driver can support the multi-rate with the optimum current consumption. If the user wants to transfer data at the data rate of 2.5 Gbps, the current consumption can be minimized to about 15 mA compared to that at the data rate of 10 Gbps. The output voltage swing is almost constant as 360 mVpk-pk at the data rate of 2.5~10 Gbps. Therefore, it can be applied to various optical applications.

Table 2 summarizes the measured performance of the VCSEL driver

The power consumption of this work is lowest compared with references [13-16] thanks to the proposed digital power calibration technique.

V. CONCLUSIONS

This paper presents a 4-channel multi-rate vertical-

cavity surface-emitting laser (VCSEL) driver for PtP WDM and TWDM-PON systems. In order to keep the output power constant with respect to variations in the PVT, automatic power and magnitude are proposed.

For the fast turn-on time, the high-speed 10-bit time-interleaved flash-SAR ADC is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption.

This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm2. The power consumption is 370 mW for 4-channel from a 3.3 V supply voltage. The measured current range and resolution of bias/modulation current for APC/AMC are 5~20 mA and 0.015 mA, respectively.

ACKNOWLEDGMENTS

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (2014R1A5A1011478). This research was supported by Global PH.D Fellowship Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education. (2013H1A2A1034225)

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Table 2. Performance comparison of VCSEL driver with prior works

Parameters [13] [14] [15] [16] This work

Data Rate 11.3 Gb/s 0 ~ 10.7Gb/s 10-Gb/s 11.3 Gb/s 10-Gb/s Number of Channel Single 4 Channels 4 Channels Single 4 Channels

Power Consumption N.A. 140 mW / Channel 211.2 mW / Channel 214 mW 117.84 mW/Channel

(Max Current Setting) Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

Area (Package or Die)

4 mm×4 mm (QFN) N.A. 2.05 mm×1.67 mm

(Bare Die) 3 mm×3 mm

(LFCSP) 4.2 mm2

Automatic Power Control (APC) O X X X ○

(Digital feedback loop) Modulation Current

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Bias Current (IBIAS) 20 mA (max.) N.A. 10 mA (max.) 2 ~ 25 mA

2.65 ~ 11.16 mA (Diff. 5.3 ~ 22.3 mA)

Fig. 16. Measured output current and voltage swing of the Pre Driver with respect to the data rate.


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[12] Ohhata, K., Imamura, H., Takeshita, Y., Yamashita, K., Kanai, H., Chujo, N., “Design of a 4 × 10-Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Inter- connection,” IEEE Transactions on Microwave Theory and Techniques, Vol.58, NO.5, pp.1107-1115, May, 2010.

[13] Company: TEXAS INSTRUMENTS, Model: ONET1191V.

[14] Company: ZARLINK SEMICONDUCTOR, Model: PX6514.

[15] Company: GIGOPTIX, Model: HXT5004A. [16] Company: ANALOG DEVICES, Model: ADN2530.

Sunghun Cho received his B.S. degree from the Department of Electronic Engineering at Hongik University, Seoul, Korea, in 2013, and his M.S. degree in the electronic engineering at Sungkyunkwan Uni- versity, Suwon, Korea, in 2015. He is

currently working toward a Ph.D. degree at the School of Information and Communication Engineering, Sungkyun- kwan University, Suwon, Korea. His research interests include CMOS RF transceiver and Automotive IC design.

DongSoo Lee received his B.S., and M.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2012, and the electronic engineering at Sungkyunkwan University, Suwon, Korea, in 2014, respectively. He is

currently working toward a Ph.D. degree in electronic engineering at Sungkyunkwan University. His research interests are focused on CMOS RF IC and Phase Locked Loop, Silicon Oscillator, Sensor Interfaces design.

Juri Lee received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013, where she is currently working toward the combined Ph.D. & M.S degree in School of Information and Commu-

nication Engineering, Sungkyunkwan University. Her research interests include CMOS RF transceiver.


Hyung-Gu Park received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2010, where he is currently working toward the Ph.D. degree in College of Information and Communication

Engineering, Sungkyunkwan University. His research interests include high-speed interface IC and CMOS RF transceiver.

YoungGun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively. His research interest is focused on CMOS fully integrated frequency

synthesizers and oscillators and on transceivers for low-power mobile communication.

Sang-Sun Yoo received his B.S. degree from Dong-guk University, Seoul, Korea, in 2004, and his M.S/Ph.D. degree received from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2012. He worked for System LSI

division in Samsung Electronics from 2012 to 2015 where he focused on ADPLL for 3/4G SAW-less mobile applications as a senior design engineer in RFIC development. Since 2015, he has been a Research Assistant Professor in KAIST. His research interests include RF systems for mobile communications, reconfigurable RFICs, ADPLL, RFID, and sensor communications. He is listed in Marquis’s Who’s Who in the World. He received the best paper award for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS (TIE) in 2011.

Keum Cheol Hwang received his B.S. degree in electronics engineering from Pusan National University, Busan, South Korea in 2001 and M.S. and Ph.D. degrees in electrical and electronic engineering from Korea Advanced Institute of Science and

Technology (KAIST), Daejeon, South Korea in 2003 and 2006, respectively. From 2006 to 2008, he was a Senior Research Engineer at the Samsung Thales, Yongin, South Korea, where he was involved with the development of various antennas including multiband fractal antennas for communication systems and Cassegrain reflector antenna and slotted waveguide arrays for tracking radars. He was an Associate Professor in the Division of Electronics and Electrical Engineering, Dongguk University, Seoul, South Korea from 2008 to 2014. In 2015, he joined the Department of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon, South Korea, where he is now an Associate Professor. His research interests include advanced electromagnetic scattering and radiation theory and applications, design of multi-band/broadband antennas and radar antennas, and optimization algorithms for electromagnetic applications. Prof. Hwang is a life-member of KIEES, a senior member of IEEE and a member of IEICE.

Youngoo Yang (S'99-M'02) was born in Hanyang, Korea, in 1969. He received the Ph.D. degree in electrical and electronic engineering from the Pohang University of Science and Technology(Postech), Pohang, Korea, in 2002. From 2002

to 2005, he was with Skyworks Solutions Inc., Newbury Park, CA, where he designed power amplifiers for various cellular handsets. Since March 2005, he has been with the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea, where he is currently an associate professor. His research interests include power amplifier design, RF transmitters, RFIC design, integrated circuit design for RFID/USN systems, and modeling of high power amplifiers or devices.


Cheon-Seok Park was born in Seoul, Korea in 1960. He received the B.S. degree in electrical engineering from the Seoul National University, Seoul, Korea, in 1988, and M.S. and Ph.D. degrees in electrical & electronic engineering from the Korea Advan-

ced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1990 and 1995, respectively. He is currently a Professor in the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea. His research interests include design of RF power amplifiers, linearization techniques, and efficiency enhancement techniques.

Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semicon-

ductor Inc., San Jose, CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of Information and Communication Engineering, Sungkyunkwan University, where he is currently an Associate Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed.

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