a 40 mv /4 uw cmos colpitts oscillator with additional positive feedback at 2.12 ghz
DESCRIPTION
A 40 mV /4 uW CMOS Colpitts Oscillator with Additional Positive Feedback at 2.12 GHz. Rodrigo Eduardo Rottava Fernando Rangel de Sousa. Outline. Introduction Proposed Topology Analysis Design Post-layout Simulations Conclusions. Introduction. - PowerPoint PPT PresentationTRANSCRIPT
Brasília, September 1st 2012
[email protected]@ieee.org
LCI - UFSC
Integrated Circuits Laboratory – Tecnological CenterDepartment of Electrical EngineeringFederal University of Santa Catarina
A 40 mV/4 uW CMOS Colpitts Oscillator with Additional
Positive Feedback at 2.12 GHz
Rodrigo Eduardo RottavaFernando Rangel de Sousa
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected] 2
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected] 3
Introduction
The aim: new topology to reduce power consumption and supply voltage of radio-frequency oscillators.
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Introduction
The aim: new topology to reduce power consumption and supply voltage of radio-frequency oscillators.
How: to add a new positive feedback technique in a classical Colpitts oscillator.
3
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Introduction
The aim: new topology to reduce power consumption and supply voltage of radio-frequency oscillators.
How: to add a new positive feedback technique in a classical Colpitts oscillator.
Applications: WBAN’s (ultra-low power consumption).
3
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
4
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Colpitts Oscillator
5
High level representation
Oscillation Criteria:
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Colpitts Oscillator
5
High level representation
Oscillation Criteria:
Colpitts Oscillator
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Colpitts Oscillator
5
High level representation
Oscillation Criteria:
Colpitts Oscillator
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Adding Feedback
6
Source admittance Lg :
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Adding Feedback
6
Source admittance Lg :
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Adding Feedback
6
Source admittance Lg :
By using those two feedback sources it is possible to reduce the bias current.
Proposed topology.
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
7
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
Circuit Losses
Small-signal representation
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
Circuit Losses
Small-signal representation
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
Circuit Losses
Small-signal representation
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
Circuit Losses
Small-signal representation
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Small-Signal Representation
Proposed topology
8
Circuit Losses
Small-signal representation
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Required gms
Total source transconductance:
Total drain transconductance:
9
Circuit Losses
The required gms in order to start-up the oscillator:
1st oscillation criterion:
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Oscillation Frequency
10
The oscillation frequency is given by: where:
2nd oscillation criterion:
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
11
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
Two strategies to reduce the required gms were studied.
11
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
Two strategies to reduce the required gms were studied.
11
a) Optimum capacitor ratio:
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
12
b) Gate inductive degeneration:
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
12
b) Gate inductive degeneration:
For |α|, |β| < 0
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Reducing the required gms
Required gms:
12
b) Gate inductive degeneration:
For |α|, |β| < 0
Nevertheless, for
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Effect of Lg
Effect of Lg on the input conductance of theone-port network.
13
Parameters Value
gms 4.5 mS
gmd 1.5 mS
gmg 2.5 mS
Cgs 100 fF
Cgd 100 fF
C1 540 fF
C2 700 fF
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Effect of Lg
Effect of Lg on the input conductance of theone-port network.
13
Parameters Value
gms 4.5 mS
gmd 1.5 mS
gmg 2.5 mS
Cgs 100 fF
Cgd 100 fF
C1 540 fF
C2 700 fF
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
14
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
Gate Inductor
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
Gate InductorOptimum
Capacitive Ratio
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
Gate InductorOptimum
Capacitive Ratio
Minimum gms?
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
Gate InductorOptimum
Capacitive Ratio
Minimum gms?
Decrease VDD
No
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Design Flow
15
DC Characterization
Gate InductorOptimum
Capacitive Ratio
Minimum gms?
Gate InductorNo
Optimized Low-Voltage Oscillator
Yes
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Specifications
16
• Oscillator at 2.4 GHz in CMOS 130 nm using a zero VTH transistor.
• Buffer in order to adapte the oscillator with the spectrum analyzer.
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Specifications
16
• Oscillator at 2.4 GHz in CMOS 130 nm using a zero VTH transistor.
• Buffer in order to adapte the oscillator with the spectrum analyzer.
Oscillator Core
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Specifications
16
• Oscillator at 2.4 GHz in CMOS 130 nm using a zero VTH transistor.
• Buffer in order to adapte the oscillator with the spectrum analyzer.
Buffer
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Specifications
16
• Oscillator at 2.4 GHz in CMOS 130 nm using a zero VTH transistor.
• Buffer in order to adapte the oscillator with the spectrum analyzer.
Spectrum Analyzer
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Parameters
17
Transistor Parameter VDD = 40 mV
Value
gms 4.50 mS
gmd 1.52 mS
gmg 2.50 mS
Cgs 103 fF
Cgd 102 fF
Circuit Parameters Value
C1 541 fFC2 704 fFC3 10 pFC4 40 pFL1 9.18 nH
LRFC 10 nHLg 12 nH
M1 (zero VTH) 200u/400nM2 (nfet_rf) 50u/120n
R1 74 kΩIB 3 mA
VB 1.5 V
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Parameters
17
Transistor Parameter VDD = 40 mV
Value
gms 4.50 mS
gmd 1.52 mS
gmg 2.50 mS
Cgs 103 fF
Cgd 102 fF
Circuit Parameters Value
C1 541 fFC2 704 fFC3 10 pFC4 40 pFL1 9.18 nH
LRFC 10 nHLg 12 nH
M1 (zero VTH) 200u/400nM2 (nfet_rf) 50u/120n
R1 74 kΩIB 3 mA
VB 1.5 V
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Parameters
17
Transistor Parameter VDD = 40 mV
Value
gms 4.50 mS
gmd 1.52 mS
gmg 2.50 mS
Cgs 103 fF
Cgd 102 fF
Circuit Parameters Value
C1 541 fFC2 704 fFC3 10 pFC4 40 pFL1 9.18 nH
LRFC 10 nHLg 12 nH
M1 (zero VTH) 200u/400nM2 (nfet_rf) 50u/120n
R1 74 kΩIB 3 mA
VB 1.5 V
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Final Layout
Technology: IBM 130 nm.
M1 = Zero-VTH transistor
Area: 0.9 mm²
L1 LRFC
Lg
18
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Final Layout
Technology: IBM 130 nm.
M1 = Zero-VTH transistor
Area: 0.9 mm²
18
M1
M2
IB
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Final Layout
Technology: IBM 130 nm.
M1 = Zero-VTH transistor
Area: 0.9 mm²
VDD GND
RF OUTB1 B2
18
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
19
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Post-layout Simulation
Transient Simulation (loaded oscillator)Output voltage and drain current
20
Vout
ID
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Post-layout Simulation
Transient Simulation (loaded oscillator)Output voltage and drain current
20
Vout
ID
30 mV
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Post-layout Simulation
Transient Simulation (loaded oscillator)Output voltage and drain current
20
Vout
IDVDD ID = 4 µW
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Post-layout Simulation
Phase Noise Simulation21
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Comparative Table
[2] T. Brown, F. Farhabakhshian, A. Guha Roy, T. Fiez, and K. Mayaram.
[3] H.-H. Hsieh and L.-H. Lu.
[4] K. Kwok and H. Luong.
22
Parameters [2] [3]a [3]b [4] This Work
CMOS Technology (nm) 130 180 180 180 130
Supply Voltage (mV) 475 600 400 350 40
Frequency (GHz) 4.90 5.60 5.60 1.40 2.12
DC Power (mW) 2.70 3.00 1.10 1.46 0.004
Phase Noise (dBc/Hz) -136.2¹ -118.0² -114.0² -128.6² -91.5²
FoM (dBc/Hz) 196.3 189 189.0 189.8 182
¹ @ 3 MHz² @ 1 MHz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Comparative Table
[2] T. Brown, F. Farhabakhshian, A. Guha Roy, T. Fiez, and K. Mayaram.
[3] H.-H. Hsieh and L.-H. Lu.
[4] K. Kwok and H. Luong.
22
Parameters [2] [3]a [3]b [4] This Work
CMOS Technology (nm) 130 180 180 180 130
Supply Voltage (mV) 475 600 400 350 40
Frequency (GHz) 4.90 5.60 5.60 1.40 2.12
DC Power (mW) 2.70 3.00 1.10 1.46 0.004
Phase Noise (dBc/Hz) -136.2¹ -118.0² -114.0² -128.6² -91.5²
FoM (dBc/Hz) 196.3 189 189.0 189.8 182
¹ @ 3 MHz² @ 1 MHz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Comparative Table
[2] T. Brown, F. Farhabakhshian, A. Guha Roy, T. Fiez, and K. Mayaram.
[3] H.-H. Hsieh and L.-H. Lu.
[4] K. Kwok and H. Luong.
22
Parameters [2] [3]a [3]b [4] This Work
CMOS Technology (nm) 130 180 180 180 130
Supply Voltage (mV) 475 600 400 350 40
Frequency (GHz) 4.90 5.60 5.60 1.40 2.12
DC Power (mW) 2.70 3.00 1.10 1.46 0.004
Phase Noise (dBc/Hz) -136.2¹ -118.0² -114.0² -128.6² -91.5²
FoM (dBc/Hz) 196.3 189 189.0 189.8 182
¹ @ 3 MHz² @ 1 MHz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Comparative Table
[2] T. Brown, F. Farhabakhshian, A. Guha Roy, T. Fiez, and K. Mayaram.
[3] H.-H. Hsieh and L.-H. Lu.
[4] K. Kwok and H. Luong.
22
Parameters [2] [3]a [3]b [4] This Work
CMOS Technology (nm) 130 180 180 180 130
Supply Voltage (mV) 475 600 400 350 40
Frequency (GHz) 4.90 5.60 5.60 1.40 2.12
DC Power (mW) 2.70 3.00 1.10 1.46 0.004
Phase Noise (dBc/Hz) -136.2¹ -118.0² -114.0² -128.6² -91.5²
FoM (dBc/Hz) 196.3 189 189.0 189.8 182
¹ @ 3 MHz² @ 1 MHz
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Outline
• Introduction• Proposed Topology• Analysis• Design• Post-layout Simulations• Conclusions
23
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Conclusions
• Two positive feedback sources + optimization = decrease the power and supply voltage.
24
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Conclusions
• Two positive feedback sources + optimization = decrease the power and supply voltage.
• We have achieved an oscillator with 40 mV of supply voltage and 4 uW of power consumption.
24
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
Errata
25
+
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
A 40 mV/4 uW CMOS Colpitts Oscillatorwith Additional Positive Feedback at 2.12 GHz
Questions
Thank you!
26
A 4
0 m
V/4
uW
CM
OS C
olp
itts
Osc
illato
r w
ith A
ddit
ional
Posi
tive F
eedback
at
2.1
2 G
Hz
LCI - UFSC
Rodrigo E. Rottava and Fernando R. de Sousa – [email protected]
ISCAS 2012
27