a 512gb 3-bit/cell 7 -generation 3d nand flash memory with
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30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 1 of 12
A 512Gb 3-bit/Cell 7th-Generation 3D NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
Jiho Cho, D.Chris Kang, Jongyeol Park, Sang-Wan Nam, Jung-Ho Song, Bong-Kil Jung, Jaedoeg Lyu,Hogil Lee, Won-Tae Kim, HONGSOO Jeon, SUNGHOON Kim, In-Mo Kim, Jae-Ick Son,
KyoungTae Kang, Sang-Won Shim, JongChul Park, Eungsuk Lee, Kyung-Min Kang, Sang-Won Park,Jaeyun Lee, Seung hyun Moon, PANSUK Kwak, ByungHoon Jeong, Cheon An Lee, KISUNG Kim,
Junyoung Ko, Tae-Hong Kwon, Junha Lee, Yohan Lee, Chaehoon Kim, Myeong-Woo Lee, Jeong-yunYun,HoJun Lee, Yonghyuk Choi, Sanggi Hong, JongHoon Park, Yoonsung Shin, Hojoon Kim, Hansol Kim,
Chiweon Yoon, Dae Seok Byeon, Seungjae Lee, JIN-YUB LEE, Jaihyuk Song
Samsung Electronics, South Korea
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 2 of 12
Self Introduction
Education Background
Work Experience
• B.S degree in Computer Science Engineering from Pusan National University, Pusan, South Korea, in 1998
• Have been with Samsung Electronics since 1998• Designed Planar NOR/NAND Flash 1998-2012• Designed VNAND [2nd / 4th / 7th Gen.] since 2013 as Project Leader
Research Interest• Memory Architecture / Circuit Design Cell Characteristic / Fault Analysis• Business Strategy / Applications of Memory
*E-mail : [email protected] or [email protected]
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 3 of 12
Technologies for 7th Generation 3D-NAND
Performance
Power Consumption for COP Architecture
2.0Gbps IO Support
• Conventional BL Forcing• 2-step BL Forcing w/Dynamic latch• 2-step BL/WL Forcing
• MIM Cap for COP• Optimization of Pumping Capacitors
• Dual Interface of Termination type
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 4 of 12
Conventional BL Forcing
Channel
0V
SSL
Unsel.WL
Unsel.WL
Sel.WL
GSL
Channel
VpassBoosting
SSL
Unsel.WL
Unsel.WL
Sel.WL
GSL
Channel
ForcingLevel.
SSL
Unsel.WL
Unsel.WL
Sel.WL
GSL
PGM InhibitPGM with BLForcing
2nd
Sense (Target Vth)1st
Sense
P state upper
Slightly PGM
Fully PGM
VPGM-VforceVPGM
With BL forcing, the programming electric field between SEL WL and Channel is reduced.
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 5 of 12
AC
RST_1SET_1 SET_2 RST_2
B
DE
Normal Cell Region
VFY1 VFY3VFY2
2-step BL forcing w/Dynamic latch
Forcing Region2(Vforc2)
Forcing Region1(Vforc1)
Concept of *TBF
WL
PGM EXE w/ 2-STEP Forcing RCY
VBL(Force1)
Select WL
Unselect WL
VBL(Force2)
VBL(Normal)
Vforc1
VDD (Inhibit)
GND (PGM)
VPGM
VPASS
Timing Diagram of TBF
Dynamic Latch with TBF
TBFConv. BL Forcing
Internal Forcing
1step
2step
Vforc2
* GND < Vforce1 < Vforce2 < VDD
WLSETUP
Forcing Step1 & 2=> Upper Control
*Two-step BL Forcing
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 6 of 12
2-step BL/WL forcing
WL
WL SETUP PGM EXEw/ Forcing 1-Step RCY
VBL(Force)
Forcing 2-Step
VBL(Normal)
Select WL
Unselect WL
VPGM - Vforc + 0.5ISPP
Normal Cell Region
Forcing Region
VFY1 VFY2
Vforce
VDD (Inhibit)
GND (PGM)
VPGM
VPASS
Concept of *TBWF Timing Diagram of TBWF
External Forcing
2step1step
TBWFConv. BL Forcing
Forcing Step1 => Upper ControlForcing Step2 => Under Control
*Two-step BL/WL Forcing
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 7 of 12
Comparison of Pumping Cap. Structures
CSLWL
WL
WL
LM
N+ N+
G-Poly
LMLM
MMM
SUBWL
WL
WL
SUBN+ N+
G-Poly
MMMMMM
Conventional Architecture Cell Over Peri Architecture
Metal Contact
Comparison of pumping capacitors of 3D NAND
Pumping capacitors of metal contact is not available in Cell Over Peri Architecture. So, power and area efficiency of charge pumps is degraded
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 8 of 12
1st Stage LVN Cap. & MIM Cap for COP
Optimization of pumping capacitors by series stage
1st
stage
Thin Oxide. Thick Oxide.
2nd
stageN-1
stageN
stage
CLK nCLK CLK nCLK
MIM caps for COP
CSLWL
WL
WL
LM
N+ N+
G-Poly
LMLM
MMM
SUB
≈
≈
≈
A
B
LVN
B
A A
B
LVN
B
A
1st Stage LVN Cap. & MIM caps for COP achieve 24% power reduction and 27% area reduction of charge pumps
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 9 of 12
Toggle 4.0 Interface
CTT Interface Signaling
For high speed SI, using strong ODT is required. But it increases channel power consumption.
Driver ODT
Ron# Rtt#
Ron# Rtt#
Transmission Line
VOH = VccQ
VOL = VSS
w/o ODTVccQVOH
VOLVSS
w/ Rtt1
VccQVOH
VOLVSS
w/ Rtt2
Driver & ODT
VccQVOH
VOLVSS
w/ Rtt2
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 10 of 12
Dual Interface
Comparison of Interface type
Interface Type (A) CTT (B) LTT
(C) V-NAND 7th Gen(Dual interface)
= CTT @ CTT mode= LVSTL @ LTT mode
CTT mode LTT mode
PMOS NMOS PMOS NMOS
NMOS NMOS NMOS NMOS
Circuit
Signaling
Tr. type
Pull Up
Pull Down
Topology
Driver ODT
TransmissionLine
Driver ODT
VccQ
VSS
VOH
VOL
Vref Range Vref
Range
Driver ODT
Dual Interface : In heavy load systems, select CTT interface mode and in lighter-load systems select LTT interface mode.
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 11 of 12
Power comparison
Termination type Power comparisonAt 2Gbps I/O speed, 62% channel power reduction in LTT interface than in CTT interface.
100%105%
111%116%
122%
44% 47% 50% 54% 57%
%
20%
40%
60%
80%
100%
120%
140%
800 1,200 1,600 2,000 2,400
Com
paris
ion
(%)
Data Rate (Mbps)
Power Comparison(AC signal power + DC termination power)
CTT_50 LTT_50
30.3 : A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface© 2021 IEEE International Solid-State Circuits Conference 12 of 12
Conclusion - 7th Generation 512Gb 3D NAND
Die photograph Feature Summary
PAD/Peripheral CircuitsPAD
Plane-2Plane-1
Plane-4Plane-3
BLWL
ISSCC 2019[1] This Work
Bits per cell 3 3
Density 512Gb 512Gb
Page Size 16KB/Page 16KB/Page
Bit Density 5Gb/mm2 8.5Gb/mm2
I/O Bandwidth Max. 1.2Gb/s Max. 2.0Gb/s
tBERS 3.5ms (Typ.) 3.5ms (Typ.)
tR 45us 40us
ProgramThroughput 82MB/s 184MB/s
Vcc 2.35V to 3.6V 2.35V to 3.6V
Vccq 1.2V 1.2V