a 975 to 1960 mhz, fast-locking fractional-n synthesizer with...
TRANSCRIPT
A 975 to 1960 MHz, Fast-Locking Fractional-N Synthesizer with
Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners
Lei Lu1,2, Zhichao Gong1,2, Youchun Liao2, Hao Min1, Zhangwen Tang1
1 Fudan University, Shanghai, China2 Ratio Microelectronics, Shanghai, China
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 2
Outline• Motivation
• Synthesizer Architecture
• Proposed TechniquesAdaptive Bandwidth ControlDivision-Ratio-Based AFC Technique4/4.5 Prescaler
• Measurement Results
• Conclusions
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 3
Motivation
• Digital TV tuners need a wideband frequency synthesizer such as DVB-T
• Loop bandwidth changes greatly during a wide frequency range
• Wideband VCO needs AFC to select the sub-band automatically
• Low phase noise and low phase error are required in the receiver
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 4
Pros & Cons• Advantages
Loop bandwidth is adaptively controlledResidual fractional error is reduced and VCO clock is counted directlyLower phase noise due to the 4/4.5 prescalerMeasured low phase noise, low phase error and fast locking time
• DisadvantagesThe 4/4.5 prescaler leads to a little bit higher powerThe fractional spur is high when fractional modulus is close to 0 or 1
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 5
Synthesizer Block Diagram
LPF
Prescaler4/4.5
P/S Counter
Double-edge Retiming
PFD
3rd-order DSM
Dithering
AFC8
Vref
s1fref
25MHz
s1
R1
R1
C1/2
C2
C2 R3
R3
C3
C3
Vref
s1
s1
s2
s2
VCO
fout
0.975~1.96GHz
2323 3.F[22:0]
N[7:0]+.F[23]9
9
Differential CP
4 MSBs
8
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 6
Loop Bandwidth
• KVCO and fvco are two factors affecting loop bandwidth
• Maintain loop bandwidthOutput frequency fvco varies greatly across the wide range, but ICP also is tuned to compensate fvco
KVCO is maintainedThen the loop bandwidth is adaptively controlled across the whole frequency range
CP VCO ref 1 1
vco 1 2 3
Loop bandwidth2
= ⋅+ +
I K f RCπf C C C
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 7
Simplified LC-tank of Multiband VCO• Switched capacitors and
switched varactors are both adjusted simultaneously with different values of units to maintain both KVCO and band steps
• α1 ~ α255 and β1 ~ β255 are programmed coefficients
• See [Lu, et al., IEEE RFIC Symp., 2008]
f
1 f
ctrl
osc+ osc-
en1
255 f
f
1 f
255 fen255
v v
1 v 1 v
en1
255 v 255 v
en255
ctrlB
ctrlB
LC
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 8
Multiband VCO Calibration Using AFC• The purpose of AFC is to select the sub-band of
VCO whose center frequency is closest to the target frequency automatically
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 9
Conventional AFC• Frequency comparison by counter• Selected fvco is closest to N*fref, not (N+.F)*fref
Residual fractional error .F*fref is generated
ref
divref
vco
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 10
Division-Ratio-Based AFC
• Ndec is decoded from the division ratio N.Fdec, Residual fractional error is reduced to 2-4*fref
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 11
Direct Count of VCO Clock
• High-speed asynchronous divide-by-2 counters are used to count the VCO clock directly
Ncntr cntr dec
ref
AFC
cntr
cntr cntr
cntr cntr cntr
vco
vco
ref
Counter Ncntr
dec dec
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 12
Divider Chain• N=4, P=9~20, S=0~7, the overall division ratio
without DSM is N*P+0.5*S=36~83.5 (step=0.5)
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 13
Behavioral Simulations of Phase Noise• Comparison between step size of 1 and step size of 0.5• Similar phenomenon in [Yang, et. al., IEEE JSSC, Nov.
2006]step size of 1 step size of 0.5
102 103 104 105 106 107-150
-130
-110
-90
-70
Frequency Offset (Hz)
Pha
se N
oise
(dB
c/H
z)
total
VCO
CP
LPF
Ref.Div
DSM
102 103 104 105 106 107-150
-130
-110
-90
-70
Frequency Offset (Hz)
Pha
se N
oise
(dB
c/H
z)
total
VCO
CP
LPF
Ref.
DSM
Div
4.5dB reduction
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 14
Schematic of 4/4.5 Prescaler
• Works at both rising edge and falling edge• In divide-by-4.5 mode when mod is high
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 15
Timing Chart• Divide-by-4.5 mode• Q8 lags half a period behind Q5
vco
4.5
9
9
9
9
4.5 4.5
4.5 4.5 4.5
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 16
Double-Edge-Triggered Retiming Circuit• Comparison between single and double edge
single-edge-triggered retiming
double-edge-triggered retiming
div
vco
vco
div
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 17
Other Circuit Details
• VCOPower supply from LDOComplementary cross-coupled transistorsTwo tail inductors to lower the phase noise
• Charge PumpDifferentially configuredRail-to-rail CMFB
• Loop FilterOn-chip MIM capacitor and high-res poly resistor
• DSM & P/S CounterProgrammed using Verilog language
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 18
Die Micrograph
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 19
VCO Gains and Band Steps
0 50 100 150 200 2504
5
6
7
8
9
10
11
12
Sub-band (0~255)
KV
CO (M
Hz/
V)
0 50 100 150 200 2503
4
5
6
7
8
9
Ban
d S
tep
(MH
z)
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 20
Loop Bandwidth & Phase Error
1 1.2 1.4 1.6 1.8 20.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
Output Frequency (GHz)
Pha
se E
rror (
Deg
)
1 1.2 1.4 1.6 1.8 20
20
40
60
80
100
120
140
160
Loop
Ban
dwid
th (k
Hz)
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 21
Phase Noise• The division ratio is 53.56
Target
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 22
Locking Time
1.11.21.31.41.5
Freq
uenc
y (G
Hz)
0 10 20 30 40 501
1.11.21.31.4
Time (μs)
Freq
uenc
y (G
Hz)
5 15 25 351.21
1.2121.2141.216
start
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 23
Performance Summary
20 μs (6.4 μs for AFC)Locking Time< 1.5 HzFrequency
Resolution
0.6° to 1.05°Phase Error (rms)
83 to 102 kHz
Loop Bandwidth
-123@1 MHz14 mACurrent
-91@ 3kHzPhase Noise
(dBc/Hz)
1.8 VSupply Voltage
0.975 to 1.96 GHz (67.1%)
Output Frequency1.58 *1 mm2Die Area
25 MHzReference Frequency
0.18 μm CMOSTechnology
© 2009 IEEE International Solid-State Circuits Conference © 2009 IEEE 24
Conclusions
• Have demonstrated loop bandwidth is maintained in calibration-enable mode
• Have obtained 20 μs locking time and residual fractional error is reduced for AFC
• Have designed a 4/4.5 prescaler to obtain lower output phase noise contributed from DSM
• Have demonstrated low phase noise and low phase error performance across the whole wideband tuning range