A Continuous-Time Sigma-Delta ADC with Tunable Pass-Band for Multi-Standard Applications

Mahmood Barangi,t Ahmad Beirami,+ Hamid Nejati,t and Warsame H. Ali* tElectrical Engineering and Computer Science Department, University of Michigan, Ann Arbor, MI 48105. ({barangi, hnejati}@umich.edu)

"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332. (beirami@ece.gatech.edu) *Electrical and Computer Engineering Department, Prairie View A&M University, Prairie view, TX 77446. (whali@pvamu.edu)

Abstract-In this paper, we present a tunable continuous-time band-pass sigma-delta (��) analog-to-digital converter (ADC). Our design is suitable for multi-standard multi-user applications. Additionally , the tunability advantage enhances the obtainable resolution while reducing the power consumption by only operating in the desired bandwidth from the reserved bandwidth required for ADC's application. Our simulation results demonstrate that a relatively high SNR can be obtained using the designed �� ADC. We provide an implementation of the designed ADC using Gm-C circuits with O.18J-im mM CMOS technology. The circuit operates with 8MHz clock frequency and achieves 57.6dB Signal to Noise and Distortion Ratio (SNDR) with 20KHz bandwidth. At the mentioned clock frequency and 1.5V supply level, the circuit consumes less than ImW power. Our HSPICE simulation results are in very good agreement with our simulated model based on second order modified all-pass transfer functions. The effective number of bits obtained from our implemented ADC was observed to be ENOB=9.28 bits.

Index Terms-Analog-to-Digital Conversion; Sigma-Delta ADC; Gm-C Circuits; Continuous-Time Signal Processing.

I. INTRODUCTION

The stability, noise immunity, programmability, and high com­putational power of digital signal processing (DSP) as compared to the limited computational power, design complexity, and high power consumption of analog counterpart have motivated designers and engineers to push most of the signal processing to the digital domain. As the CMOS technologies continue to scale down, digital systems become more power and area efficient, while analog systems suffer from static power dissipation and large area of analog components. This does not allow analog de­signers to take enough advantage of newer technologies. There­fore, popularity of Analog-to-Digital Converters (ADC) have drastically increased in the recent decade since they provides the interface between analog and digital world. Fast growth of digital processing compared to its analog counterpart necessitates the use of ADC's closer to transceiver front end. This will reduce the analog processing and furthermore will save data from noise and distortion in the analog circuitry. However, for high speed appli­cations, the use of high speed ADC's will increase the system's power consumption dramatically. Down mixing is proposed as an approach to reduce the required speed for the ADC. Traditional approach is to convert the RF signal to a bandpass signal by either superheterodyne technique or direct conversion and then use low-speed ADCs to convert the signal into digital form. This approach has four main shortcomings. First, the flicker (l/f) noise of the analog circuitry can have significant effects on the signal in low frequencies. Second, the signal spectrum is very sensitive to DC offset. Third, there is a high sensitivity to UQ mismatch since direct conversion incorporates quadrature mixers. Fourth, direct conversion receivers are sensitive to even-order distortion in addition to odd-order distortion that is common to all RF receivers. Therefore, if possible, analog to digital conversion is preferred to be performed after the signal is demodulated into

low Intermediate Frequencies (low-IF). Consequently, band-pass ADCs are required.

Sigma-Delta (�,6.) modulation is popular in low speed high precision applications like audio and seismic systems. One sig­nificant advantage of �,6. ADCs is achieving high resolution by merely using a I-bit quantizer [1]. In a �,6. ADC, the input signal is oversampled at a much higher frequency than the Nyquist rate. This means that the effective bandwidth of the signal constitutes a negligible portion of the whole band. Noise shaping techniques are used to reduce the power spectrum of noise in the effective bandwidth of the signal. Note that in this case, the quantization error is also treated as noise. Several implementations of the discrete-time [2]-[5], continuous-time [6], [7] and a combination of both [8] have been presented in the literature. Due to the lack of power hungry input buffers and anti-aliasing filters in the continuous-time (CT) Delta-Sigma ADCs high bandwidth, power efficiency and dynamic range are achievable [6].

A lot of communication standards suffer from a poor band­width utilization due to the fact that the bandwidth assigned to each user is much less than the reserved bandwidth. This is aggravated in case of employing time multiplexing techniques. Therefore, a tunable ADC can significantly improve the perfor­mance. In Cognitive radio receivers, a high performance and easily reconfigurable ADC is highly on demand. Cognitive radio is a solution for increasing number of parallel communication standards as well as high traffic. In Cognitive radio, a set of parallel channels are active at the same time [2], [9]. Other applications of tunable ADC are in software defined radios [10] in third generation of cellular network and in switch-mode audio (class-D) power amplifiers, which are required in base-station transmitters [11]. Tunable ADC's are playing important roles in multi channel applications such as LTE-advanced [6] and WiMax [12].

In this paper, we present a tunable continuous-time (CT) band­pass (BP) �,6. ADC by directly designing the noise transfer function in the continuous-time signal domain. The operating frequency and bandwidth of the presented ADC can be tuned using circuit parameters. Therefore, our design is suitable for multi-standard multi-user communication systems.

II. DESIGN PRINCIPLES

Due to high simulation speed and ease of behavioral modeling, discrete time (DT) domain modeling and circuit implementation are preferred in �,6. ADCs. However, switched-C circuits, which are the most popular implementation technique for DT-�,6. ADCs, suffer from non-ideal switching problems, such as, charge injection, feed through, jitter effects, and settling time. On the other hand, continuous time (CT) domain modeling and circuit implementation, such as, Gm-C implementation can provide more robust designs with wider bandwidth. Therefore, in this paper we focus on the design of CT-�,6. ADCs.

978-1-4 799-0066-4/13/$3l.00 ©20 13 IEEE 633

Fig. I. Block diagram of a general single stage CT Ell. ADC.

Due to the major advances in the modeling and imple­mentation of DT-I:6 ADCs, in addition to the simplicity in simulations, one may plan to transform the discrete-time transfer function Hd(Z) of a DT-I:6 ADC to the continuous-time transfer function Hc (s) using the mapping Z = esT, [13] where Ts is the sampling period. However, it turns out that this transformation usually does not yield a realizable s-domain transfer functions. On the other hand, bilinear transformation can be used to well approximate a realizable CT filter transformed from the DT domains. However, bilinear transformation is only accurate in a specific range on the Z-circle, which would consequently increase our design constraints [14].

In order to achieve an accurate performance and a realizable tunable design, we implemented our tunable block (H(s)) di­rectly in the CT-domain (s-domain). Figure 1 shows the general block diagram for a single stage CT sigma-delta ADC. In this block diagram, E(s) represents the error due to the I-bit quantizer. It is important to note that Y (s) (the output of the ADC) is indeed a digital signal, which is obtained after sampling the output of the main block plus the quantization error. The sampling procedure does not impact the signal X (s) since the Nyquist condition is satisfied. On the other hand, the quantization error does have high frequency components which will be filtered out by the main block. Since these components are random in some sense, it is reasonable to assume that the quantization error to be a noise signal source uniformly distributed over [0, ws/2]' where Ws is the radial sampling frequency [1]. In Figure 1, it is straightforward to verify that the output signal is the input signal modulated by a signal transfer function (STF) Hx (s) given by Hx (s) = H(s), plus the noise that is modulated by a noise transfer function (NTF) He(s), which is given by He(s) = 1 - H(s). Hence, the s-domain relationship between the input and output will be

Y(s) = H(s)X(s) + (1- H(s))E(s). (1)

Our goal is to minimize the quantization noise around the center frequency of the signal. In addition, we want the signal to appear unaffected in the output. In other words, H x (s) should not affect the signal in the frequency band of interest, while He(s) must suppress the noise as much as possible. Hence, we choose Hx (s) to be an all-pass transfer function, i.e., IHx (jw)1 = 1. A similar approach by using first order all-pass transfer function has been investigated in Z-domain in [15], however, those results are not directly applicable to the continuous-time domain due to the aforementioned reasons. In order to achieve noise suppression at the operating frequency band, we chose H (s) such that 1 - H (jw) has a zero at w = wo, where Wo denotes the center frequency of the signal. We designed our all-pass transfer function H(s) = Hx (s) using the basic signal processing procedure [13] and it is given by

( ) ( ) s2-2Qwos+w� . Hx s = H s = - 2+2 + 2, where a and Wo are arbitrary s awos Wo constants and 0 < Wo < ws/2. Note that we will use a and Wo as design parameters in order to tune the bandwidth as well as

20

10 ,

-10 in os -20 '§' =., -30 �

-40

-50

-60

-70 0 0.1 0.2 0.3 0.4 0.5 w/WsamPling

Fig. 2. NTF for different values of'Y = wo /ws with ex = 1.

the center frequency of the ADC. Let 'Y = � denote the center frequency tuning parameter for the presented ADC. In this case, the NTF is expressed as

2(S2 + w6) He(s) = 1- H(s) = 2· s2 + 2awOS + Wo

(2)

It can be observed that He (jw) has two zeros that are located at w = ±wo. Figure 2 shows the behavior of our presented block I H (jw) I at four different values of the tuning parameter 'Y. Since the signal bandwidth is much smaller than the sampling frequency, the STF phase LH(jw) is approximately a linear function of w. Thus, the input signal appears in the output with only a slight delay that we will characterize in the sequel.

There are two main concerns about our design that need to be resolved. The first one is shown after calculating IHe(jw)l:

IHe(jw)1 = 21w2 - w61

Jlw2 - w612 + 12awwol2 (3)

This shows that the filtering property of H (s) will degrade if Wo « Ws since limwo-+o IHe(jw)1 = 2. In other words, the proposed transfer function will not have the desired noise suppression property for very low frequencies near DC. Conse­quently, we take our center frequency tuning parameter 'Y to be greater than 0.1 ('Y > 0.1). Since the bandwidth is much smaller than the sampling frequency, (3) can be further simplified to

IHe(jw)1 � 21w - wol . awo

(4)

The second concern is about the implementation of this transfer function. This transfer function has a non-zero DC value. In particular, we have lims-+(X) H (s) = -1. Thus, the inverted input will directly appear in the output at very low frequency near DC. If we use this transfer function in a feedback loop as shown in Fig. 1, an algebraic loop will be formed (a loop only containing gain elements). This will result in an unstable circuit. In order to solve this instability problem, we add a third pole that eliminates the DC. This third pole is placed at Wp, which is far from the operation frequency so that it does not impact the characteristics of H(jw) for 0 < w < ws/2. The new transfer function with the third pole added is given by

H( ) - wp(s2-2awos+w�) I h· k . I h s - - s3+wp(s2+2awos+w5). n t is wor , we Imp ement t e

main block defined by the dashed line in Fig. l. Let Hb denote the transfer function of the main block, which can be calculated to be

Hb(S) = H(s)

1 - H(s) Wp(S2 - 2awos + w6)

s 3 + 2wp (s2 + w6) , (5)

634

Fig. 3. The s-domain realization of the presented transfer function H(s).

where we choose W p » "!!'. This ensures that W p impacts the place of the rest of the poles negligibly.

Next, we present a block diagram in Fig. 3 for the realization of the transfer function using a Gm-C circuit. The transfer function of the proposed block diagram is given by

(6)

Thus, in order to realize Hb, we need the following equalities.

{ al = -wPw5, a2 = 2awpwo, a 3 = -Wp, bi = -2wpw5, b2 = 0, b 3 = -2wp.

We implemented our tunable block in Simulink and used it to simulate the behavior of the proposed CT-BP I:6 ADC by using only one stage of our tunable block. Figure 4 shows the simulation results for wo/ws = 0.2. The simulated signal is located at the center frequency fo = 1.6MHz with signal bandwidth BW = 20kHz and sampled with sampling frequency fs = SMHz. As can be seen a relatively high SNR and effective number of bits (ENOB) is obtained using the proposed converter. In particular, at 'Y = 0.2, the effective number of bits is ENOB=9.4S. Note that it is a common practice to cascade a few stages of a I:6 ADC in order to further improve the performance of the sigma-delta ADCs [1].

In order to have an estimation of the expected signal-to­noise ratio (SNR) value generated from our tunable I:6 ADC, we present a compact formula for SNR estimation. We present calculations of the output noise power ((l;y) for the general case, in which L stages of the presented ADC are cascaded. It is straightforward to calculate the noise transfer function for an L-stage modulator: He(s) = [He(s)]L = [1 - H(S)]L [1]. We have i·wa +w B Jwa +w B (l;y = Pey(w)dw = 11 - H(jw)12L Pe(w)dw,

WO-WB WO-WB (7)

where Pey is the noise power density measured in the out­put, 2w B is the signal bandwidth, and Pe (w) is the noise power density of the source, which is assumed to be constant (Pe(w) = (l;/ws where 0 < w < ws). Consequently, by substituting IHe(w)1 from (4), SNR can be calculated using

SNR(dB) = 10 log ( :·L) . It can be shown that increasing a will result in better SNR. On the other hand, this will degrade the linearity of the phase of STF [13]. Therefore, a can not be increased beyond a certain limit. Assuming a I-bit quantizer, we have (l; = V2/3 [1], where V is the amplitude of the quantized signal. For a sinusoidal input with amplitude V (full dynamic range), we have (l; = V2/2. According to the number of bits required, we can calculate the necessary SNR. This will determine the oversampling ratio (OSR = fs/4fB). Therefore, we find the required sampling frequency fs and then we can tune the system using Wo to work in the signal center frequency.

0.5 1.5 2 2.5 Frcquency[Ml-lzJ

3.5

Fig. 4. Power spectral density (PSD) for a single stage of our tunable transfer function with Q = 1 and 'Y = wo /ws = 0.2.

::-E:: itt XIs) +;==rF====M====il

VIs) +

(b) V3 V'3

Fig. 5. (a) Gm-C implementation for our presented tunable Ell. block, (b) the transconductor-adder block.

III. IMPLEMENTATION USING GM-C CIRCUITS

In order to implement our presented tunable I:6 ADC, we used Gm-C architecture, as shown in Fig. 5(a). In this implemen­tation we used a new transconductor block, as shown in Fig. 5(b), which is referred to as the transconductor/adder block. The function of this block is to add the input voltage signals together and convert the summation to output current. Figure 6 shows the transistor-level implementation for the transconductor/adder block, which has the advantage of area and power saving by combining the two functions in one circuit implementation.

In the transconductor/adder implementation, shown in Fig. 6, MI-M6 are biased in the triode region to generate a current that is linearly proportional to the input voltage according to the classical drain current model in the triode region given by . [ VES ] �D = K (Yin + VCM - VT)VDS - -2- , (8)

where Yin and Vc M are the AC and DC components in the input signal, respectively, and K = fJ,nCox �. We use auxiliary opamps to drive the gates of M7 and M8 to guarantee the negative feedback and make VDS = Vc = constant. Therefore, assuming the same transistor sizing and the same DC input voltage, the current flows in M7 and M8 are given by

iM7 K [ ( � v"/ + 3VCM - 3VT) Vc - 3�c2 ] , (9)

iM8 K [ ( � Yj-+ 3VCM - 3VT) Vc _ 3�c2 ] . Transisitors M9 and MlO and the common-feedback (CMFB) circuit are responsible to equate the DC current in the differential branches and generate an AC differential current that is linearly proportional to the input voltage, which is given by,

G _ iM7 - iM8 m - = 2KVc'

V1+V2+V3 (10)

We should note that because of the CMFB, the output will remain unchanged due to DC changes in the signal. Therefore

635

Fig. 6. Transistor-level implementation for the transconductor-adder block used in our implementation.

! 2

:� _ ____ , " _----=--.-- _ E �o \1 J -40 !

-60 oL- --0:"-.'---C0.-=-2 ----:0":-.3--.,..0.4,--- --=-'0.5

� -9:1�--------' . � f�::: �--- __ _ ........ _-----

_360L--�--�----:�-�---=-' o 0.1 0.2 0.3 0.4 0.5 woo,

Fig. 7. The magnitude and phase response of the NTF (He(s)) extracted from HSPICE (solid blue curve) against the ideal transfer function (red dashed curve).

the transfer function will have a zero at DC which will degrade the behavior of the all-pass system in low frequencies. However, as mentioned before, we are not interested in using this config­uration for low-pass signals since we chose "( = wo/ws > O.l.

Consequently, the produced transfer function from our Gm-C implementation is given by

Y(s) X(s)

_ Grn3 82 + Gm2Grn3 S _ Grnl Gm2Gm3 G3 G2G3 G,G2G3

S3 + k �S2 + k �S + k GmlGm2Gm3' 3 G3 2 G2G3 1 G, G2G3 (11)

where we set the design parameters using Gm3/C3 = Wp, Gm2/C2 = 2o:"(ws, and Gml/C1 = ,,(ws/2o: in order to achieve the desired tunable transfer function. The radial operating fre-

quency of the signal is found to be Wo = "(Ws = J GC:g:;2. We

also set wp to be Wp = 50ws' In order to implement the main block in Fig. 1 according to (5) we have k3 = -2, k2 = 0, and kl = -2. According to (10), we see that Gm is a linear function of Vc. Therefore, the tuning is done with the aid of Vc in the second and the third transconductor-adder blocks.

The HSPICE simulation results for the NTF (He(s)) are shown in Fig. 7. Here, the simulated signal is located at the center frequency fo = 1.6MHz (wo = 5.02Mrad/s) with signal bandwidth BW = 20kHz and sampled with sampling frequency fs = 8MHz (ws = 25.13Mrad/s). Hence, we have "( = wo/ws = 0.2. We further calculated the signal delay in the output to be D = nOns using the phase of the STF (i.e., Hx (s)) from the implemented circuit. We previously demonstrated in Fig. 4 that the effective number of bits (ENOB) using the ideal continuous-time ADC at "( = 0.2 is expected to be ENOB=9.48 bits. However, when the HSPICE implementation is used for analog to digital conversion, the ENOB is slightly degraded to ENOB=9.28 bits, as shown in Fig. 8.

636

Fig. 8. Power spectral density (PSD) for a single stage of the HSPICE imple­mentation of the tunable transfer function with Q = 1 and 'Y = wo /ws = 0.2.

IV. CONCLUSION

We presented the design and implementation for a tunable continuous-time band-pass sigma-delta (�b.) ADC. Our design has the advantage of performance accuracy as it is designed directly in S-domain. Simulation results verified the tuning advantage of our design. Finally, we implemented the design using Gm-C architecture with 0. 18/Lm CMOS technology. Our simulation results demonstrated that the effective number of bits obtained from our implemented ADC is ENOB=9.28 bits using a single block of the presented �b. ADC.

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