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Integrated Ferroelectrics: AnInternational JournalPublication details, including instructions forauthors and subscription information:http://www.tandfonline.com/loi/ginf20

A DUAL-GATE CELL (DGC)FeRAM WITH NDRO ANDRANDOM ACCESS SCHEME FORNANOSCALE AND TERABIT NON-VOLATILE MEMORYHEE-BOK KANG a b , JAE-JIN LEE a , SUK-KYOUNGHONG a , JIN-HONG AHN a , JOONG-SIK KIH a , MANYOUNG SUNG b & YOUNG-KWON SUNG ba R&D Division, Hynix Semiconductor , Ichon,467-701, Koreab Department of Electrical Engineering , KoreaUniversity , Seoul, 136-701, KoreaPublished online: 17 Aug 2006.

To cite this article: HEE-BOK KANG , JAE-JIN LEE , SUK-KYOUNG HONG , JIN-HONGAHN , JOONG-SIK KIH , MAN YOUNG SUNG & YOUNG-KWON SUNG (2006) A DUAL-GATECELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE ANDTERABIT NON-VOLATILE MEMORY, Integrated Ferroelectrics: An International Journal,81:1, 141-148, DOI: 10.1080/10584580600660249

To link to this article: http://dx.doi.org/10.1080/10584580600660249

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Integrated Ferroelectrics, 81: 141–148, 2006

Copyright © Taylor & Francis Group, LLC

ISSN 1058-4587 print / 1607-8489 online

DOI: 10.1080/10584580600660249

A Dual-Gate Cell (DGC) FeRAM with NDRO andRandom Access Scheme for Nanoscale and Terabit

Non-Volatile Memory

Hee-Bok Kang,1,2,∗ Jae-Jin Lee,1 Suk-Kyoung Hong,1 Jin-Hong Ahn,1

Joong-Sik Kih,1 Man Young Sung,2 and Young-Kwon Sung2

1R&D Division, Hynix Semiconductor, Ichon, 467-701, Korea2Department of Electrical Engineering, Korea University, Seoul 136-701, Korea

ABSTRACT

This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composedwith MFSFET and MOSFET faced in parallel with common drain, source and floatchannel. The gates of the dual-gate cell are controlled by wordline and bottom wordline,respectively. A multitude of the dual-gate cells are arrayed in serial connection for unitarray scheme. The WL 1 to WL m of MFSFET are not biased for sensing operation inread mode, thus there are no degradation and disturbance to the cell retention data inread access. The write cycle composed with two sub-write cycles of data ‘1’ preserve ordata ‘0’ write cycle after the first sub-write cycle of data ‘1’ write to all active cells. Thedata ‘1’ is preserved by the same voltage polarity between WL 1 and channel voltageof the MFSFET. The random access operation is possible in both read and write modewith non-destructive read out (NDRO).

Keywords: MFSFET; dual-gate cell (DGC) FeRAM; enhancement DGC; depletionDGC; non-destructive read out (NDRO)

I. INTRODUCTION

Consumers and enterprises seem to have an insatiable demand for data storagein their mobile devices and computers. DRAM has long been a commodity busi-ness. Flash is now starting to experience the same price decrease and commoditycharacteristics of DRAM. Keys to the memory market remain high density andlow cost-per-bit. Cost makes process technology a key determinant of market

Received April 17, 2005; in final form January 23, 2006.∗Corresponding author. E-mail: kanghb@hynix.com

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success. With high growth prospects continuing to attract new players to thenonvolatile memory market, ferroelectric random access memory (FeRAM)may start to experience the same low price and commodity characteristics ofDRAM and Flash in near future. FeRAM is a non-volatile memory combiningboth ROM and RAM advantages in addition to non-volatility features and wellfit to the embedded process of single or multiple metal processes in system ona chip (SOC) with RF, analog, digital, nonvolatile memory and etc. Its higherspeed due to fast electric polarization switch of less than 1 ns in the ferroelec-tric film, its low power consumption without charge pump, as well as its highendurance with no limit for writing due to the absence of degrading gate oxidefilm that is implemented in the other non-volatile memory devices, make itsuperior to any other memory type. Standard 1T1C/2T2C FeRAMs have highperformance like DRAM and SRAM, but relatively large memory cell sizes,leading to high manufacturing costs [1]. The key elements for relatively largememory cell sizes are due to the process immature and large cell distributionproperties from weak cells. Today, FeRAM has a real differentiating advan-tage over EEPROM in portable applications, where non-volatility, low powerconsumption and high access time are all required. FeRAM for contact-less ICcard of bank cards, credit cards, prepayment cards, telephone cards, e-purseand passenger tickets, subscription cards, tags for identification, access controland etc., are today in common use all over the world. The application exampleof FeRAM for contact-less IC card is low density FeRAM applications suchas smart ID, memory cards and contactless RFID tag from few bytes up to16 Kbytes requiring high endurance and fast transaction. FeRAM densities ofgames applications are from 4 Kbytes up to 256 Kbytes and more. FeRAMdensities of high end smartcards, multi-application SIM cards and networkingcards are from 32 Kbytes up to 4 Mbytes. FeRAM densities of cellular phoneare from 1 Mbyte up to 16 Mbytes, and audio, video, image, fax printing andstorage with up 64 Mbytes.

The Flash type memory cell structure of metal ferroelectric semiconductor(MFS) field effect transistor (FET) is realized by replacing the silicon oxide filmwith ferroelectric film for gates with scaling shrink range up to unit polarizationlattice structure as shown in Fig. 1 [2, 3]. The FET-type FeRAM don’t havetunnel oxide for data retention so that the sensing current of the FET on-state islarge enough for fast operation and large scale cell size shrink. Reducing costsis largely a matter of squeezing more transistors onto each silicon wafer man-ufactured. The NAND Flash cell size is very small so that the cell size is costeffective. Today it is Flash memory, but after upcoming nanoscale technology,Flash will face some technical difficulties in scaling further. FeRAM will haveto come down in price and bet out other budding alternatives to EEPROM orFlash. The conventional NAND Flash cell array structure is composed of cellsof a string. The unit string is composed with serially connected cells, two stringselect transistors of select gate1 and select gate2. The string on-current in highdensity NAND Flash is so small that the sensing speed is in the range of 5 µs

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Figure 1. FET-type FeRAM advantage over EEPROM and flash.

and 10 µs, normally. Flash is seen by many as only a bridge for mobile systemapplications to a new type of memory, such as FeRAM with some momentumbehind it. The MFSFET is well in accordance with the scaling rules. 1-tarnsistor(1T) type memory cell reduces the area requirements considerably renderingFeRAMs cost competitive. 1T cell technology enables low voltage operationbut has a challenge achieving adequate data retention, which is negatively im-pacted by the depolarization field. The read voltage of VREAD like the NANDflash is too high for MFSFET FeRAM for data retention in ferroelectric layerwith low coercive voltage. Applying a certain gate voltage makes it possible thatcell data is given in the on and off form of drain current levels, so that MFSFETdesign technologies are very similar to EEPROM or Flash memory design tech-nologies. The non-destructive read out (NDRO) FeRAM will enable a limitlessnumber of read-out cycles. The MFSFET is difficult because of crystal incon-sistencies on the interface between the silicon substrate and ferroelectric film.However, nonvolatile single molecular scale MFSFET with carbon nano-tubeand ferroelectric polymer is very promising and under construction.

II. A DUAL-GATE CELL (DGC) FeRAM WITHNON-DESTRUCTIVE READ OUT (NDRO) AND RANDOM

ACCESS SCHEME

The cell structure of single FET with common substrate has some operating is-sues in circuit level. The conventional MFSFET cell can’t operate with randomaccess operation and can’t have long data retention time by read and write dis-turbance operation with the bias voltage at gate. To overcome the conventional

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Figure 2. The two types of enhancement and depletion dual gate cell (DGC).

MFSFET cell issues, we propose the two types of the enhancement type anddepletion type of dual-gate cell as shown in Fig. 2. The MFSFET and metaloxide semiconductor (MOS) FET are faced in parallel with common drain,source and float channel. The gates of MFSFET and MOSFET are controlledby wordline (WL) and bottom wordline (BWL), respectively. The data ‘1’ writeand read method of enhancement type is shown in Fig. 3.

For the write of data ‘1’ of (a), the WL and BWL are biased to negativevoltage 〈−V〉 and positive voltage 〈+V〉, respectively and drain and sourcenodes are biased to ground voltage 〈GND〉. For the read of (b), the WL andBWL are biased to ground voltage 〈GND〉 and drain and source nodes are

Figure 3. The data ‘1’ write and read method of enhancement type.

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A Dual-Gate Cell FeRAM [2285]/145

Figure 4. The data ‘0’ write and read method of enhancement type.

biased to sensing voltage for checking current flow. In this case, the channel ofMFSFET is off state by hole inducing polarization. The data ‘0’ write and readmethod of enhancement type is shown in Fig. 4.

For the write of data ‘0’ of (a), the WL and BWL are biased to positivevoltage 〈+V〉 and drain and source nodes are biased to ground voltage 〈GND〉.For the read of (b), the WL and BWL are biased to ground voltage 〈GND〉 and

Figure 5. Block diagram of core circuits.

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Figure 6. The timing waveform details of read cycle.

drain and source nodes are biased to sensing voltage for checking current flow. Inthis case, the channel of MFSFET is on state by electron inducing polarization.The block cell array scheme of the proposed dual-gate cell is shown in Fig. 5.A multitude of the dual-gate cells are arrayed to each other in serial connection.One edge node of the cell array is connected to source node of the switch deviceQ0 controlled by SEL 1 signal. The drain node of Q0 is connected to the bitlineof BL 1. The other edge node of the cell array is connected to drain node of theswitch device Q m+1 controlled by SEL 2 signal. The source node of Q m+1is connected to the sense line of SL 1. The timing waveforms of read cycle areshown in Fig. 6. The SEL 1 and SEL 2 are on state during t1 to t5. The WL 1to WL m are off state of ground voltage VSS, thus there are no degradation anddisturbance to the cell data retention in read mode.

Figure 7. Write and write-back method of write cycle.

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A Dual-Gate Cell FeRAM [2287]/147

Figure 8. The timing waveform details of write cycle.

The BWL 2 to BWL m are on state during t2 to t4, while BWL 1 isoff state, thus the other cells except the active cell are electrically shorted byBWL 2 to BWL m. During t3, the sense amplifier (SA) connected to BL 1forces to sensing voltage to BL 1, detects the cell current and amplifies the cellcurrent. The new data write and write-back method of write cycle is shownin Fig. 7. The timing waveforms of write cycle are shown in Fig. 8. Thewrite cycle composed with two sub-write cycles of data ‘1’ write to all ac-tive cells and data ‘1’ preserve or data ‘0’ write. For the first sub-write cycle,the SEL 1 and SEL 2 are on state during t1 to t6. The WL 2 to WL m areoff state, while WL 1 is negative voltage state of VNEG during t3 to t4. TheBWL 2 to BWL m are on state during t2 to t5, while BWL 1 is positive voltagestate during t4. For the second sub-write cycle, the SEL 1 is on state duringt1 to t6, while SEL 2 is off state for conducting BL 1 signals to cell array.The WL 2 to WL m are off state, while WL 1 is positive voltage state duringt4.

The BWL 1 to BWL m are on state during t2 to t5. The BL 1 signal ispositive voltage for preserve of the previously written data ‘1’ during the firstsub-write cycle and the BL 1 signal is ground voltage for data ‘0’ write. Thedata ‘1’ is preserved by the same voltage polarity between WL 1 and channelvoltage of the MFSFET. By this way random access operation is possible withNDRO.

III. CONCLUSIONS

The DGC string is more shrinkable than the NAND Flash string by the largecell sensing current and high punch-through voltage. The DGC structure is

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applicable in both enhancement and depletion FET-types. The DGC overcomesthe conventional single MFSFET cell issues related to the circuit limitationsand has no degradation and disturbance to the cell data retention integrity inread access. The random access operation is possible in both read and writemode with NDRO.

REFERENCES

1. Hee-Bok Kang, et al., “A Current-Gain Scheme for High Density and LowVoltage FeRAM”, Integrated Ferroelectrics 56, 1033–1043 (Feb. 2003).

2. Y. Tarui, IEDM 7–16 (Dec. 1994).3. S. Y. Wu, IEEE Trans. Electron Devices ED-21(8),499–504 (Aug. 1974).

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