a general space vector pwm algorithm for multilevel inverters including operation in over modulation...

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007 517

A General Space Vector PWM Algorithm forMultilevel Inverters, Including Operation

in Overmodulation RangeAmit Kumar Gupta, Student Member, IEEE, and Ashwin M. Khambadkone, Senior Member, IEEE

Abstract—This paper proposes a simple space vector pulsewidthmodulation algorithm for a multilevel inverter for operation in theovermodulation range. The proposed scheme easily determines thelocation of the reference vector and calculates on-times. It uses asimple mapping to generate gating signals for the inverter. A five-level cascaded inverter is used to explain the scheme. The schemecan be easily extended to a -level inverter. It is applicable to neu-tral point clamped topology as well. Experimental results are pro-vided for five-level and seven-level cascaded inverters.

Index Terms—Cascaded H-bridge inverter, modulation index,multilevel inverter, overmodulation, space vector pulsewidth mod-ulation (SVPWM).

I. INTRODUCTION

MULTILEVEL inverters [1], [2] include an array of powersemiconductors and capacitor voltage sources, which

generate output voltages with stepped waveforms. It leadsto waveforms of superior quality at relatively low switchingfrequencies as compared to two-level inverters. Multilevelinverters are very useful for medium voltage high power indus-trial drive applications [3].

Pulse width modulation (PWM) is widely used for voltagesource inverters, since it can produce output power with vari-able voltage and variable frequency. In the linear range of mod-ulation, the maximum obtainable voltage is 90.7% of the six-step value. This voltage can be increased further by properlyutilizing the dc link capacity through overmodulation. Spacevector PWM (SVPWM) is widely used for two-level inverterespecially for the operation in overmodulation [4]–[6] region.

SVPWM is also an attractive candidate for a multilevel in-verter as: i) it directly uses the control variable given by thecontrol system, and identifies each switching vector as a pointin complex space [7]; ii) it is useful in improving dc linkvoltage utilization, reducing commutation losses and THD [7];and iii) it is suitable for digital signal processing (DSP) imple-mentation and optimization of switching patterns as well [8].

The implementation of SVPWM for a multilevel inverters isconsidered complex [9]. This complexity is expected to increasefurther in the overmodulation region due to the nonlinearity ofthis region. In [10], we proposed a scheme to deal with the com-plexities of SVPWM in the linear range of modulation. In this

Manuscript received June 24, 2005; revised January 25, 2006. Recommendedby Associate Editor J. Rodriguez.

The authors are with the Department of Electrical and Computer Engineering,National University of Singapore, Singapore 117570.

Digital Object Identifier 10.1109/TPEL.2006.889937

paper, we propose a scheme for a multilevel inverter to operateit in overmodulation and right into six-step. Let us first brieflyreview some of the recent work in this area.

The schemes in [8] and [11] are proposed for linear modu-lation mode. Celanovic [8] proposed a SVPWM based schemebased on the 3-D Euclidean vector system. This scheme mainlyfocuses on calculation of on-times in the linear mode. Seo [11]proposed a scheme for a three-level inverter based on two-levelSVPWM. The three-level space vector diagram is divided intosix two-level space vector diagrams. This division is simple andobvious for a three-level space vector diagram, but cannot be di-rectly applied to a -level inverter. Therefore, as level 3increases, complexity and computation both increase.

In the recent literature [12]–[14], overmodulation for mul-tilevel inverters has been reported. McGrath [12] explains thebehavior of the key multilevel carrier based PWM methods fordiode clamped, cascaded, and flying capacitors topologies in theovermodulation region. Mondal [13] performs SVPWM basedovermodulation on a three-level NPC inverter. The on-time cal-culation equations differ for every triangular section at any mod-ulation index. Due to increased computational complexity, it iscumbersome to extend this scheme to a -level inverter 3 .Saeedifard [14] uses classification algorithm in overmodulationrange for SVPWM of a three-level NPC inverter. It is not clear,how it can be extended to a -level inverter . In over-modulation range, [13], [14] modify the trajectory of referencevector by using lookup tables.

This paper presents a significantly different approach from allaforementioned references and provides a general solution. It isbased on stator coordinate system, and hence can be easily im-plemented with existing outer control loops for speed or torque.The salient features of the proposed scheme are as follows.

• Simple on-time calculation due to the use of a two-levelgeometry based on-time equations. The on-time calcula-tion equations for linear and overmodulation mode do notchange with the position of reference vector like the tradi-tional approach in [13] and [15].

• Normally to model the nonlinearity of the overmodulationregion, the solution to nonlinear equations or lookup tablesare required. They are not used in the method used for im-plementing overmodulation in this paper, leading to sim-plicity of implementation.

• There are 1 triangles in a sector of the space vectordiagram of a three-phase -level inverter. The trianglewhere the reference vector is located, is identified as aninteger using a simple algebraic expression. We call

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518 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

Fig. 1. Five-level cascaded H-Bridge inverter topology.

a triangle number, it implies the th triangle amongthe 1 triangles in a sector. The triangle leads tothe simplicity and flexibility of optimizing the switchingsequences.

• The major feature of the proposed scheme that it can beused for any -level 3 inverter without significantincrease in computations.

The proposed scheme is explained with the help of a five-level cascaded H-bridge inverter (also called cascaded inverter)topology shown in Fig. 1. The scheme is then extended to a

-level inverter. The scheme is equally applicable to neutralpoint clamped (NPC) topology [16].

The paper is organized in eight sections. Section II introducesvarious modulation modes. Section III introduces the basic ideaof calculating on-times in the proposed scheme. Section IV ex-plains the proposed algorithm for a five-level inverter. Section Vexplains the implementation for a five-level inverter. Section VIshows the experimental results for a five-level cascaded inverter.Section VII explains the extension of the proposed scheme to a

-level inverter. Section VIII concludes the paper.

II. MODULATION INDEX AND MODES OF MODULATION

In this paper, we define modulation index as[4], where is the peak value of funda-

mental voltage generated by the modulator and is thepeak value of fundamental voltage at six-step operation. For a

-level cascaded topology 2 1 ,where is the dc link voltage on each H-bridge as shownin Fig. 1. For a NPC topology [16] 2 ,which is same as two-level inverter [4]. Based on the valueof the modulation index 0 1 , there arethree modes of operation [4], namely sinusoidal mode orlinear mode 0 0.907 , overmodulation modeI 0.907 and overmodulation mode II

1 . The value of marks the boundaryof overmodulation I and II.

The scheme proposed by Holtz [4] is to modify the magni-tude and phase of the reference voltage, to achieve the voltagecontrol in overmodulation range. In [4], a value of 0.952 is usedfor . Methods such as [5] and [13] also use0.952. Tripathi [6] obtains a higher value of as 0.9535

Fig. 2. Space vector diagram for first sector of a two-level inverter.

through angular velocity balance of the flux displacementvector. In this paper, the value of is taken to be 0.9535and a strategy similar to [6] is used. The two-level basedovermodulation schemes such as [5], [17] can also be easilyextended to a multilevel inverter using the implementationproposed in this paper.

III. PROPOSED IDEA OF ON-TIME CALCULATION

FOR A MULTILEVEL INVERTER

The basic idea of space vector modulation is to compensatethe required volt-seconds using discrete switching states andtheir on-times.

In a two-level inverter, on-time calculation [10] is based onthe location of the reference vector within a sector , 16, where “ ” signifies that can take any integer value from 1to 6.

For the geometry of a sector shown in Fig. 2, the on-times arecalculated as

(1)

(2)

(3)

In (2), 2 is the height of a sector , which isan equilateral triangle of unity side. In (1)–(3), 1 2where is the switching frequency.

Fig. 3(a) shows the space vector diagram of first sector ofa five-level inverter. Each sector can be split into 16 triangles

, where 0 15. In this figure, is the reference

GUPTA AND KHAMBADKONE: GENERAL SPACE VECTOR PWM ALGORITHM 519

Fig. 3. Space vector diagram—virtual two-level from five-level.

vector of magnitude at an angle of with axis. We definea small vector , which describes the same point in shiftedsystem , see Fig. 3(b). It makes angle with theaxis.

The volt-seconds required to approximate the small vectorin the shifted system should be equal to those re-

quired for actual vector in the original system . Hence,we can obtain the on-times for any reference vector by findingthe on-times of respective small vector .

First, we identify the triangle where the required reference islocated and then obtain the coordinates of the smallvector. The on-time calculations can be performed by usingthe geometry shown in Fig. 3(b), which would result in thesame on-time equations as those for a classical two-level SVM(1)–(3). Since the triangles within any sector of a -level inverterare analogous to a sector of a two level inverter, this idea can beextended to any level. For example; if is taken as zero vectorthen triangle can be assumed similar to sector 1 of atwo-level inverter, as per Fig. 2 and Fig. 3(b). Thus, multilevelon-time calculation problem is converted to a simple two-levelon-time calculation problem. This method is described in detailin [10] for a three-level inverter.

In the proposed method, since triangle is considered as thebasic unit, any suitable vertex can be chosen as virtual zerovector. For example, for triangle in Fig. 3(a), any of the threevertices , or can be chosen as a virtual zero vector andoptimal switching sequence [18] can be formed. The order inwhich on-times , , and are used, depends on the order ofarranging the switching states.

IV. OPERATION OF FIVE-LEVEL INVERTER IN

LINEAR AND OVERMODULATION MODE

The space vector diagram of a three-phase voltage source in-verter is a hexagon, consisting of six sectors. Here, the operationis explained for the first sector, the same is applicable for othersectors too.

Fig. 4. Space vector diagram of the first sector of a five-level inverter showingsinusoidal mode, 0� m <0.907.

For a given position of the reference vector, the sector of op-eration 1 6 and its angle 0 60 withinthe sector is determined by using (4) and (5), respectively

(4)

(5)

In (4) and (5), 0 360 is the angle of the referencevector with respect to axis, is standard math function “in-teger” and is standard math function “remainder.”

A. Sinusoidal Modulation Mode 0 0.907

In this mode, the reference vector , moves on a circulartrajectory as shown in Fig. 4. The tip P of the reference vector

can be located in any of the 16 triangles; . PerSection III, a triangle in Fig. 4 can be treated as a sector of atwo-level inverter. The objective here is to identify the trianglein which the point is located, subsequently using the smallvector analogy in the virtual two-level geometry, the on-timesfor this triangle can be calculated using two-level on-times(1)–(3).

For simplicity, it can be assumed that the sectorin Fig. 4 consists of two types of triangles: type 1 and type 2. Atype 1 triangle has its base side at the bottom, e.g., triangle ,

. A type 2 triangle has its base side at the top, e.g., triangle, .

The search for the triangle that has point P can be narroweddown by using two integers and , which are dependent onthe coordinate of point P as

(6)

In (6), signifies part of the sector between the linesand , e.g., in Fig. 4

2, it signifies the part of the sector between line segmentsand . In (6), signifies part of the sector between

the lines and 1 , e.g., in Fig. 4 1, itsignifies the part of the sector between line segments and

. These two regions are inclined at 120 . Geometrically,the values of and , signify the intersection of these tworegions. This intersection is either a triangle or rhombus. For


the reference vector in Fig. 4(a), 2 and 1, i.e., theintersection is rhombus where the tip P of referencevector is situated.

This rhombus is made of two triangles and . Letbe the coordinates of the point P with respect to the

point , obtained as

(7)

The slope of is and the slope of diagonalis . The triangle where point P is located can be determined

by comparing the slope of with . Slope comparisonis done by evaluating the inequality , leading tofollowing two results on small vector and triangle number

.1) : The point P is within the triangle and

the small vector is represented by. The triangle number is obtained as

(8)

2) : The point P is within the triangle and the

small vector is represented by 0.5. The triangle number is obtained as

(9)

These two results can be generalized to triangles of type 1 andtype 2 respectively. For example; when the point P is in triangle

, inequality will be true because triangle isa triangle of type 1. The small vector is represented

by . In (8) and (9), “ ” symbolizes a triangle and“ ” the triangle number. Hence, is an integer and signifiesth triangle in the sector.

Having determined the small vector ( , ) for the ref-erence vector, the on-times are now calculated using (1)–(3).The triangle in a sector is identified as an integer using asimple algebraic expression (8) or (9). It is a byproduct of thesmall vector determination process, so no other computation isrequired. It greatly simplifies the PWM process as switchingstates can be easily mapped with respect to the triangle number

. The triangle number is formulated to provide a simpleway of arranging the triangles, leading to ease of identificationand extension to any level.

The flowchart in Fig. 7(b) shows the determination ofon-times and triangle number for the circular trajectory ofreference vector.

B. Overmodulation Mode I 0.907 0.9535

This region is marked by nonlinearity. In Fig. 5, the thickdotted circle shows the desired trajectory of the referencevector . Traditionally, depending on the , the trajectory ismodified and tip P of the actual vector moves on trajectory

shown in thick solid lines. i.e. first it moves alongthe circular track , then along the linear track onthe side of the sector and finally along thecircular track . This modification in trajectory is intended

Fig. 5. Space vector diagram of the first sector of a five-level inverter showingovermodulation mode I, 0.907 � m < 0.9535.

to compensate for the loss in volt-secs. The linear movementalong is called hexagonal track in this paper.

We follow an approach similar to [6], to compensate forthe loss in volt-secs by directly modifying the on-times of theswitching vectors on circular track rather than modifying thereference vector.

Let be the angle where the reference vector crosses thehexagon track, shown by the dotted arrow in Fig. 5. For

3 the vector moves on hexagonal track and forremaining part of the sector on circular track. Using cartesiangeometry, angle is obtained as

(10)For a given , is a fixed number, so it need not be calcu-

lated in every switching period.1) Hexagonal Portion 3 : For hexagonal

track, using cartesian geometry, the coordinates of the tip P ofvector are given in terms of angle and level of inverter ,as

(11)

Knowing the coordinates of from (11), theon-times and triangle number can be obtained similar to linearmode, as explained below.

We defined two integers and for (6) to find the trianglein which point P lies. Using the same definition of and ,to find the triangle on which point P lies, these two integers arenow given as

(12)

The tip of the vector resides on one of the four triangles, , and . These triangles are of type 1. Using this

fact, the small vector can be directly obtained from, without performing slope comparison. It is given as

(13)


Knowing , (1) is used to determine the on-time .Similar to two-level, on-time is zero for hexagonal track,therefore . Triangle number is calculated using(8).

Flowchart in Fig. 7(c) shows the on-times and trianglenumber calculation. Number of computations required forhexagonal track in Fig. 7(c) are less than that for circular trackin Fig. 7(b).

2) Circular Portion (0 and 33): Here, on-times are obtained using (1)–(3) as described

before for the linear mode. However, on-times are modified tocompensate for the loss of volt-secs during the linear trajectoryas described below.

In the overmodulation mode I, at a modulation index , theloss in volt-seconds over a sector is proportional to 0.907[6]. Maximum possible value of is 0.9535. Therefore, max-imum possible loss in volt-seconds over a sector is proportionalto (0.9535-0.907). Let us define a compensation factor as theratio of actual loss in volt-secs and maximum loss in volt-secs.It is given as

(14)

Compensation factor is used for modification of on-timesfor the volt-secs compensation. The varies between 0 and 1,for between 0.907 and 0.9535. For a given , is a fixednumber, and hence need not be calculated in every modulationcycle. Further details on can be referred in [6].

In Fig. 5, for the circular portion, the point P can be withinany of the triangles . Type 1 triangles , , ,and have their two vertices on the side of sector.Type 2 triangles , and have their one vertex onthe side of sector. Let the on-times of the three verticesbe , , and obtained from (1)–(3) through linear mode ofmodulation. For the two types of triangles, these on-times aremodified differently as explained below.

• Modifications for Type 1 triangle: Let the on-times of thetwo vertices which are on the side of hexagon be and ,then the modified on-times are given as

(15)

The modifications of on-times in (15) effectively reducethe on-times of the inner vector using and increase theon-times of the outer vectors. It is explained in [6] that suchscheme is suitable for fast close loop operation. Similarly,the on-times for the type 2 triangle are modified.

• Modifications for Type 2 triangle: Let the on-times of thetwo vertices that are not on the side of hexagon be and

, then the modified on-times are obtained as

(16)

Fig. 6. Space vector diagram of the first sector of a five-level inverter showingOvermodulation Mode II, 0.9535� m <1.

The modifications of on-times in (16) effectively reducethe on-times of the inner vectors and increase the on-timesof the outer vector using .

In (15) or (16), there is no compensation at 0.907 as0. At 0.9535, the compensation is maximum as

1 and 0, which corresponds to complete movement alongthe hexagonal track.

For a given , (14) and (15) or (16) are only modificationsrequired to modify the on-times. No other lookup table or solu-tion to complicated equations is required. Therefore, complexityof implementing overmodulation reduces. It also shows the lowcost of implementing overmodulation on a microcontroller.

Above 0.9535, the circular part of the trajectory vanishes andthe on-time obtained from (15) or (16) is negative which ismeaningless. Above 0.9535, another mode is used called over-modulation II.

C. Overmodulation Mode II 0.9535 1

Switching in overmodulation II is characterized by a holdangle , shown by the dotted arrow in Fig. 6. For

3 , the tip P of the vector moves on hexagonal track.In Fig. 3, let vectors at vertices and be addressed aslarge vectors. There are a total of six large vectors for the com-plete space vector diagram. For 0 and 3

3, the vector is held at one of the large vectors.Normally, is a nonlinear function of modulation index and

obtained by a lookup table. In this paper, the hold angle isobtained using a strategy similar to [6] where is calculatedby obtaining the same average normalized angular velocity overa sector as the angular velocity of the reference vector. For thedrives application if is maintained, the angular velocity isproportional to modulation index . Hence, at a given , thetime to traverse an angle is equal to where is a con-stant. Similarly, time: i) to cover the linear portion is equal to

3 2 0.9535; ii) to hold the vector at the large vec-tors of a sector is 2 1.0; and iii) to cover whole sector is

3 . A time balance equation can be written as

(17)


Fig. 7. Flowchart: (a) main routine: overall modulation process, (b) task 1:subroutine to calculate the on-times and triangle number for the circular track,and (c) task 2: subroutine to calculate the on-times and triangle number for thehexagonal track

Simplification of (17) leads to the following expression forholding angle as:

(18)

In (18), for a given only two arithmetic operations, i.e.,one division and one subtraction are required to obtain the holdangle . It shows the simplicity of implementing overmodula-tion II.

Fig. 8. Simplified block diagram of the proposed algorithm.

For 3 , the on-time calculation is same asthat during the hexagonal trajectory in overmodulation mode I.For 0 and 3 3, the vector is held atone of the six large vectors. At 1.0, hexagonal track van-ishes and vector is only held at the six large vectors sequen-tially. This is six-step operation similar to two-level inverter.Therefore, a multilevel inverter when operated at 1.0,looses its multilevel characteristics.

V. IMPLEMENTATION FOR A FIVE-LEVEL INVERTER

The implementation for a five-level inverter can be under-stood with the help of following block diagram. It has two basicunits namely a processing unit and a mapping unit.

A. Processing Unit

Processing unit is basically a microcontroller. The basescheme for processing unit is explained in previous section, andsummarized in flowchart in Fig. 7. It determines parameterssuch as sector, triangle, and calculates on-times. These detailsare subsequently used by mapping unit to generate gatingsignals.

B. Mapping Unit

The job of mapping unit is to generate gating signals for theinverter. It uses memory to store sequences of switching states.A switching sequence is a set of switching states to be appliedin a switching period. The structure of a switching sequence de-pends on the trajectory of the vector. There are three possibletrajectories: i) circular track: for linear modulation mode andsome part of overmodulation I; ii) hexagonal track: for somepart in overmodulation I and overmodulation II; and iii) holdmode: in overmodulation II. Due to the difference in structuresof switching sequence among the trajectories, three separatememory units M–CR, M–HX, and M–HL are used in mappingunit, where CR, HX, and HL stand for circular, hexagonal, andhold, respectively. The flowchart in Fig. 7(a) introduces an in-teger parameter , called as track index. It is used for realtimeimplementation. It helps in identifying the memory unit with re-spect to track using three values as: i) 0 for circular track;ii) 1 for the hexagonal track; and iii) 2 for the holdmode. The is independent of the level of inverter.

There exist 125 5 switching states for five-level inverter, where , , 2 1 0 1 2 . In Fig. 3, weshow the switching states for first sector in the space vector di-agram. A phase-leg state describe the “ON”or “OFF” conditions of the switches in the respective phase. InFig. 1, , , and ,


Fig. 9. Switching state at a memory location—ON/OFF signals for the powerswitches.

where . Hence, essentially four signals are re-quired to control the eight switches of a phase-leg. Equivalently,each requires 4 b to store the state of the re-spective phase-leg. To this end, 12 b of memory in Fig. 9 storesa switching state at a memory location in M–CR, M–HX, andM–HX units. Due to the difference in the switching sequencesin these units, the order in which switching states are organizedin memory units differ from one another.

1) Memory Unit for Circular Track (M–CR): On circulartrack tip P of the reference vector is positioned within a triangle

. There are redundant switching states at the ver-tices of the triangles. Due to redundant states, there could beseveral switching sequences for a triangle. For example, for therange 0.5236 0.7854, at a switching period, the tip ofthe reference vector can be situated in triangle . For this tri-angle, following four sequences can be formed with minimumswitching losses.

Sequence 1:

.Sequence 2:

.Sequence 3:

.Sequence 4:

.The subscript on a switching state is stage of the sequence.

Stages 0 3 and 3 0 are the set and reset part of the sequence.Similarity to a two-level SVPWM can be seen here. Subscript“0” and “3” represent the same vertex, and correspond to virtualzero vector of the two-level space vector diagram.

Generally, a continuous PWM sequence have four stages asshown above, and a discontinuous PWM sequences have threestages [19]. The counter in processing unit generates stagenumber using the on-times , and . Here, 0 3for continuous SVM and 0 2 for discontinuous SVM.

Among the various switching sequences for a triangle, onlyone can be applied at a switching period. Following examplesexplain the selection of a switching sequence using triangle .

Example 1: Common Mode Voltage Reduction—In [20],a common mode voltage reduction scheme is given. Thefive-level ( -level) space vector diagram is converted toequivalent three-level ( -1-level) space vector diagram byretaining the switching states which generate zero commonmode voltage. Due to the absence of redundancies, onlyone switching sequence exists for every triangle.Example 2: Intertriangle Switching Losses Minimiza-tion—There are two possible transitions of the referencevector for triangle . The transition depends on :

Fig. 10. Memory address for circular track.

i) for the range 0.5236 0.6614, the transition is, and Sequence 1 (or 2) is selected and ii) for the

range 0.6614 0.7854, the transition is ,and Sequence 3 (or 4) is selected. Here, “ ” signifiestransition between triangles.Example 3: DC-link Balancing in NPC topology—DC-link balancing is a key issue [21], [22] for NPC topology.To have a better control authority over dc-link balance, asequence is selected whose virtual zero vector has highestduty ratio among the three duty ratios, i.e., , , and

for triangle . Therefore, in triangle , Sequence1 (or 2) is selected if is maximum, Sequence 3 is se-lected if is maximum and Sequence 4 is selected ifis maximum. This technique is well known for three-levelinverter.

These examples show that the selection of a switching se-quence is dependent on the modulation scheme. For a givenscheme, a set of relevant switching sequences can be identifiedfor every triangle and stored in memory unit in contiguous lo-cations. This is an off-line process.

To this end, an 11-b address is given in Fig. 10. This addressidentifies a memory location in M-CR unit. It is divided intofour parts: i) “Sector”: 3 b , as for sector number

, 1 6; ii) “Triangle”: 4 b , as for trianglenumber , 15; iii) “Sequence”: 2 b , con-sidering a retention of maximum four sequences per triangle;and iv) “Stage”: 2 b , considering three or fourstages per sequence with respect to continuous or discontinuousSVM, respectively.

For a given modulation scheme, at any switching period, theprocessing unit calculates these parameters. Using these param-eters, a memory location (switching state) is identified. Sincethe contents of a memory location represent “ON” or “OFF”condition for the switches of the inverter, they can be directlyapplied for generating gating signals. The proposed mappingconcept can be used to implement a variety of schemes as ex-plained above. It shows the generality of the proposed mappingconcept.

2) Memory Unit for Hexagonal Track (M–HX): On hexag-onal track in Figs. 5 and 6, the tip P of the vector moves along

on a side of one of the triangles , , , and. There is one switching state at a vertex on hexagonal

track. The switching states at the nearest two vectors are utilizedto form a switching sequence. For example; for triangle ,the switching sequence is

. Conclusively, a switching se-quence on hexagonal track has only two stages. The counter inprocessing unit generates stage number using on-timesand .

To this end, an 8-b address is given in Fig. 11. This addressidentifies a memory location in M–HX unit. It is divided intothree parts: i) “Sector”: 3 b ; ii) “Triangle”: 4 b

; and iii) “Stage”: 1 b , as only two stages


Fig. 11. Memory address for hexagonal track.

Fig. 12. Memory address for hold mode.

Fig. 13. Voltage V , current I , and FFT of voltage V at m =0.90.

exist. Due to the absence of redundant switching states, onlyone switching sequence exists for a triangle on hexagonal track.

3) Memory Unit for Hold Mode (M-HL): In hold mode, thevector is held at a large vector. The switching state at thisvertex, e.g., (2, 2, 2) is applied for full switching period. Un-like other two tracks, the switching sequence contains only onestage in hold mode. To this end, a 3-b address is given in Fig. 11,to identify a memory location in M–HL unit. The “Triangle,”“Sequence,” and “Stage” are not required here.

This implementation is advantageous as compared to imple-mentation of carrier based schemes for a multilevel inverter. Incarrier based schemes, a separate controller might be requiredfor every H-bridge [20] as every phase-leg is controlled sepa-rately. In such implementation, the synchronization of the con-trollers might lead to implementation complexity. On the otherhand, using the proposed scheme a single controller unit gener-ates the gating signals for all the switches of the inverter.

The proposed scheme is applicable to both NPC and cascadedinverter. For a given level, the two topologies have same spacevector diagram and equal number of power switches, so the costof peripherals does not change. The processing unit is same forboth the topologies. For a given level, there are equal number ofcontrollable switches in these topologies but their arrangementis different. Hence, for a given switching state, the gating signalsor the set of bits at a memory location in Fig. 9 differ for the



two topologies. Hence, the mapping unit should be redesignedwhile changing from one topology to the other. We show theimplementation of the proposed scheme for a three-level NPCinverter in [23].

VI. EXPERIMENTAL RESULTS FOR FIVE-LEVEL

CASCADED INVERTER

The algorithm is implemented using a dSPACE DS1104 card,due to its availability. Owing to the simplicity of the algorithm


Fig. 16. Line voltage for seven-level inverter at (a)m = 0.89, (b)m = 0.93, and (c)m = 0.97.

it can be easily implemented on a fixed point DSP as well. Thealgorithm is tested on a laboratory prototype of a five-level cas-caded inverter. The test was performed on a 0.75-kW inductionmotor at 100 V, fundamental frequency 50 Hzand sampling frequency 5 kHz. Here, is voltageapplied on each H-bridge module per Fig. 1.

Figs. 13–15(a) show the line voltage and current ata modulation index of 0.90, 0.94, and 0.98 corresponding tolinear mode, overmodulation mode I and overmodulation modeII, respectively.

Figs. 13–15(b) show the linear RMS FFT of line voltageat a modulation index of 0.90, 0.94, and 0.98 corresponding tothe linear mode, overmodulation mode I and overmodulationmode II, respectively. In Figs. 13–15(b), the top right quarteris complete FFT. This FFT is 10 vertically magnified to studyvarious harmonics which occupies the remaining three quarters.Weighted total harmonic distortion WTHD [19] is given to studythe harmonic losses. The is RMS value of fundamentalcomponent of the line voltage. For a cascaded inverter, theoret-ical RMS value of is given as .The error between experimental and theoretical value is lessthan 1% for the three cases. The error between simulation andtheoretical value is less than 0.4% for at any .

VII. EXTENSION OF THE PROPOSED SCHEME

TO A -LEVEL INVERTER

The block diagram in Fig. 8 describes the proposed schemeand its implementation for a five-level inverter. Some changescan be expected when it is applied to a -level inverter. Wediscuss below, the processing unit with respect to computationalload, and mapping unit with respect to memory requirement.

A. Processing Unit

The processing unit calculates on-times and basic parametersto apply a switching state. The base scheme in Fig. 8 is essen-tially the flowchart in Fig. 7. This flowchart is given for a -levelinverter. The main routine in Fig. 7(a) and sub-routinein Fig. 7(c) use as a linear constant, showing that number ofcomputations are same for any value of . Whereas inFig. 7(b) is independent of . Therefore, the number of compu-tations for the base scheme in processing unit remain same forany value of . Conclusively, the same processing unit can beused for any level without any change.

B. Mapping Unit

Conceptually, the mapping unit for -level is the same asshown in Fig. 8. However, there are the following two structuralchanges in the number of bits at a memory location in Fig. 9 andits address in Figs. 10 and 11.

1) In Fig. 9, for -level, bits are required to store aswitching state at a memory location.

2) The bits required for “Triangle” in Figs. 10 and 11 change,as there are 1 triangles per sector. For example, 7 bare required for “Triangle” part for an 11-level inverter asthere are 100 triangles per sector. Except for “Triangle,”other parts in Figs. 10 and 11 remain unaffected by thechange in .

Commercially available EPROM chips of 1-, 4-, 16-, 32-, and64-kB sizes fulfill the memory requirement of mapping unit,to implement the proposed scheme for three-level, five-level,seven-level, nine-level, and 11-level inverter, respectively. Thisestimation is based on the memory structure shown in Figs. 9–12where the bits at memory location are directly used for gener-ating gating signals. This estimation may change with the mod-ulation scheme. The memory requirement increases with , asswitching states . The size of the memory is reduced to halfif a two-step cascaded memory is used.

Fig. 16(a)–(c) show the line voltage for a seven-levelcascaded inverter at a modulation index of 0.89, 0.93, and 0.97.For this implementation, the same processing unit is used asfor five-level without any change. The mapping unit is modifiedper the requirements of a seven-level inverter. The test was per-formed at 100 V, fundamental frequency 50 Hz,and sampling frequency 5 kHz.

VIII. CONCLUSION

This paper proposes a SVPWM based scheme to performovermodulation for a multilevel inverter, and its implementa-tion. The position of the vector is identified using an integer pa-rameter, called a triangle number. The switching sequences aremapped with respect to the triangle number. The on-times cal-culation is based on on-time calculation for two-level SVPWM.The on-time calculation equations do not change with the tri-angle. A simple method of calculating on-times in the overmod-ulation range is used, hence, a solution to complex equationsand lookup tables are not required. This leads to ease of imple-mentation. There are no significant changes in computation withthe increase in level. The proposed implementation is general innature and can be applied to a variety of modulation schemes.The implementation is shown for a five-level and seven-level


cascaded inverter. The experimental results are provided. Theproposed method can be easily implemented using a commer-cially available motion control DSP or micro-controller, whichnormally supports only two-level modulation.

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Amit Kumar Gupta (S’04) was born in India,in 1978. He received the B.E. degree in electricalengineering from the Indian Institute of Technology,Roorkee, in 2000 and is currently pursuing the Ph.D.degree at the National University of Singapore,Singapore.

From 2000 to 2003, he worked for Bechtel IndiaPvt., Ltd., New Delhi and Samsung Heavy Industries,Ltd., Korea. His research interests include PWM formultilevel converters, power electronics, and motioncontrol.

Ashwin M. Khambadkone (SM’04) receivedthe Dr.-Ing. degree from Wuppertal University,Wuppertal, Germany, in 1995 and the GraduateCertificate in education from the University ofQueensland, Brisbane, Australia.

At Wuppertal, he was involved in research and in-dustrial projects in the areas of PWM methods, field-oriented control, parameter identification, and sen-sorless vector control. From 1995 to 1997, he was aLecturer at the University of Queensland. He was alsoat the Indian Institute of Science, Bangalore, India in

1998. Since 1998, he has been an Assistant Professor at the National Universityof Singapore. His research activities are in the control of ac drives, design andcontrol of power electronic converters, and fuel cell based systems.

Dr. Khambadkone received the Outstanding Paper Award in 1991 and theBest Paper Award in 2002 both which appeared in the IEEE TRANSACTIONS ON

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a general space vector pwm algorithm for multilevel inverters including operation in over modulation...

Documents

overmodulation region

proposed scheme

twolevel inverters

switching vector

level cascaded inverters

reference vector

voltagesource inverters

implementation of svpwm