a low area, switched-resistor loop filter technique for fractional-n synthesizers
TRANSCRIPT
A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable
Oscillator
ISSCC 2010, Session 13.1
M.H. Perrott, S. Pamarti1, E. Hoffman2, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker3, S. Perumal4, B.
Soto5, N. Arumugam, B.W. Garlepp
SiTime Corporation, Sunnyvale, CA, USA1 UCLA, Los Angeles, CA, USA2 Global Foundries, Sunnyvale, CA, USA3 Invensense, Sunnyvale, CA, USA4 Consultant5 SLAC National Accelerator Laboratory, Palo Alto, CA USA
2
Why Switch to MEMS-based Programmable Oscillators?
A part for each frequency and non-plastic packaging- Non-typical frequencies
require long lead times
Same part for all frequencies and plastic packaging- Pick any frequency you want
without extra lead time
Quartz Oscillators MEMS-based Oscillator
We can achieve high volumes at low cost using IC fabrication
source: www.ecliptek.com
3
Architecture of MEMS-Based Programmable Oscillator
MEMS device provides high Q resonance at 5 MHz- CMOS circuits provide DC bias and sustaining amplifier
Fractional-N synthesizer multiplies 5 MHz MEMS reference to a programmable range of 750 to 900 MHzProgrammable frequency divider enables 1 to 115 MHz output
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump Continuously
Programmable
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider
1 to 115 MHz
4
Compensation of Temperature Variation
High resolution control of fractional-N synthesizer allows simple method of compensating for MEMS frequency variation with temperature- Simply add temperature sensor and digital compensation logic
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump
Temp
Freq Error (ppm)
Digital
Logic
Temperature
Sensor
Temp
Freq Compensation (ppm)
Temp
Freq Error (ppm)
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider Continuously
Programmable
1 to 115 MHz
5
The Focus of This Talk
How do we achieve a fractional-N synthesizer withlow area, low power, and low design complexity?
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump
Temp
Freq Error (ppm)
Digital
Logic
Temperature
Sensor
Temp
Freq Compensation (ppm)
Temp
Freq Error (ppm)
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider Continuously
Programmable
1 to 115 MHz
6
Analog Versus Digital Fractional-N Synthesizer?
Analog PLL wins in 0.18u CMOS for low power
Analog PLL
Digital PLL
+ Low power- Large loop filter
(Higher power)
+ Smaller loop filter- Difficult in 0.18 CMOS
Can we achieve a low area (and low power) analog PLLwith reduced design effort?
(Dominated by C2)Reg
D Qdiv(t)
D Q
reset
1
1
ref(t)
up(t)
C1down(t)
R1
C2
vtune(t)
Divider
out(t)ref(t)
DCODivider
div(t)
Time-to-Digital
ConverterDigital
Loop Filter
7
The Issue of Area: What Causes a Large Loop Filter?
Loop filter noise (primarily from charge pump) often dominates PLL phase noise at low offset frequenciesWe will show that- The common approach of reducing loop filter noise leads to
increased loop filter area (i.e., C2 for charge pump PLL)- We can instead increase PD gain to lower the impact of
loop filter noiseLoop filter area can be smaller
Reg
D Qdiv(t)
D Q
reset
1
1
ref(t)
up(t)
C1down(t)
R1
C2
vtune(t)
Divider
Inoise
f
VCONoise
Charge Pump Noise
Output Phase Noise
8
First Step: Model PLL with Charge Pump Noise
Divider
PD
Gain
Z(s) 2 Kv
s
PFDRC
Network VCO
out(t)error(t)
ref(t)
div(t)
Ipump
Reg
D Qdiv(t)
D Q
reset
1
1
ref(t)
up(t)
C1down(t)
R1
C2
vtune(t)
ChargePump
Divider
C2
Inoise
Inoise
f
VCONoise
Charge Pump Noise
Output Phase Noise
1Nnom
9
Increasing Ipump Reduces Input-Referred Loop Filter Noise
Area gets larger since C2 is typically increasedas well to maintain desired open loop gain
Divider
PD
Gain
Z(s) 2 Kv
s
PFDRC
Network VCO
out(t)error(t)
ref(t)
div(t)
Ipump
ChargePump
C2
Inoise
f
VCONoise
Loop FilterNoise
Output Phase Noise
1Nnom
Divider
PD
GainZ(s)
2 Kv
s
PFD Loop Filter VCO
out(t)ref(t)
div(t)
Ipump
C2
LFnoise
1Nnom
LFnoise
2 1
Ipump
2
Inoise
2
Ipump
1
Ipump
10
Increasing PD Gain Reduces Impact of Loop Filter Noise
But how do we increase the PD gain?
Loop filter area does not need to become larger
f
VCONoise
Loop FilterNoise
Output Phase Noise
Divider
PD
Gain2 Kv
s
PFD VCO
out(t)ref(t)
div(t)
LFnoise
1Nnom
LFnoise
2
PD Gain
Nnom2
Z(s)
Loop Filter
Ipump
C2
PD
(t)
Nnom
Ipump
1
PD Gain
PD Gain
1
PD GainKeep Open Loop
Gain Constant
PD Gain Ipump
Impact of Loop Filter Noise on Output
11
PD Gain of Classical Tristate PFD
Compute gain by averaging Up/Down pulses vs. phase error- Note that tristate PFD has a phase error range of 2 Ref periods
Reg
D QDiv(t)
D Q
reset
1
1
Ref(t)
Up(t)
Down(t)
Phase Detector Characteristic
Div(t)
Ref(t)
Up(t)
Down(t)
2
2error
avg{Up(t)-Down(t)}
-2
1
-1
PD Gain = 2
1
Ipump
RC
Network
Ipump
12
Proposed Method of Increasing Phase Detector Gain
Reduce phase detection range to 1/4 of the Ref period- Achieves 8X increase in phase detector gain
How do we capitalize on this reduced range in the filter?
Div(t)
Ref(t)
Up(t)
Down(t)
2
2error
avg{Up(t) - Down(t)}
-2
1
-1
PD Gain = 2
1
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
2 /8error
avg{Up(t) - Down(t)}
-2 /8
1
-1
PD Gain = 2
8
13
Simple RC Network Can Be Utilized
Achieves full voltage range at Vc1 as phase error is swept across the reduced phase detector rangeNote: instead of being influenced by charge pump gain after the PD, we are influenced by (regulated) supply voltage
See also: Hedayati, Bakkaloglu
RFIC 2009Div(t)
Ref(t)
Up(t)
Down(t)
High
Gain
PD
1
-1
R1
C1 Vc1(t)
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
2 /8error
avg{Vc1(t)}
-2 /8
1
-1
PD Gain = 2
8
14
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
QRef(t)
Div_4x(t)
Up(t)
Down(t)
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Tdiv
Tref
Tdiv
Tref2
avg{Up(t) - Down(t)}
Phase Detector Characteristic
PD Gain = Tdiv
Tref
2
12
error
Delay Buffer For Non-Overlapping Up/Down Pulses
1
-1
= 2
8
Implementation of High Gain Phase Detector
Use 4X higher divider frequency- Simple digital implementation
15
Multi-Phase Pulse Generation (We’ll Use it Later…)
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
QRef(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Tdiv
Tref
Short PulseGenerator
Tdiv
Tref2
avg{Up(t) - Down(t)}
Phase Detector Characteristic
error
1
-1
PD Gain = Tdiv
Tref
2
12 =
2
8
16
Overall Loop Filter – Consider Using Charge Pump
Can we remove the charge pump to reducethe analog design effort?
We can use the high gain PD in a dual-path loop filter topology- But we want a simple design!
See also: Craninckx, JSSC, Dec
1998
High
Gain
PD
Ref(t)
Div_4x(t)
w
H(w)C2
Vtune(t)
(High Kv)
Vdd
Gnd
Up(t)
R1
C1
Down(t)
Ipump
Ipump
Vtune(t)
(Low Kv) ref(t)
div(t)
2
8
PDGain
2
2
PDGain
2
Vdd
SupplyGain
ChargePump
Ipump
1+sR1_effC1
1
sC2
1
RCNetwork
IntegrationCap
wz
17
Passive RC Network Offers a Simpler Implementation
Capacitive feedforward path provides stabilizing zeroDesign effort is simply choosing switch sizes and RC values
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
w
Cf+C3
Cf
DC Gain = 1
H(w)
R2
R3
Vc1(t)
Vtune(t)
wz
18
The Issue of Reference Spurs
Ripple from Up/Down pulses passes through to VCO tuning input
Is there an easy way toreduce reference spurs?
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R2
R3
Vc1(t)
Vc1(t)
Vtune(t)
Vtune(t)
19
Leverage Multi-Phase Pulsing
Ripple from Up/Down pulses blocked before reaching VCO- Reference spurs reduced!- Similar to sample-and-hold
technique (such as Zhang et. al., JSSC, 2003)
There is a nice side benefitto pulsing resistors…
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Vc1(t)
Vc1(t)
Mid(t)
Last(t)
R2/2 R2/2
R3/2 R3/2
Cf
Mid(t)Last(t)
Vtune(t)
Vtune(t)
20
Pulsing Resistor Multiplies Resistance!
Resistor only passes current when pulsed on- Average current through resistance is reduced according
to ratio of On time, Ton, versus pulsing Period, Tperiod- Effective resistance is actual resistance multiplied by ratio Tperiod/Ton
Resistor multiplication allows a large RC time constantto be implemented with smaller area
Pulse_On(t)
Ton
Tperiod
R/2R/2 Ton
TperiodRR_eff =
21
Parasitic Capacitance Reduces Effective Resistance
Spice simulation and measured results reveal that>10X resistor multiplication can easily be achieved
Parasitic capacitance stores charge during the pulse “On” time- Leads to non-zero current through resistor during pulse
Off time- Effective resistance reduced
Ton
Tperiod
Pulse_On(t)
CpCp Cp CpCpCp
R/4R/4 R/4 R/4 Ton
TperiodR<R_eff
22
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
R3/2 R3/2
Cf
Mid(t)
Last(t)
Vtune(t)
w
Cf+C3
Cf
1
H(w)
wz
R3_eff Cf
1wz =
Ton
Tperiod
C3
For robust stability, PLL zero should be set well below PLL bandwidth of 30 kHz- Assume desired wz = 4 kHz- Set Cf = 2.5pF (for low area)- Required R3_eff = 16 MegaOhms
Large area
Proper choice of Ton and Tperiod allows R3_eff = 16 MegaOhms to be achieved with R3 = 500 kOhms!
Switched Resistor Achieves PLL Zero with Low Area
23
The Issue of Initial Frequency Acquisition
During initial frequency acquisition, Vtune(t) must be charged to proper bias point- This takes too long with R3_eff = 16 MegaOhms
How do we quickly charge capacitor C3 during initialfrequency acquisition?
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
Cf
Vtune(t)
C3 = 35pF
R3_eff = 16MegaOhms
24
Utilize Switched Capacitor Charging Technique
Charge C3 high or low only when frequency error is detected- No steady-state noise penalty, minimal power consumption
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
Cf
Vtune(t)
C3
R3/2 R3/2
Cc
Vdd
Gnd
Counter Count > 4
Count < 4Ref(t)
Tdiv_4x
Tref
Count
Charge High
Ref(t)
Charge Low(t)
Charge High(t)
Div_4x(t)
Charge Low
Connect
Connect(t)
25
CppSim Behavioral Simulation of Frequency Locking
Switched capacitor technique allows relativelyfast frequency locking
0
0.5
1
vtune
1
charge_high
0 10 20 30 40 50 60
1
Time (microseconds)
charge_low
0
0
26
CMOS and MEMS Die Photos Show Low Area of PLL
Active area:- VCO & buffer &
bias: 0.25mm2
- PLL (PFD, Loop Filter, divider): 0.09 mm2
- Output divider: 0.02 mm2
External supply- 1.8/3.3V
Current (20 MHz output, no load)- ALL: 3.2/3.7mA- VCO: 1.3mA- PLL & Output
Divider: 0.7mA
27
Measured Phase Noise (100 MHz output)
Suitable for most serial applications, embedded systems and FPGAs, audio, USB 1.1 and 2.0, cameras, TVs, etc.
Integrated Phase Noise:17 ps (rms) from 1 kHz to 40 MHz
Ref. Spur: -65 dBc
-90 dBc/Hz
100 Hz 40 MHz30 kHz
-140 dBc/Hz
28
−50 0 50 100−50
−40
−30
−20
−10
0
10
20
30
40
50
Temperature (degC)
Fre
qu
ency
Var
iati
on
(P
PM
)
Frequency Variation After Single-Temperature Calibration
< 30 ppm across industrial temperature rangewith single-temperature calibration
1013 Parts
29
Conclusion
A MEMS-based programmable oscillator provides an efficient solution for industrial clocking needs- Programmability of frequency value simplifies supply chain
and inventory management- Leveraging of semiconductor processing, rather than
custom tools for quartz, allows low cost and low lead timesProposed fractional-N synthesizer allows low area, low power, and reduced analog design effort- High gain phase detector lowers impact of loop filter noise- Switched resistor technique eliminates the charge pump
and reduces area through resistor multiplication- Switched capacitor frequency detection enables reasonable
frequency acquisition time with no noise penalty
Frequency references have entered the realm ofintegrated circuit design and manufacturing
30
Supplemental Slides
31
Noise Analysis (Ignore Parasitic Capacitance of Resistors)
Assumption: switched resistor time constants are much longer than “on time” of switches- Single-sided voltage noise contributed by each resistor
is simply modeled as 4kTReff (same as for a resistor of the equivalent value)
Note: if switched resistor time constants are shorter than “on time” of switches- Resistors contribute kT/C noise instead of 4kTReff- We would not want to operate switched resistor filter in
this domain since time constants would not be boosted
Φref(t) R1_eff R2_eff
R3_eff
C1 C2 C3Cf
Vtune
Φdiv(t)
8
2π
Voltage
Signal
4kTR1_eff 4kTR2_eff 4kTR3_eff
Vdd
2
PDGain
SupplyGain
32
Issue: Nonlinearity in Switched Resistor Loop Filter
Nonlinearity is caused by- Exponential response of
RC filter to pulse width modulation
- Variation of Thold due to Sigma-Delta dithering of divide value
Note: to avoid additional nonlinearity, design divide value control logic to keep Ton a constant value
Ref(t)
Div_4x(t)
Up
Down
Vc1
Vc1
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2
C1
Vc1[k]Vc1[k-1] Vc1[k+1]
Ton
Tperiod
Thold
33
Nonlinearity Due to Pulse Width Modulation
Pulse width modulation nonlinearity is reduced as ratio ΔT/(R1C1) is reduced- If ΔT/(R1C1) is small:
Keep Ton constant to avoid increased nonlinearity!
Ref(t)
Div_4x(t)
Up
Down
Vc1
Vc1
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2
C1
Vc1[k]Vc1[k-1]
Thold Ton
Ton/2+ΔT Ton/2-ΔT
34
Nonlinearity Due to Hold Time Variation
Hold time nonlinearity is reduced as changes in Thold(due to divide value dithering) are reduced- Reduce order of MASH Σ−Δ
Benefits are offset by reduced noise shaping of lower order Sigma-Delta
- Reduce step size of MASH Σ−Δ
Achieved with higher VCO frequency
Ref(t)
Div_4x(t)
Up
Down
Vc1
Vc1
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2
C1
Vc1[k]Vc1[k-1]
Thold Ton
35
Nonlinearity Is Not An Issue For This Design
Folded quantization noise due to nonlinearity is reasonably below other noise sources for this design- However, could be an issue for a wide bandwidth PLL design
Use (CppSim) behavioral simulation to evaluate this issue
Other PLLNoise Sources
Phase noise referred toVCO carrier frequency
Folded Sigma-DeltaQuant Noise
36
Div(t)
Ref(t)
Up(t)
Down(t)
Phase Detector Characteristic
2error
avg{Up(t)-Down(t)}
-2
1
-1
PD Gain = 2
2
Ipump
RC
Network
Ipump
High
Gain
PD
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
What If We Use A Pure Charge Pump Loop Filter?
PD Gain increased by 2 compared to tristate PFD- Reduced phase error range and max/min current occurs
High linearity despite charge pump current mismatch- Similar to XOR PD, but noise is reduced