Fusion Engineering and Design 71 (2004) 159–165

A low-cost galvanic isolated fast PCI transient recorderwith signal processing capabilities

Miguel Correia∗, A.J.N. Batista, A. Combo, Nuno Cruz, P. Carvalho,Carlos Correia, J. Sousa, C.A.F. Varandas

Associação EURATOM/IST, Centro de Fusão Nuclear, Instituto Superior Técnico, Av. Rovisco Pais, 1049-001 Lisbon, Portugal

Available online 7 June 2004

Abstract

A new transient recorder module architecture was developed to fulfil many of today’s requirements of data acquisition forplasma diagnostics on fusion experiments. This architecture is supported by the availability of new high-density devices inthe fields of digital signal processors and programmable logic devices, which can provide features such as multi-channel datareadout in real-time, real-time digital signal processing and a large quantity of onboard memory. This paper describes the designand implementation of a transient recorder module in compliance with this new architecture, which, along with the developedsoftware, can be efficiently used either as a stand-alone or integrated in a multi-unit data acquisition system. The module enclosesall aforementioned capabilities in an eight-channel peripheral component interconnect (PCI) unit. All channels are differential,galvanic isolated at 1 kV and over-voltage protected. Acquisition rate is 2 M samples per second with 14-bit resolution. Localdata storage capacity is 256 M samples.© 2004 Elsevier B.V. All rights reserved.

Keywords: Data acquisition; Transient recorder; PCI; Real-time; Signal processing

1. Introduction

Control and data acquisition systems for plasmadiagnostics are continuously required to keep upwith the ever-growing demands of fusion experi-ments. These requirements include, among others,multi-channel data readout, real-time signal process-ing, a wide range of timing/triggering solutions anddata cleanness.

Over the last years, the Industry has been able todeliver the key components which support or even

∗ Corresponding author. Tel.:+351-239410108.E-mail address: miguelfc@lei.fis.uc.pt (M. Correia).

motivate these advances. In the Silicon devices area,latest generation digital signal processors (DSP) andfield programmable gate arrays (FPGA) play a ma-jor role as motivators for new architectural solutions[1–3], especially when combined with the features ofhigh performance buses, such as peripheral compo-nent interconnect (PCI), also made readily availableto designers.

The module discussed in this paper, referred to as“PCI-TR-256”, aims at incorporating these advantagesin a multi-channel transient recording architecture thatcomprises eight galvanic isolated analogue inputs ca-pable of acquiring simultaneously on all channels at arate up to 2 MHz, and has a local memory capacity of

0920-3796/$ – see front matter © 2004 Elsevier B.V. All rights reserved.doi:10.1016/j.fusengdes.2004.04.028

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256 M samples, at a 14-bit resolution. Board architec-ture relies on state-of-the-art hardware components,namely latest generation DSP and FPGA devices, soas to implement these and other functionalities. Rel-evant aspects of the various software packages thathave been developed to obtain a fully functional unitwill also be addressed.

2. Architecture

The board’s architecture comprises four mainblocks, as depicted inFig. 1:

1. Acquisition channels: To achieve galvanic isola-tion of each channel, the analog-to-digital con-verter (ADC) output data is serialized and sent to a

Fig. 1. The PCI-TR-256 module architecture.

magneto-coupler. Each channel has its own dc–dcisolated power supply.

2. FPGA: To implement data de-serialization, syn-chronism, data buffering and interface with theDSP.

3. Timing: Generates and distributes timing sig-nals within and towards other modules. ThePCI-TR-256 includes connectors to allow syn-chronization of up to eight boards within the samechassis.

4. DSP: Handles not only data processing tasks, butalso interfaces with the PCI bus and performs con-trol of onboard memory up to 512 MB SDRAMin DIMM format. This enables the PCI-TR-256 totake the advantages of a low-cost, large capacityindustry standard.

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Fig. 2. Acquisition channel diagram.

The DSP, FPGA and serializer PLD can be pro-grammed onboard through their join test actiongroup (JTAG) interfaces. This possibility permits thePCI-TR-256 to be quickly and easily re-configured.

2.1. Acquisition channels

Fig. 2shows the diagram of one acquisition channel.The PCI-TR-256 has a total of eight differential

input channels that receive analog signals from the37-pin sub-miniature D-type connector located at themodule front panel. Every channel is galvanic isolated,up to 1 kV, by means of a magneto-coupler device.

The differential signal is conditioned by a four-waygain switch, with available voltage ranges of±10,±2.5,±0.5, and±0.1 V and filtered through a 1 MHzpassive third order Butterworth low-pass filter. Thisisolated analogue path minimizes electrical cross-talk,especially the noise induced by common-mode highvoltages.

After filtering, the signal is converted by a 14-bit2 MSPS ADC (Linear Technology, LTC® 1414)in two’s complement binary parallel format. Thisword is then serialized by a Xilinx® CPLD [4]

into a serial bit stream, before being sent to thehighspeed magnetic isolator (Agilent Technologies,HCPL-091J). This device also handles the two clocksignals of 2 and 32 MHz, needed for the PLD togenerate ADC control and to synchronize the serialup-link.

2.2. Field programmable gate array

All eight data streams coming from the acquisitionchannels are de-serialized by a SpartanTM IIE Xilinx ®

FPGA [4] using the same 2 and 32 MHz clocks toachieve word synchronization. Both clocks run con-tinuously and thus the acquisition process is also con-tinuous. Eight circular memory buffers of 512×16-bitwords receive the parallel data words, non-stop, over-lapping when full. These buffers generate an interruptto the DSP when half-full and full. For each interrup-tion, the DSP fetches the corresponding half-bufferthrough its external memory interface (EMIF) into itsinternal memory. This process occurs without inter-rupting the acquisition process, being fast enough totransfer data before next half is filled. Each bufferserves a set of four channels in order to present a 64-bit

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data word to the 64-bit EMIF bus in a single cycle, tomaximize transfer bandwidth.

The FPGA also includes a 64-bit time-counterwhich counts the number of digitized samples sincethe assertion of a reference signal (SYNC), issued bythe MASTER module. The circular memory buffersuse a 9-bit range of the time-counter to address thenext cells to be written. Whenever this 9-bit countturns 256 (half-full) or 0 (full) an interrupt is issuedto the DSP, as described before, and the time value isstored at the Block Time register. This value is readby the DSP and stored in its internal memory, in ablock address table which contains the end time ofthe acquisition of each data block. Also the 64-bittime-counter value is available at the current time

Fig. 3. FPGA block diagram.

register which can be accessed by the DSP throughthe EMIF interface. This allows the DSP to have thenumber of samples since SYNC (or the elapsed timein 500 ns units) or the last memory position whichhas been written. The time-counter can also generatea periodic interrupt to the DSP.

The process of data storage into external memory iscontrolled by the external trigger (TRG) signal. WhenTRG is asserted the time value is stored, trigger reg-ister value is locked and an interrupt to the DSP isgenerated. The DSP then reads the time value (alsounlocking the trigger logic) and uses it as a pointerto an address in the DSP internal memory data pool(via the block address table) thereby allowing to deter-mine the corresponding sample vector start. The DSP

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then starts sending this vector to the external SDRAMmemory for storage.Fig. 3 shows the functional dia-gram of the FPGA.

2.3. Timing block

The timing logic, depicted onFig. 4, receives trigger(TRG) and clock (CLK) signals from the front panelD9 connector. To avoid wiring all modules externally,an internal Synchronism bus is used to daisy-chainthese two signals and an additional (SYNC) to all mod-ules inside the PCI crate. Only one of the modules

Fig. 4. Timing block diagram.

is selected to be the MASTER in the Synchronismbus, using an onboard jumper. The MASTER boardactivates a buffer which outputs three lines: CLK andTRG from the D9 connector and the FPGA MasterSYNC line which is activated by software to indicatethe start time to all boards. All other boards (desig-nated as SLAVEs) have the same outputs deactivatedbut all of them (MASTER board included) receivethe three signals. This scheme prevents timing offseterrors, caused by unbalanced propagation paths. TheTRG and SYNC signals go directly to the FPGA to beused as described in the FPGA section. The CLK sig-

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nal, is input to a voltage controlled crystal oscillator(VCXO) based phase-locked loop (PLL) which gen-erates a low-jitter clock of 2 MHz. This PLL will pro-vide this frequency even if the D9 connector CLK sig-nal is not connected or is programmed to be ignored.From this clock, another PLL generates the 32 MHzserial acquisition clock. Both clocks are input to theFPGA to be used as previously described.

Yet another PLL generates the three frequenciesneeded by the DSP EMIFs, and CPU clock. Both PLLsare programmed through the FPGA. This allows gen-erating different frequencies for future upgrading.

2.4. Digital signal processor

The TMS320C6415TM is a “highest-performancefixed-point” DSP that handles up to 4800 million in-structions per second at a clock rate of 600 MHz[5].This DSP features application-specific hardware logic,on-chip memory and peripherals. It uses a two-levelcache-based architecture where the second level canbe configured as mapped memory or combinations ofcache (up to 256 KB) and mapped memory.

Among all on-chip peripherals, it is important tounderline its 32-bit/33 MHz, 3.3-V PCI Master–SlaveInterface, compliant with Specification 2.2, acting asa bridge between the PC and the module.

Secondly, the two glueless external memory in-terfaces (64-bit EMIFA and 16-bit EMIFB), both

Fig. 5. DSP and data paths.

of which capable of interfacing to synchronous(SDRAM, SBSRAM, ZBT SRAM, and FIFO) andasynchronous (SRAM and EPROM) memories andperipherals up to 1280 MB total addressable externalmemory space.

Also included is an enhanced direct-memory-access(EDMA) controller, providing 64 independent chan-nels for data transfer between all (external) peripher-als.

3. Data paths

The PCI-TR-256 control program running in thehost computer sets all operation variables in a prede-fined table structure stored in the DSP internal mem-ory. The code running on the DSP uses these param-eters to program all the data transfer peripherals in-volved.

Fig. 5 shows the data paths through these periph-erals in two data transfer scenarios (data paths A andB). For both paths the DSP sets an EDMA channelto transfer one 256× 64-bit block of data from theFPGA to the DSP internal memory whenever the cor-responding interrupt is issued. The periodically trans-ferred data blocks are stored in a circular buffer in theDSP’s internal memory.

For data path A, when the DSP receives an interruptfrom the FPGA which corresponds to the assertion of

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an external trigger, it fetches the occurrence time andstarts processing data. Algorithms such as filtering,data rate conversion or other data reduction techniquescan then be applied provided that the maximum cycletime response is not exceeded. A software interruptis then issued to trigger another EDMA transfer thatstores the processed data into SDRAM memory.

Data processed via path B is stored only in internalDSP memory and is transferred periodically to the hostcomputer for real-time monitoring.

During the data acquisition process all memoryspaces can be accessed by the host computer throughthe PCI interface and data can be fetched in real-timeusing adequate memory pointers.

4. Software

The module’s software includes a user-end applica-tion and the DSP programming.

User-end application will perform the necessarytasks for module’s operation, such as control ofall acquisition process, data path configuration, andSDRAM access. Data can be represented and savedeither in graphic or text file format.

The code includes Jungo® WinDriverTM generatedapplication programming interface (API)[6] to accesshardware, which is compatible with both Windows®

and Linux platforms.DSP software will control data transfers involved in

the acquisition process at DSP-level, as is the case ofFPGA interrupt handling and EDMA transfer manage-ment. Data can migrate directly between SDRAM andFPGA, but the DSP can also be programmed to pro-cess data in real-time (ex: an implemented low-passfilter).

The routines are developed with Code ComposerStudioTM [5] and can be uploaded to DSP directlyfrom the host computer (via PCI). Upload throughdedicated JTAG interface or from flash memory, con-nected to EMIFB, is also possible.

5. Conclusions

The implementation of advanced architectures tak-ing full advantage of combined features of complex

silicon devices and of the PCI bus can bring sig-nificant improvements to the functionalities of dataacquisition boards. Flexibility is equally improvedby the high degree of programmability of thesedevices.

FPGA devices play a crucial role in this new archi-tecture since they integrate a large number of dedicatedfunctions such as sophisticated triggering control, databuffering memory and interrupt management.

Galvanic isolation of the input channels also rep-resents an important contribution to the solution ofproblems that are placed by typical nuclear fusion ex-periments electromagnetic harsh environment.

Acknowledgements

This work, supported by the European Communi-ties and “Instituto Superior Técnico”, has been carriedout within the Contract of Association between EU-RATOM and IST. Financial support was also receivedfrom “Fundação para a Ciencia e Tecnologia” in theframe of the Contract of Associated Laboratory. Theviews and opinions expressed herein do not necessar-ily reflect those of the European Commission, IST andFCT.

References

[1] A. Combo, et al., An event-driven real-time-processing systemfor the next generation fusion experiments, Rev. Sci. Instrum.74 (3) (2003) 1815–1818.

[2] A. Combo, et al., A PCI transient recorder module for the JETmagnetic proton recoil neutron spectrometer, presented at 4thIAEA Technical Meeting on Control, Data Acquisition andRemote Participation for Fusion Research, San Diego, 2003,Fusion Eng. Des. 71 (2004) 151–157.

[3] J. Sousa, et al., A PCI time digitizer for the new JETtime-of-flight neutron spectrometer, presented at fourth IAEATechnical Meeting on Control, Data Acquisition and RemoteParticipation for Fusion Research, San Diego, 2003, FusionEng. Des. 71 (2004) 101–106.

[4] http://www.xilinx.com: Xilinx Programmable Logic Devices,FPGA & CPLD.

[5] http://www.ti.com: TMS320C6415: Fixed-Point Digital SignalProcessor, Texas Instruments, SPRS146G, March 2003.

[6] http://www.jungo.com: Jungo Device Driver DevelopmentTools, Home Gateway Software.