A Low-Voltage High-Drive Differential AmplifierFor ISDN Applications

L. Tomasini A. Gola' R. Castello*

Abstract

A CMOS differential buffer amplifier for ISDN applications is reported. The chip operates from a

single 5 V power supply and can deliver a 6 Vpp 80 kHz signal into a load of 100 ohm and/or 300 pFwith a THD of about 0 25 % The circuit main feature is its PSRR which remain practically constantfrom de to several hundred kHz around -75 dB for both positive and negative supplies with thecommon mode voltage generated ou chip. The step response at % for the same loading conditionsis less than 500 nsec for a step of +1.51' and less than 1 ßsec for a step of -f-GV. By using relativelysmall devices at the output the amplifier occupies an area of only 1720 square mils in a 2.5 ¡mi n-wellCMOS technology

1 IntroductionThe large majoiitv of analog blocks have traditionally been realized in bipolar technology which is par¬ticularly advantageous when designing circuits required to drive large capacitive and/or small resistiveloads. However, in recent years, CMOS has become the dominant technology for complex large digitalsystems. This has resulted in a continuous increase in the level of performance required to the peripheralanalog cells \t the same time, due to technological constraints, the supply voltage for such circuits hasbeen reduced from 10 V to 5 V leading to possible further reductions to 3.3 V in the near future.These characteristics are all present in the ISDN "U" interface system whose analog section is required todrive a full swing signal of approximately 100 kHz into a load of 100 ohms or less and up to few hundredspicofarad using a single 5 V supply with good linearity and maximum power efficiencyThis paper reports on the first truly differential circuit of this kind which achieves levels of performancecomparable and in some cases superior to the characteristics of single ended amplifiers intended for sim¬ilar applications [1,2,5]. In particular the circuit displays a supplv rejection that remains practically flatin the range from c to few hundred kHz.

2 Different Topologies for CMOS Buffer AmplifiersFully different ia! transe ondw tanc e op amps have been widely used for applications like switched capacitorfilters and A/D or D/A converters in mixed digital-analog systems [3]. Such amplifiers have a largerdynamic range and have greater immunity to the digital noise which is always present in such systemsHowever, virtually all the circuits interfacing with the outside world have been realized in single endedfashion [2,5] because the signals used in these circuits are generally referenced to ground Even circuitswhich drive a differential load have been designed with two single ended circuits both referenced to an

intermediate voltage [1] instead of a trulv differential circuit.The advantages of using a trulv differential amplifier are not immediately obvious without an extensivecircuit analysis nonetheless this solution offers some potential benefits in terms of noise immunity over

single ended amplifiers especially when a single supplv is used On the other hand the trulv diffèrenti¿xlsolution poses some new difficult design problems due to the interaction of the differential amplifiei andthe common mode feedback circuit This is a more severe problem than in transcondutance amplifierssince in buffer amplifiers the differential and common mode loads can be very different.In the design reported here the amplifier drives a purely differential load. We have adopted a truly

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differential topology since it is the most natural choice and because the circuit must have a good supplyrejection in the 100 kHz range. This choice has, however, required using particular care to insure circuitstability due to the large difference between the time constant of the differential load (i.e. 100 ohms inparallel with few hundred pF) and the time constant of the common mode load (i.e. a resistance close toan open circuit in parallel with few tens of pF). A description of the circuit solutions used is given next

3 Circuit ArchitectureA block diagram of the overall circuit architecture is shown in Fig. 1. It consists of a folded cascode inputstage with its common mode feedback circuit, shown in Fig. 2, driving a class a/b differential intermediatestage (Fig.3). This circuit provides a rail to rail signal at the gate of the output complementary devicessupplying the current drive for the load shown in Fig. 4 with its common mode feedback circuit.This solution allows the use of reasonably small output transistors (P-channel of 2800/3 and n-channelof 1000/3) when compared with other designs [2] while at the same time achieving a 6 Vpp output signalinto a differential load of less than 100 ohms.One disadvantage of the above solution is that the output transistors enter the linear region of operation,resulting in large distortion, while they provide the peak current to the load, flowever, an importantadvantage is the larger bandwidth,or larger gain at the frequency of the signal to be processed, due to thenon dominant pole located at higher frequency which is an inherent feature of the small output devices.When used in a closed loop feedback configuration this circuit can take advantage of the larger availablegain to greatly reduce the open loop non linearities. Both simulations and measurements show that thissolution is a viable alternative to the more area intensive solution used elsewhere [2] at least up to an

overall linearity requirement in the 60 dB range around lOOkhzBesides the differential amplifying path two common mode feedback circuits are necessary to establishthe proper common mode bias as shown in Fig. 1. Two distinct common mode circuits are necessarybecause the signal runs differentially from input to output in order to avoid using the noisv analog grownwithin the differential path.Small signal stability is assured by using nested miller compensation [4] in the differential path and two

simple miller compensation in the two common mode cirruits

4 Experimental ResultsThe buffer amplifier described in the previous section was realized using a 2.5/xm CMOS n-well technologyrequiring an active area of 1720 square mils A microphotograph of the chip prototype is shown in Fig.5. The amplifier achieves a c gain of more than 110 dB, when driving a differential load of 100 ohm, andan extrapolated gain band product of about 11 Mhz The circuit was compensated to give an adequatestability when used in an inverting configuration with a gain of 1.5 therefore the closed loop bandwidthis about 4.5 Mhz. All measured results reported below correspond to such a configuration. The amplifierresponse to a small and large signal step is shown in Fig. 6. The settling time to 1 % is less than 500nsec and l/jser respectively. It is important to point out that the settling time is basically unchangedfor any combination of 100 ohm and /or 300 pf differential load, demonstrating the very stable designThe slew rate is about l^V/fisec. The linearity of the circuit is depicted in Fig. 7 where the second andthird harmonics are plotted versus output signal amplitude for a 80 kHz sinusoidal input. A distortionof about 0.25 % is achieved for a 6 V pp signal. The PSRR for both positive and negative supply versus

frequency is shown in Fig. 8 in the range from c to 1 Mhz. These measurements were taken with thecommon mode signal generated on chip. The remarkable flatness of these curves well beyond 100 kHz isone of the main features of this circuit and demonstrates the advantages of the fully differential approachwhen high immunity to the supply noise is required especially at high frequency. A summary of theamplifier performance is shown in Table I.

5 ConclusionsThe first truly differential CMOS buffer amplifier has been described. The circuit achieves excellentpower supply rejection, especially at high frequency, and good linearity while using <omparativelv smallsize output devices. The circuit operates from a single 5 V supply and is intended for applications which

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interface differentially with the load. Its ability to operate in noisy environments makes it particularlysuitable for applications where digital system and analog peripheral cells share the same substrate.An improved version of the circuit is presently under developments with shorter (2.5 ^m) channel lengthsand using a modified common mode circuitry. Simulations predict a 40 to 50 % improvement in linearitywith the same power consumption and a 25 % reduction in the overall area.

6 AcknowledgmentThe authors wish to thank S.Mariam* and S.Sala for the careful layout .

Reference

[1] D. Sallaerts, D. H. Rabaey, R. F. Dierckx, J. Sevenhans, D. R. Haspeslagh and B. J. Ceulaer, "ASingle-Chip U-Interface Transceiver for ISDN", IEEE J. Solid-State Circuits, vol. SC-22, pp. 1011-1021, December 1987.

[2] J. A. Fisher and R. Koch, "A Highly Linear CMOS Buffer Amplifier" IEEE J. Solid-State Circuits,vol. SC-22, pp. 330-334, June 1987.

[3] H. Ohara, H. X. Ngo, M. J. Armstrong, C. F. Rahim and P. R. Gray, "A CMOS ProgrammableSelf-Calibrating 13-bit Eight-Channel Data Acquisition Pheripheral", IEEE J. Solid-State Circuits,vol. SC-22, pp. 930-938, December 1987.

[4] J. H. Huijsing and D. Linebarger "Low-Voltage Operational Amplifier with Rail-to-Rail Input andOutput Ranges" IEEE J. Solid-State Circuits, vol. SC-20, pp. 1144-1150 December 1985.

[5] J. A. Fisher "A High-Performance CMOS Power Amplifier" IEEE J. Solid-State Circuits, vol. SC-20,pp. 1200-1205,December 1985

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Fig. 1 Block diagram of the circuit

1, Fig. 2 Input stage schematicCe,*

Fig. 3 Intermediate stage schematic

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Fig. 4 Output stage schematic

U(32,58) Fig. 5 Chip microphotography

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12 3 4 3 6 7 8Tine ( sec > *i6E-6.

Fig. 6 Ampi, step response

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Fig. 7 Measured distortion *\

TABLE 1PERFORMANCE SUMMARY(Power Supply -5V)

1KHZ 1BKHZ leeKHZ 1MHZ

PARAMETERS

Gain Band Product

Open Loop Geln

Power DissipationVoffset x

Output swlnj, 1 I THO(Rl> let Oh«, CL. 366 pf)Heraonlc Distorsion Vout=6Vpp(ft. <. KHz, RL-16« Oh.,C1» 316 pF)HD I

NO3

Slew rite

CARR 1 KHzIM KHz

PSÍR ? 1 KHzne KHz

PSR« - 1 KHzlee KHz

MEASURED RESULTS

11 MHz> l?e dB

16 aU

3 S IV

6 4 Vpp

55 dB56 dB

1« u / mee

lte dBas da

ae dB7« dB

- 74 dB- 7« dB

Fig. 8 PSRR versus frequencyESSCIRC'88 240