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9656 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 11, NOVEMBER 2018

A Miniature 300-MHz Resonant DC–DC ConverterWith GaN and CMOS Integrated in IPD Technology

Ming-Jei Liu and Shawn S. H. Hsu , Member, IEEE

Abstract—A 300-MHz class-E dc–dc converter using the reso-nant gate driving technique is proposed. The gate driver utilizes theharmonic shaping network and RC feedback to enhance the outputswing voltage, and the class-E power converter can minimize thevoltage–current overlap to improve efficiency. With the 0.25-µmGaN high-electron-mobility transistor and 0.18-µm CMOS for theswitching power device and the gate driver, respectively, a completedc–dc converter operating at 300 MHz is demonstrated includingall the passive components microfabricated by integrated passivedevice (IPD) technology on the high-resistivity silicon substrate.The overall chip area is smaller than 1 cm × 1 cm and the volumeis only 0.115 cm3. The measured results show a maximum outputpower of 4.16 W with 47.3% efficiency. An excellent power densityof 36.2 W/cm3 can be achieved. The flip-chip assembled converteron the IPD substrate demonstrates the potential of heterogeneousintegration for high-frequency power conversion applications.

Index Terms—Class E, CMOS, GaN high-electron-mobilitytransistor (HEMT), high frequency, power converter, powersupply-in-package (PSiP), resonant power converter.

I. INTRODUCTION

IN RECENT years, the research and development of powerconverters at high switching frequencies [1]–[19] has at-

tracted significant attention from both academia and industry.Power converters with a small size and high power densityare favorable for modern electronic products, especially for theportable applications [1], [5], [13], [15]. Also, the miniaturizedpower converter is critical to the next-generation technologysuch as insect-sized microrobots that can provide surveillanceand reconnaissance in hostile or other hard-to-reach environ-ments [2]. In many cases, the size and weight of a power con-verter are determined by the passive components, which are theessential parts of the system. To achieve a converter with a com-pact size, smaller passive components are favorable, which usu-ally means higher operating frequencies. In addition to the sizereduction, power converters with a high switching frequencyare required for the advanced modulation schemes necessaryto achieve high power-added-efficiency such as envelope track-ing and envelope elimination and restoration (EER) transmitter

Manuscript received October 16, 2017; accepted December 22, 2017. Dateof publication January 1, 2018; date of current version August 7, 2018. Rec-ommended for publication by Associate Editor Jose A. Cobos. (Correspondingauthor: Shawn S. H. Hsu.)

The authors are with the Department of Electrical Engineering, NationalTsing Hua University, Hsinchu 30013, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2017.2788946

systems [1], [13]. Different approaches and techniques havebeen proposed for high switching frequency power convert-ers with reduced sizes. For example, a copper air-core micro-inductor with a 30-μm thick electroplated copper [2] and thepackaging inductors including bond wires and lead frames wereutilized [7] to enhance circuit performance by the inductor with ahigh quality factor. The idea of a self-oscillating gate driver wasreported to achieve soft gating with improved efficiency com-pared with hard switching [3], [4], [9], and the resonant gatedriver can reduce the gate losses at high switching frequencies[11], [17]–[19]. Also, some previous publications emphasizedusing the standard CMOS process for fully integrated powerconverters [8], [17], whereas some reported works employedthe GaAs Pseudomorphic High-Electron -Mobility Transistor(pHEMT) [15], [16] or GaN HEMT technology [9] to take ad-vantage of low on-resistance and high switching speed of thetransistors for high-efficiency power conversion. The conceptof system-in-package (SiP) was also incorporated to achieve acompact circuit size by stacking the chips [6], [16].

There are some obstacles to be overcome in order to achievehigh-frequency operation while maintaining a good efficiencyin power conversion systems, including increased switchingloss and driver power consumption, limitation of the switchingfrequency by the nature of power devices, realization of high-Qpassive components, and parasitic effects due to package andcircuit layout. Many efforts have been made to reduce the powerconsumption of switching and the gate driver with an increasedoperating speed of power converters. One approach to minimizethe switching loss is referred to as “zero-voltage switching”(ZVS) [3], [4], [10]–[14], [20], which can be attained by class-Eor some other resonant converter topologies. Compared withhard switching power converters, the ZVS design can mitigatethe overlap of voltage and current waveforms in the powerdevice to minimize the switching loss. Another challenge is theconsiderable power consumption of the driving circuit due tothe large input capacitance of power devices at high-frequencyswitching. Resonant gate drive techniques have been proposedto reduce the power consumption of the driving circuits[17]–[19], [21]–[24]. The basic concept of using the interactionof a capacitor with a series-connected inductor and a switchingelement for resonant gate drive was illustrated in [22]. Theresonant gate driver allows energy recovery using the inductivecomponents, and an enhanced efficiency is expected [24]. Acombined low-side and high-side resonant-type gate driver withpartially shared inductor was proposed in [17]. The resonant gatedriver was also employed in the low-side switch for a 100-MHz

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LIU AND HSU: MINIATURE 300-MHZ RESONANT DC–DC CONVERTER WITH GaN AND CMOS INTEGRATED IN IPD TECHNOLOGY 9657

GaAs dc–dc converter to reduce the loss under light load con-ditions, and a 5% efficiency improvement can be achieved [18].A 200-MHz fully integrated dc–dc converter with a resonantgate driver using an on-chip air-core inductor was realized in0.25-μm BiCMOS technology [19]. A multistage gate driverwas proposed in [23], which employed a hard-switched inverteras the first stage, and the resonant second-harmonic class Einverter was used as the following stage to drive the powerdevice.

The switching frequency is also limited by the power devices,where tradeoffs exist among the on-resistance, breakdown volt-age, and switching speed. Power devices based on relatively newwide bandgap semiconductors such as SiC and GaN have beenproposed in recent years to take advantage of superior materialproperties [25]–[31]. The performance of wide bandgap powerdevices was improved by different approaches such as the hybriddrain structure [25], [27], ohmic/Schottky contact engineering[26], [30], and square gate geometry [28]. The advantages ofusing SiC-based devices for high-power and high-frequency ap-plications were discussed [31]. In addition, the loss of inductivecomponents becomes a serious issue as the operating frequencyincreases due to the eddy current and hysteresis loss [2]. Dif-ferent approaches were reported to improve the high-frequencyperformance of magnetic materials for inductors and transform-ers [32]–[40]. Multiple layers of magnetic materials such asCo–Zr–O [32], [40], permalloy (Ni80Fe20) [34], and FeCoB[39] were employed to increase the flux density. The distributedair-gap structure was proposed using low-temperature cofiredceramic technology to achieve a very compact inductor [38].The loss characteristics of RF magnetic materials for powerconversion applications were investigated in details [33], andthe challenges and considerations of integrating magnetics foron-chip power supply were discussed and reviewed [35], [37].

One effective solution for achieving a compact powerconverter with high operating frequencies is to increase theintegration level of the system, which means using more micro-fabricated elements with an advanced semiconductor process toreplace the discrete components for system integration and cir-cuit size reduction. However, most of the high-frequency powerconverters reported to date are still realized at the board levelusing discrete active and passive components with relativelylarge sizes [3]–[5], [10]–[14]. In this work, a class-E dc–dc con-verter with a resonant gate driver is proposed. With integratedpassive devices (IPDs) technology on a high-resistivity siliconsubstrate, a complete power converter is heterogeneously flip-chip integrated, including the resonant gate driver in standard0.18-μm CMOS, the power device in 0.25-μm GaN HEMTtechnology, and the planar inductors and metal–insulator–metal(MIM) capacitors microfabricated directly on the IPD substrate,as illustrated in Fig. 1. The overall chip area of the converter issmaller than 1 cm × 1 cm with a volume of only ∼0.1157 cm3.

The focus of this work is to demonstrate a high-frequencypower converter with the novel SiP technology together withCMOS and GaN devices. The goal is to achieve high powerdensity with more design and integration flexibility. We presentthe results in a relatively wide input voltage range from 4 to 12 V,which could potentially be used for applications such as lithiumbattery of about 4 V [2], and the boost converters of a 12-V

Fig. 1. Conceptual plot of the proposed class-E power converter using bothGaN and CMOS devices/circuits integrated in the IPD technology.

car battery input and a 20-V output [9]. Also, the convertercan supply LEDs used for LCD backlight [3]. Moreover, theproposed power converter can be possibly employed to drive thelow-power dc motor [41]. This paper is organized as follows.Section II introduces the principle of class-E circuit topologyand analysis of the ZVS class-E power converter. Section IIIpresents the detailed design of the proposed dc–dc converterwith different technologies employed. Section IV presents theexperimental results and discussion, and Section V concludesthis work.

II. CLASS-E CIRCUIT TOPOLOGY

Both the hard switching and resonant topologies are theoreti-cally capable of achieving 100% efficiency for power converters.Compared with the hard switching design, the main advantageof resonant converters is the reduced switching loss for high-frequency operation by achieving ZVS or “zero-current switch-ing (ZCS)” conditions [42]. In addition, the resonant topologyprovides an effective approach to resolve the issues caused bythe parasitics for high-frequency power conversion. The par-asitic effects such as the output capacitance of the switchingtransistor and the stray inductances and parasitic capacitancesintroduced from the circuit layout and package can degrade thecircuit performance, which becomes more severe at high fre-quencies in the conventional hard switching power converters.In contrast, the resonant-type designs can absorb the parasiticsas a part of the circuit for achieving the ZVS/ZCS condition[3], [4], [10]–[14]. In this study, we focus on the resonant-typeclass-E power converter operating in the UHF range.

A. Operating Principle of Class-E Topology

Operation of the power converter at high frequencies intro-duces a significant switching loss, which makes the circuit topol-ogy critical for improving the conversion efficiency. One of theZVS techniques employed is the class-E topology, first intro-duced by Sokal and Sokal in 1975 [43], [44] for RF power am-plifiers. Fig. 2(a) shows the circuit topology of a typical class-Eamplifier, where the transistor S1 acts as a switch, L1 functionsas an RF choke, and C2 and part of L2 form a series resonator(open circuit at the harmonics) to transfer power to the load atthe fundamental frequency. Part of L2 and the shunt capacitorC1 function together to achieve the ZVS condition of the class-Epower amplifier [45]. Although different configurations can alsoachieve the ZVS condition for power converters and switchingamplifiers [20], [46]–[48], the class-E topology possesses somedistinct advantages owing to its load network design. First, the


Fig. 2. (a) Class-E circuit topology, and (b) current and voltage waveforms.

transient response of the load network (C1 , L2 , C2 , and RL ; L1is sufficiently large acting as a constant current source) allows adelay of voltage increase at switch turn OFF, which makes surethat high voltage does not exist across the switch as the currentflowing through it is nonzero [43]. In addition, the class-E topol-ogy can reach an approximate zero voltage slope (dv/dt ≈ 0)at switch ON with a properly designed load network, which per-mits a time interval during turn ON to still meet the conditionof v = 0. The conditions of both zero voltage and zero voltageslopes together also imply that the switch current starts fromzero gradually. As a result, the moderate turn ON of switch caneffectively reduce the power dissipation during transistor turnON. This also allows slightly mistuning of the circuit without se-vere loss of efficiency [43]. More detailed analysis of the class-Etopology is described as follows based on the assumptions ofideal switching characteristics [47]. Also, the choke inductor islarge enough so that the input current is a pure dc current, andthe loaded quality factor of the resonant tank is very high toensure pure sinusoidal current.

Assume the current of load iR is

iR (ωt) = IR sin (ωt + φ) (1)

where IR is the amplitude and φ is the initial phase. The currentsin the ideal switching transistor S1 and the shunt capacitor C1for each half-cycle (assuming 50% duty cycle) can be expressedas (2) and (3), respectively. Assume that S1 is ON during the firsthalf-cycle (iC 1 = 0) and OFF in the second half-cycle (iS1 = 0)

iS1(ωt) = IL1 − IR sin (ωt + φ) 0 < ωt ≤ π (2)

iC 1(ωt) = IL1 − IR sin (ωt + φ) π < ωt ≤ 2π (3)

where IL1 = IIN is the total current at the input. As a result, thevoltage vS1 across C1 can be obtained from

vS1(ωt) =1

ωC1

∫ 2π

π

iC 1(ωt)d(ωt)

=

⎧⎪⎨⎪⎩

0 0 < ωt ≤ π1ωt [IL (ωt − π) + IR (cos (ωt + φ) π < ωt ≤ 2π

− cos (π + φ)]

.

(4)

To achieve the goals of ZVS and zero derivative switching(ZDS), the conditions VSI(ωt)|ωt=2π = 0 and ∂vS I (ωt)

∂ (ωt) |ωt=2π =0 must both be satisfied. These two requirements at the end ofthe OFF state indicate that the switch current at the beginningof the ON state will be zero, and also the current only increases

gradually from zero. This feature is desirable to reduce thepower dissipation during the turn ON transient [43]. Based onthese constrains, we can obtain the following equations:

IR = IL1π

cos (π + φ) − cos (φ)(5)

iS1(ωt) = IL1

[1 − π sin (ωt + φ)

cos (π + φ) − cos φ

]0 < ωt ≤ π

(6)

iC 1(ωt) = IL1

[1 − π sin (ωt + φ)

cos (π + φ) − cos φ

]π < ωt ≤ 2π

(7)

where φ = tan−1(−2π ). The dependence of input voltage Vdc =

VIN on the voltage across S1 can be obtained by

VIN =12π

∫ 2π

0vS1(ωt)d(ωt). (8)

As a result, the voltage and current of the switching transistorS1 in each half-cycle can be obtained as

iS1(ωt)=IIN

[π

2sin (ωt) − cos (ωt) + 1

]0 < ωt ≤ π (9)

vS1(ωt) =

VIN

{π

[ωt − 3

2π − π

2cos (ωt) − sin (ωt)

]}π < ωt ≤ 2π.

(10)

The amplitude of voltage across the load can be calculatedfrom vS1 (ωt) as

VL = −4 sin(

π2 + φ

)π

. (11)

Also, the inductor L2 can be divided into two serially con-nected elements of LA and LB , where LA and C2 can be tunedto resonate at the fundamental frequency, while the values of LB

and C1 for achieving ZVS and ZDS conditions can be obtainedby the derived IR , VIN , and the voltage across RL as

C1 =8

π(π2 + 4)ωRL(12)

LB =π(π2 − 4)

16· RL

ω. (13)

Fig. 2(b) plots the corresponding voltage and current wave-forms based on (9) and (10), which shows nonoverlapping char-acteristics of current and voltage with no dc power consumption.


Fig. 3. Class-E dc–dc power converter including the inverter stage and therectifier stage.

The peak values of iS1 is 2.86× of IIN , and that of vS1 is 3.56×of VIN . The output voltage across the load is also shown inthe figure. The analysis indicates that the class-E topology canachieve the ZVS/ZDS condition with the ideal switching tran-sistor and passive components. Based on the similar concept ofcreating nonoverlapping current and voltage across the switch,this topology is suitable for power converts to achieve highefficiency at high frequencies.

B. Class-E DC–DC Converter

Fig. 3 shows the design of a dc–dc power converter usingclass-E topology, which can be analyzed in two stages, theinverter stage and the rectifier stage. The inverter stage iscomposed of L1 , S1 , C1 , LT , and CT , and the rectifier stageincludes D1 with COUT . The inverter stage of the class-Epower converter is based on the aforementioned class-E RFpower amplifier. The main difference is that the series capacitorC2 is replaced by the shunt capacitor CT , which allows the dccurrent of the power converter to pass while still resonating atthe fundamental frequency. This design can also be consideredas combining the input tank of the rectifier stage with theoutput resonant tank of the inverter stage [10], which cansimplify the circuit and effectively reduce the size. In practicaldesign, the initial value of LT is chosen to be similar to L2 ,and then optimized together with CT for the ZVS conditionof a maximum efficiency. Note that the current and waveformequations for the proposed class-E dc–dc converter are similarto those of the class-E amplifier at the reference plane beforethe rectifier stage (see the red dashed line in Fig. 3). The onlydifference is the additional dc level due to the modified shuntcapacitor (C2 becomes CT ). Detailed analysis about the impactof the rectifier stage on the output waveform can be found inthe previous publication [14] for a high-frequency resonantboost converter with a similar topology to the proposed design.The analysis was conducted by replacing the inverter stagewith a sinusoidal voltage source with a dc offset. It should bementioned that if the diode and capacitor are ideal in the rectifierstage, the efficiency will not be degraded, which can be verifiedby simulation. In practice, the efficiency will drop mainly dueto the loss introduced by the nonideal characteristics of thediode such as parasitic resistance and nonzero turn ON voltage.

The transfer function of the parallel resonant converter wasanalyzed [42]. Assume that both the switching network andrectifier stage are ideal, the transfer function of the parallelresonant tank LT − CT and the voltage transfer ratio from VINto output voltage VL can be expressed as follows (Re is the

effective resistive load looking into the rectifier stage, f0 isthe resonant frequency of LT − CT , and fS is the operatingfrequency)

H(s) =Z0(s)sLT

where Z0(s) = sLT ‖ 1sCT

‖Re (14)

VL

VIN=

8π2

1√(1 − F 2)2 +

(FQe

)2(15)

where F = fS /f0 , f0 = ω02π = 1

2π√

LT CT, and Qe = R0/Re

with R0 = ω0LT = 1/ω0CT .At resonance, the conversion ratio can be obtained as RL/R0 .

As mentioned, one advantage of the resonant-type convertershould be emphasized is that parasitic elements in the circuitcould be utilized as a part of the circuit to prevent performancedegradation at high switching frequencies if properly designed.With the required LC components for resonance in the class-Epower converter, the parasitics can be codesigned into the cir-cuit to achieve the desired frequency response with suppressedharmonics and improved efficiency. On the other hand, onedisadvantage of the resonant-type converter is that the ZVScondition can only be maintained at the resonant frequency. Asindicated in (12) and (13), the values of passive devices are afunction of the operating frequency, which should be designedproperly to achieve the ZVS condition. The efficiency degradeswhen the operating frequency deviates from f0 due to the in-creased switching loss. In a practical design, C1 is obtained byincorporating the effective output capacitance of S1 , and theoptimization of CT is combined with the parasitic capacitanceslooking into the rectifier stage. The design of LT and CT shouldbe such that the higher order harmonics are suppressed and theZVS condition is achieved. The interconnects in the IPD layoutare also considered by rigorous EM simulation to be codesignedwith the IPD inductors of L1 and LT . More details will be dis-cussed together with the IPD layout in Section III.

III. PROPOSED CLASS-E DC–DC POWER CONVERTER

Fig. 4 shows the complete circuit topology of the proposedclass-E dc–dc power converter, including the resonant gatedriver in 0.18-μm CMOS, the power transistor and diode in0.25-μm GaN HEMT, and the passive components in IPD tech-nology on the high-resistivity silicon substrate.

A. Resonant Gate Driver

The design of a gate driver capable of high-frequency opera-tion while maintaining a high efficiency is critical to achieving ahigh-performance power converter. The conventional gate driveris usually realized by cascading inverters to provide sufficientdriving capability. However, the power consumption increasessignificantly with the operating frequency. Also, a large supplyvoltage is often needed to achieve a high output swing. Differ-ing from the conventional inverter-type gate drivers, the resonantgate drivers use the LC components to assist charging and dis-charging the large input parasitic capacitance of power devicesmore efficiently. The LC resonance techniques were reported to


Fig. 4. Proposed 300-MHz dc–dc power converter with the resonant gate driver in standard 0.18-μm CMOS, and the class-E inverter stage with 0.25-μm GaNHEMT as the switch transistor. The whole circuit is integrated by the IPD technology in a high resistivity silicon substrate including all the passive components.

reduce the driving loss [17]–[19], [21]–[24]. A high-frequencyresonant-type gate driver was demonstrated at 200 MHz [19].However, most of the published results were designed and op-erated at relatively low frequencies (below 10 MHz).

In this work, a resonant gate driver is proposed based onthe topology of class E/F switching-mode power amplifiers andclass Φ2 inverters [4], [48]–[51], where the series-connectedLS and CS resonate at around the second harmonic frequency(short circuited to ground), and together with LD to enhance thefundamental and third harmonic signals. Note that the dc blockCB is relatively large and has negligible impact at the frequencyof interest. Similar to the principle in other resonant gate drivers[10], [24], the inductive energy-storage elements help to chargeand discharge the input capacitance CIN of the switching tran-sistor to improve the efficiency. Also, LD serves as an inductiveload similar to a typical RF amplifier [52], which allows usinga low supply voltage to achieve a large output swing. More-over, the low-order harmonic shaping network in the class Φ2topology results in a trapezoidal waveform (see Fig. 7) [10],which is preferred for driving the class-E configuration [44].The proposed resonant gate driver is composed of a three-stagepredriver using CMOS inverters, and a main driving stage con-sisting of a self-biased RC feedback cascode configuration. Itshould be emphasized that GaN technology is also a good choicefor realizing the gate driver, which can be integrated with theswitching transistor directly to minimize the parasitic effects athigh frequencies with an excellent driving capability [9]. How-ever, the cost of GaN technology is a major concern. Also, theCMOS technology provides more freedom to combine the con-trol circuits directly with the gate driver. As shown in Fig. 5(a),the conventional cascode topology is often adopted to preventdevice breakdown [53]. With VDD distributed to both transistors(Q1 and Q2), a large output swing can be achieved even with thesubmicron CMOS devices. However, the fixed gate voltage VG2of Q2 can still result in a considerable drain–gate voltage VDG2 ,which stresses the transistor under large output swing and canraise the breakdown and reliability issues. With the proposedfeedback path formed by RSB and CSB , VG2 can vary with theoutput voltage, which effectively reduces the drain–gate volt-age crossing on Q2 to prevent transistor breakdown. Fig. 5(b)compares the simulated voltages of the two designs at differentnodes. As can be seen, the drain–gate voltage of Q2 is reduced

Fig. 5. (a) Comparison of the conventional and proposed RC-feedback self-biased cascode configuration, and (b) simulated characteristics of the circuits.

Fig. 6. (a) Harmonic shaping network at the output of gate driver, and(b) simulated impedance of the harmonic shaping network.

effectively with the RC feedback. Note that the 0.18-μm CMOStransistors used for the last stage (cascode with RC feedback)are the I/O devices in the standard process, and the operatingvoltage should not exceed 3.3 V as suggested by the foundry(common-source configuration). As shown in this figure, thevoltage swing VD2 across the cascode transistors exceeds 4 V,while the most critical drain–gate voltage of Q2 is kept below2 V during operation. The circuit can be operated with suffi-cient reliability without the concern of device breakdown anddegradation.

Fig. 6(a) shows the equivalent circuit of a multiresonant tankin the gate driver for harmonic shaping, formed by LD of 8.5 nH,LS of 5.5 nH, and CS of 11 pF at 300 MHz, and the effectiveinput capacitance CIN of the power device. Fig. 6(b) shows thesimulated result of input impedance ZIN of the tank under two


Fig. 7. Simulated output waveform of the proposed gate driver.

different loading conditions of 18 and 24 pF, corresponding tothe actual range of CIN in our design as can be estimated fromthe transistor model. As can be seen, very high impedance can beobtained at the fundamental tone of 300 MHz with a peak at thethird harmonic around 900 MHz. With the techniques of induc-tive peaking and a multiresonant harmonic shaping network, alarge trapezoidal output signal swing and a reduced gate drivingloss can be obtained without the complicated control mecha-nism, as shown in Fig. 7. The total power consumption of theproposed resonant gate driver is 196 mW with VDD of 2.2 V,which can provide an output voltage swing up to 4.2 V. Simu-lation was performed to compare the proposed design with theconventional inverter-type driver. Under the same loading con-dition of GaN switch and operating frequency of 300 MHz, theproposed design can achieve 4.2 V swing with a power con-sumption of 150 mW, while the inverter chain driver consumes186 mW with an output swing of 3.3 V. The results indicate thatthe resonant-type gate driver exhibits a higher power efficiencyas expected. In addition, assume that the gate capacitance ofthe switching device is 24 pF, the power needed to drive thecapacitive load with a 4.2-V swing can be estimated by Pdiss =C · V 2 · f , which is ∼127 mW in an ideal case. Consideringthe nonideal effects in both the active and passive componentsin the circuit, the efficiency of the driving stage is acceptable.

As mentioned, the output swing in the typical inverter gatedriver could be limited by the breakdown voltage with a standardsubmicron CMOS process, which can be solved by the proposedtopology. It is also possible to use a high-voltage CMOS processto realize the driver for improved output swing, but the cost,operating speed, and integration level with other control circuitsare the main issues. One disadvantage in practical design is thatthe proposed resonant gate driver requires a larger area becauseof the inductive components. However, the IPD process offers arelatively low-cost design with high Q inductor and more designflexibility. Also, the resonant-type design of the output stage canabsorb the parasitics as a part of the circuit, which is suitable forUHF operation. The proposed topology is a good alternative forthe conventional inverter driver, especially at high frequencies.It should be mentioned that the CMOS chip area is expected tobe similar for both the proposed resonant gate driver and thetypical inverter-type gate driver.

B. Power Transistors and Diodes

Devices capable of high-speed and low-loss operation are es-sential for highly efficient power converters with compact size.With superior material properties, the GaN-based HEMT is apromising candidate to satisfy such requirements owing to thelarge bandgap and high electron saturation velocity of the mate-rial, and also a high carrier density in the two-dimensional (2-D)electron gas channel in the transistor. Using the class-E topologyfor the converter, the maximum voltage across and the peak cur-rent flowing through the switch could be as large as 3.56 × VINand 2.86 × IIN respectively, as illustrated in Fig. 2(b) [47]. TheGaN power devices are expected to be robust enough to sustainthe harsh operating condition. In addition, a very high switchingspeed can be achieved while maintaining low ON-resistance andhigh breakdown voltage.

In this work, the 0.25-μm GaN HEMT technology on theSiC substrate provided by WIN Semiconductor is employed torealize both the switching transistor S1 and the Schottky diodeD1 (see Fig. 4). We select the transistors with various layoutsfrom the device library to meet the design specifications. Notethat the internal transistor structure cannot be changed, and themain design parameters are the finger number and the widthof each finger. The gate length employed is 0.25 μm for high-speed operation, which is the smallest value provided by thistechnology. The device is a depletion mode (normally ON) witha threshold voltage VTH of −3 V, and the maximum drain–source voltage is around 120 V before transistor breakdown.The turn-ON voltage for the Schottky gate is 1.1 V. Note that thedevice is biased with a negative voltage VBIAS at around VTHof −3 V via the bias resistor RB and dc block CB (see Fig. 4),and the proposed gate driver is operated under a supply voltageVDD of 2.2 V achieving a voltage swing of about 4.2 V, whichis sufficient for switching the GaN HEMT.

Based on the estimated current density, the total width Wtotis determined by considering Ron , power consumption of gatedriver, output power level, and GaN chip area at the targetedswitching speed. Different combinations of Wfin (width of eachfinger) and n (finger number) were evaluated by simulation.Under a fixed Wtot for the multifinger layout, a tradeoff existsbetween Wfin (width of each finger) and n (finger number). Withincreased n and decreased Wfin , the parasitic resistance intro-duced from gate can be reduced effectively. However, the para-sitic capacitance increases with n mainly due to coupling amongthe fingers. Also, the unevenly distributed current in each fingermay become an issue when n is too large for a single transistor.The power level increases with the transistor size, but the driv-ing capability of the gate driver and the parasitic capacitances ofthe power device will ultimately limit the switching speed of thepower converter. Based on the above-mentioned considerations,Wfin is chosen as 125 μm and n = 20 of a transistor in our finaldesign. Two of the transistors are connected monolithically ona single GaN chip by the provided metal layer, and then threeunits are combined in the IPD substrate. The effective Wtot is15 mm to achieve the desired RON with a sufficient current level.Fig. 8(a) shows the measured I–V characteristics of the devicewith 125 μm × 20 fingers. The peak current density is about


Fig. 8. I–V characteristics of (a) GaN HEMT (125 μm × 20 fingers), (b) cutofffrequency fT as a function of transistor size, and (c) GaN Schottky diode(width = 5000 μm).

250 mA/mm, which is dropped by about 50% as compared withthe foundry provided model. The discrepancy between the mea-sured and modeled I–V characteristics could be attributed tothe thermal effect, which is difficult to be predicted by the pro-vided model due to the different ambient thermal conductivities(whole wafer for modeling vs. diced devices in this case) whenextracting thermal parameters in the equivalent circuit model.Based on the results in Fig. 8(a), the effective RON is estimatedto be about 0.5 Ω based on measurement with the parasitic re-sistance of measuring probes calibrated, which is larger thanthat obtained by the model of about 0.3 Ω. Fig. 8(b) shows thesimulated fT (cutoff frequency) as a function of the transistorsize based on simulation. Note that the effective transistor sizeused in our design is 120 finger by 125 μm of each finger. As thesize of power transistor increases, the parasitic capacitances ofthe transistor increase, which will eventually limit the switchingspeed of the transistor.

Another important circuit element to achieving a high switch-ing frequency is the diode, which should have a short reverserecovery time. For the fully integrated converter using the IPDtechnology, a Schottky barrier diode (SBD) is also designedusing the same GaN HEMT platform for the power transistor.Differing from an MOS transistor with an isolated gate by theoxide layer, the HEMT has an inherent Schottky gate formedby the gate metal and GaN. An intuitive way to realize a diodebased on the transistor structure is to connect the drain andsource terminals of GaN HEMT devices as the cathode, whileusing the gate as the anode to realize an SBD. The GaN diodehas a large total finger width of 10 mm (two devices connectedin parallel by IPD) to ensure a low RON for achieving a highoverall efficiency. Fig. 8(c) shows the I–V characteristics ofthe GaN diode (width = 5000 μm). The relatively high turn-ON

voltage VON of about 1.1 V is due to the large bandgap of GaNmaterial. Different approaches were reported to reduce VON ofGaN SBDs [54]–[56]. However, these are not available in the

Fig. 9. Cross-sectional view of the integrated passive device (IPD) process.

technology used in this study. If using the Si Schottky diodewith a typical VON of ∼0.4 V to replace the GaN diodes inthe proposed power converter, the efficiency can be improvedby about 3% when only considering the extra power loss due toVON . However, the operating speed of Si Schottky diode is muchslower if similar ON-resistance and breakdown voltage need tobe achieved, which makes it difficult to use the Si Schottky diodein the UHF range. Similarly, if using the CMOS transistor toreplace GaN HEMT for the switching device, based on the fun-damental material properties [57], the size will be significantlylarger than its GaN counterpart, resulting in a limitation of theoperating speed.

C. IPD Passive Components

The idea of power supply-in-package (PSiP) for a compactsystem with a high operating speed has attracted significant at-tention in recent years. One critical issue is how to miniaturizethe passive devices in the power conversion circuits, especiallythe relatively large inductive components. Various approacheswere proposed to achieve a small area/volume of power con-verters [6], [7], [58]. In this paper, we propose using the IPDtechnology to implement the reactive passive components forboth gate driver and converter to achieve a compact size with aswitching speed up to 300 MHz. As shown in Fig. 9 of the crosssection, the IPD process adopted here, which is typically usedfor RF circuits, is fabricated on a high-resistivity silicon sub-strate and the benzocyclobutene (BCB) materials are employedfor the dielectric layers (εr = 2.65) [59], [60]. The resistivityof silicon substrate is over 3 kΩ·cm with a thickness of 650 μm.The BCB layers have a low loss tangent ranging from 0.0008 to0.002, and the total thickness of BCB 1 and BCB 2 is 13 μm.This technology provides three metallic Cu layers as denotedby metal 1, metal 2, and metal 3 with the thicknesses of 1, 0.65,and 10 μm, respectively. The top metal layer (M3) is mainlyfor interconnects and planar spiral inductors, which allows toreduce signal loss and obtain high Q inductors owing to theincreased metal thickness. A NiCr layer with a thickness of0.05 μm is deposited for resistors. The IPD process also pro-vides a thin-film high dielectric constant layer (εr = 6.7 andtan δ = 0.0002) with a thickness of 0.2 μm between M1 andM2 to form MIM capacitors with a 300 pF/mm2 capacitancedensity, and the breakdown voltage of the capacitor is 40 V. Itshould be mentioned that the skin depth of Cu is only 3.76 μm at300 MHz, which implies that the top metal thickness of 10 μmin the IPD process is sufficient for low signal loss at the targetedoperating frequency. In the proposed design, all the passive el-ements including the gate driver (except CSB and RSB in the


Fig. 10. (a) Layout of the choke inductor L1 . (b) Simulated and measuredinductance and quality factor Q of L1 .

Fig. 11. (a) Conceptual plot of the interconnects used in the proposed UHFpower converter, which is similar to a microstrip structure for RF applications.(b) Comparison of simulated parasitic inductance of the interconnects with andwithout the ground plane M1.

CMOS driver, see Fig. 4) and the class-E power converter arerealized by IPD. Compared with implementing these compo-nents on either CMOS or GaN technology, IPD devices havethe advantages of low cost and high quality factor.

Fig. 10(a) shows the layout and three-dimensional plot of theinput choke inductor L1 , which is critical to the efficiency ofthe class-E resonant power converter. The planar spiral induc-tor is designed with an octagonal shape to mitigate resistiveand capacitive losses [61]. Fig. 10(b) compares the full waveEM-simulated and measured results of the inductor. As can beseen, the measured and simulated inductances are in a goodagreement. The discrepancy between the quality factors maybe attributed to the process variation with the change of aver-age metal thickness or conductivity. The CMOS gate driver andthe GaN devices are flip-chip assembled together on the IPDsubstrate with the IPD passive devices, which minimizes theparasitic effects caused by bond wires.

Fig. 11(a) shows the interconnect structure of the IPD layoutin the proposed UHF power converter, which allows to reducethe parasitic effects for high-frequency operation. The structureemployed here is similar to a microstrip line typically used for

Fig. 12. IPD layout of the proposed UHF power converter, where the locationsof different components are highlighted, including the three GaN HEMTs andtwo GaN Schottky diodes, and also the CMOS gate driver.

RF applications. The signal line is realized by the thick metalM3 of the IPD process, and the ground line is implemented byM1 as a plane throughout the whole chip for a common ground.With the paracitic capacitance CSTR existing between the twometal layers, the combination of the stray inductance LSTR andCSTR forms a microstrip transmission line structure. As a re-sult, the characteristic impedance of the interconnect becomesmaily with the real part, and the stray inductance can be effec-tively reduced. Fig. 11(b) compares the simulated results of a1000-μm line in the actual IPD layout (width of 300 μm) withand without using M1 as ground. The result clearly indicates re-duced parasitic inductance. Another point should be mentionedis that the substrate effect could also play a role as the operatingfrequency enters the UHF range. The shielding ground planerealized by M1 can isolate the coupled signals via the substrate,which minimizes the undesired interference in the circuit.

Fig. 12 presents the overall IPD layout of the power converter,where the locations of different components (see Fig. 4) arehighlighted, including the three 5000-μm GaN HEMTs (S1) andtwo 5000-μm GaN Schottky diodes (D1), and also the CMOSgate driver. In practical design, the sizes of the IPD inductorsare determined first due to the considerations of quality factorand chip area. For example, a large L1 is preferred as the RFchoke, but the final design is limited by the degraded qualityfactor as size increases, which is about 20 with a inductance of33 nH based on simulation. Similarly, the initial value of LRECTis designed based on the equations mentioned previously, butoptimization is essential to obtain a reasonable quality factorat the desired operating frequency for the overall efficiency. Inaddition, LS is determined first and then combined with CS

to resonant at around the second harmonic in the gate driver.The inductor load LD is optimized with CIN , LS , and CS [seeFig. 6(a)] to shape the gate driver output voltage, and CB isrelatively large as a dc block. It should be emphasized that thecore circuit only occupies about half of the chip area. The restof the chip is mainly employed to obtain sufficient COUT in therectifier stage for reducing the output ripple. The capacitancesfor C1 , CRECT , and COUT in the final design are 17 pF, 36 pF,and 11 nF, respectively. The IPD area can be further reduced ifcapacitance with a higher density could be realized in the IPDtechnology or part of the capacitance is also flip-chip stackedon the substrate.


Fig. 13. Simulated results of the UHF power converter (load = 50 Ω). (a) Time-domain waveforms of voltage and current for the GaN HEMT switchingtransistor, and (b) output voltage and efficiency as a function of input voltage at 300 MHz.

Fig. 14. Micrographs of (a) 0.18-μm CMOS gate driver, and (b) 0.25-μmGaN HEMT (125 μm × 40).

Fig. 15. (a) Photo of the flip-chip assembled power converter, and (b) circuitphoto and on-wafer measurement (inset).

Fig. 13(a) shows the simulated waveforms of the GaN switch-ing transistor S1 in the circuit. The maximum VDS and IDS areabout 22 V and 2.7 A (VIN = 8 V), respectively. The relativelysmall overlap between the voltage and current waveforms indi-cates that the design approaches the ZVS operating condition.The simulated results show that the switching loss is about15.1% of the total loss under this condition. It should be men-tioned that this design is optimized at 300 MHz. Reducing theswitch frequency results in deviation from the ZVS condition inthe resonant-type power converter, which is not helpful to fur-ther reduce the overlap as can be observed from the simulation.Fig. 13(b) shows the simulated output voltage and efficiency asa function of VIN . As can be seen, the maximum efficiency canbe obtained is around 52% and the maximum VOUT exceeds25 V.

One issue should be discussed here is the closed-loop controlof the proposed circuit, which is a critical part of the whole

system. As mentioned previously, this work focuses on usingnovel SiP technology to explore the possibility of achievinghigh-speed UHF dc–dc power converter with a high power den-sity. The closed-loop control is not within the scope of thiswork. Although not actually implemented, one possible controlconfiguration can be used is the ON–OFF control scheme, whichwas reported for resonant power converters [10], [11]. The con-trol algorithm is relatively simple, but practical implementationbecomes challenging as the operating frequency increases. Themain limitation could be the required high-speed comparatorin the control circuit. Also, the stability of the circuit could bean issue in the board level design with unpredicted parasiticeffects. It should be mentioned that the closed-loop controllerdemonstrated in previous works [10], [11] used the commer-cially available ICs to achieve the goal. In our design, we havethe advantages of SiP technology with CMOS circuits. Thecontrol circuitry can be integrated with the gate driver using thestandard CMOS process, which can reduce the cost and mini-mize the parasitic effects by the flip-chip package and is suitablefor high-frequency operation.

IV. RESULTS AND DISCUSSION

Fig. 14(a) and (b) shows the chip micrographs for the CMOSgate driver and the GaN HEMT device (125 μm × 20 fingers ×2), respectively. The overall circuit photo of the fully assembledconverter on the IPD substrate is shown in Fig. 15(a). Fig. 15(b)shows the photo of the power converter, with the inset showingthe on-wafer measurement using RF and dc probes. Fig. 16(a)and (b) shows the measured output power and dc voltage ofthe proposed class-E power converter at 300 MHz. An outputpower of 4.16 W (load = 50 Ω) and output voltage of 18 V(load = 100 Ω) can be achieved at VIN of 12 V at 300 MHz.Fig. 16(c) plots the corresponding output current versus theinput voltage. As can be observed, the current level reduceswith the increased load, and the maximum current level in themeasured voltage range is 288.5 mA (load = 50 Ω). Fig. 16(d)compares the measured and simulated output current levels. Thediscrepancy increases with VIN , which implies that the thermaleffect becomes more significant at high power levels and cannotbe predicted accurately by the provided model. Fig. 17(a) showsthe measured overall efficiency of the proposed class-E power


Fig. 16. Measured (a) output power, (b) output voltage, and (c) output current as a function of input voltage of the proposed class-E power converter.(d) Comparison between the simulated and measured output current.

Fig. 17. (a) Measured overall efficiency of the proposed class-E power converter. (b) Measured output ripple with different input voltages.

converter. The highest efficiency of 47.3% can be obtained atVIN = 12 V with a load of 50 Ω. The result indicates a trend ofreduced efficiency when the load moves away from the targetvalue (50 Ω in this design). Fig. 17(b) shows the output rippleat different input voltages with a 50-Ω load, which is relativelysmall compared with the fully integrated converters reported in[9]. It should be emphasized that the reduced efficiency com-pared with the simulated results as shown in Fig. 13(b) can bemainly attributed to the degraded GaN device characteristicsdue to thermal effect, which is difficult to be predicted accu-rately in the foundry provided model. Another reason is thereduced Q factor of the IPD inductor compared with simulation

(see Fig. 10), which also introduces extra loss and degrades theoverall efficiency.

Fig. 18 analyzes the loss from different parts of the powerconverter based on simulation. The values of total power lossPloss are 5.79, 6.96, and 7.89 W (total output power Pout are6.17, 5.77, and 5.23 W) respectively, corresponding to the loadsof 50, 75, and 100 Ω. Note that the measured results underthis condition (VIN = 8 V) for Ploss are 2.80, 3.43, and 4.38 W(Pout are 2.22, 2.11, and 1.89 W). The efficiency limitationof the resonant power converter presented in this work can bemainly attributed to the loss of the power transistor and the lossof spiral inductors. As shown in the figure, the loss of the power


TABLE ICOMPARISON WITH PREVIOUS WORKS OF HIGH-SPEED POWER CONVERTERS IN DIFFERENT TECHNOLOGIES

Ref. Type Topology Technology fSW(MHz)

VIN /VOUT(V)

IOUT ,m ax(mA)

POUT ,m ax(W)

ηm ax(%)

Area/volume(cm2 /cm3 )

Power density(W/cm2 )

[3] Module ResonantStep-up

Discrete MOSFET +PCB

100 12/23.7 72 1.7 55 N/A N/A

[4] 60 6/15 467 7 77 N/A N/A[5] Step-down GaN IC + discrete

component + PCB200 25/10 256 3.3 73 N/A N/A

[6] PSiP Step-down CMOS IC + stackedCMOS LC component

200 3.3/2.3 70 0.161 62 0.2 × 0.2 4

[7] CMOS IC + bond wireinductor

50 3.3/2 300 0.6 68.7 0.36 × 0.28∗0.72 × 0.64∗∗

5.95∗1.3∗∗

[8] PSoC Step-down CMOS IC 225 2.6/1.2 600 0.8 58 0.16 × 0.235 21[9] Step-up GaN IC 680 12/20.2 90 1.8 34 0.3 × 0.3 20

Thiswork

PSiP ResonantStep-up

GaN IC + CMOS IC +IPD

300 12/18# 288 4.16 47.3 0.94 × 0.98/0.115 4.5/36.2 (W/cm3 )

∗Bonding wires not included; ∗∗Estimated including the bond wires; and #Maximum output voltage condition.

Fig. 18. Analysis of loss from different parts of the proposed class-E powerconverter for three different loads based on simulated results.

transistor is in the range of 36–50% including both switchingand conduction losses. Also, the loss of the choke inductor L1plays an important role, up to 23–25% of the total. The majorpart in the loss of others comes from LRECT in the parallel LCresonant tank. Compared with the conventional hard switchingconfiguration, the higher conduction loss can be attributed tothe larger current (2.86× of the input dc current) in the class-E topology. Also, the 2-D planar inductor adopted here witha relatively lower Q limits the overall efficiency, especially therelatively large inductors L1 and LRECT . It should be mentionedthat the GaN HEMT devices have a high channel mobility andis expected to result in a small conduction loss. However, thepronounced thermal effect here seriously degraded the transis-tor performance, which can be improved by proper packagingtechnology of the GaN devices. In addition, compared with mostpreviously published hard switching designs using the discreteinductors with much higher Q, the 2-D planar inductor in theIPD technology is much compact but the lower Q degrades theoverall efficiency. If the discrete RF choke is employed or theIPD technology can be further improved with novel low-lossmagnetic materials, the overall efficiency in the proposed de-sign is expected to be further increased. The simulated resultsindicate if the Q factor is doubled and RON of the switching

transistor and diode are reduced by half, the efficiency of theproposed power converter can be improved to 74%. With theproposed resonant gate driver, the loss is well controlled. Thetrend of increased transistor loss can be observed when the loaddeviates from a target of 50 Ω due to the change of the resonantfrequency of the class-E topology. This also explains the obvi-ously increased switching loss at light load operation of 100 Ω.As a result, the ZVS condition cannot be maintained, leading toefficiency reduction [12], [62]. Studies have been reported thatproposed solutions to this issue [62], [63].

Table I compares the published high-frequency (from tens upto hundreds of MHz) power converters in different packagingtypes and technologies. The class-E and class Φ2 dc–dc con-verters operating at 100 and 60 MHz were reported in [3] and[4], respectively, using discrete components on the printed cir-cuit board (PCB) to demonstrate the resonant-type convertersin the VHF range. An open-loop power converter with the GaNHEMTs operating at 200 MHz showed the possibility of usingthe high switching power converter for EER applications [5].The studies in [6]–[8] utilized the CMOS passive components orbond wire inductor to demonstrate the potential of PSiP/powersystem-on-a-chip (PSoC) for low-power and high-speed appli-cations. The circuit reported in [9] employed a fully integratedboost converter using GaN technology, and a high power densitycan be obtained at a switching frequency of 680 MHz. Com-pared with the prior arts listed in Table I, this work presents aneffective approach using IPD heterogeneous integration for highpower density with more design flexibility and low cost. As canbe seen, the proposed resonant-type class-E design demonstratesa relatively high operating frequency compared with other PSiPstudies. Also, the output power is among the highest comparedwith all the PSiP and PSoC designs. The efficiency of this workalso achieves a level that is comparable with other PSiP or PSoCwork.

V. CONCLUSION

A 300-MHz class-E dc–dc converter with a resonant gate driv-ing technique was proposed and implemented using 0.25-μm


GaN HEMT power devices, a 0.18-μm CMOS gate driver, andIPD passive components. With all microfabricated componentsand circuit blocks, the miniaturized converter was fully inte-grated by a flip-chip assembly on the IPD substrate and hasa volume of only 0.115 cm3. A maximum output power of4.16 W and a corresponding power density of 36.2 W/cm3 canbe obtained. The achieved efficiency of 47.3% was also com-parable with the recently published work on highly integratedconverters at high frequencies. This study demonstrates the pos-sibility to realize highly integrated power converters using theapproach of heterogeneous integration of different processes fornext-generation miniature power converters. It should be em-phasized that the limitations of the presented power converterare mainly from the thermal effect of GaN power devices andthe relatively low Q of the IPD inductors. The thermal effectcould be reduced by introducing proper package technology.Also, the low-loss magnetic materials may be incorporated toenhance the quality factor of the inductive components in theIPD process.

ACKNOWLEDGMENT

The authors would like to thank Dr. Ta-Yeh Lin at NationalChip Implementation Center (CIC), Hsinchu, Taiwan, for chipassembly.

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Ming-Jei Liu was born in San Francisco, CA. Hereceived the M.S. degree from the Institute of Elec-tronics Engineering, National Tsing Hua University,Hsinchu, Taiwan, R.O.C., in 2016. His thesis focusedon high speed switch mode DC-DC power converter.

He is currently an Analog Circuit Design Engineerwith SONiX Technology, Hsinchu, Taiwan, R.O.C.

Shawn S. H. Hsu (M’04) received the B.S. degree inelectrical engineering from the National Tsing HuaUniversity, Hsinchu, Taiwan, R.O.C., in 1992, andthe M.S. and Ph.D. degrees in electrical and com-puter engineering from the University of Michigan atAnn Arbor, Ann Arbor, MI, USA, in 1997 and 2003,respectively.

He is currently a Professor with the Departmentof Electrical Engineering, Institute of Electronics En-gineering, National Tsing Hua University. He is in-volved in the design, fabrication, and the modeling

of high-frequency transistors and interconnects. His current research interestsalso include the design of monolithic microwave integrated circuits and RF-integrated circuits using Si/III–V-based technologies, heterogeneous integrationusing system-in-package, and three-dimensional integrated circuit technologyfor high-speed wireless/optical communications and power electronics applica-tions.

a miniature 300-mhz resonant dc–dc converter with gan ... papers/tpe_300 mhz dc... · 9656 ieee...

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