a non-linear neural classifier and its applications in testing analog/rf circuits*
DESCRIPTION
A Non-Linear Neural Classifier and its Applications in Testing Analog/RF Circuits*. Haralampos Stratigopoulos & Yiorgos Makris. Departments of Electrical Engineering & Computer Science YALE UNIVERSITY. * Partially supported by NSF, SRC, IBM & Intel. Test and Reliability @ YALE. - PowerPoint PPT PresentationTRANSCRIPT
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A Non-Linear Neural Classifier and its Applications in Testing
Analog/RF Circuits*
Haralampos Stratigopoulos & Yiorgos Makris
Departments of Electrical Engineering & Computer Science
YALE UNIVERSITY
* Partially supported by NSF, SRC, IBM & Intel
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Test and Reliability @ YALE
http://eng.yale.edu/trela
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Current Research Areas
Machine learning-based approach for test cost reduction Design of on-chip checkers and on-line test methods Neuromorphic built-in self-test (BIST)
Analog/RF circuits
Concurrent error detection / correction methods (FSMs) RTL Concurrent error detection in microprocessor controllers Design transformations for improved soft-error immunity (logic)
Reliability
Fault simulation, ATPG, test compaction for SI circuits Test methods for high-speed pipelines (e.g. Mousetrap) Concurrent error detection and soft-error mitigation
Asynchronous circuits
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Outline • Testing analog/RF circuits
• Current practice
• Limitations and challenges
• Summary
• Testing via a non-linear neural classifier• Construction and training
• Selection of measurements
• Test quality vs. test time trade-off
• Machine learning-based testing• General idea
• Regression vs. classification
• Experimental results
• Analog/RF specification test compaction
• Neuromorphic BIST
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Analog/RF IC Test – Current Industry Practice
Interface BoardWafer
• Post-silicon production flow
Automatic Test
Equipment (ATE)
Chip
designspecifications
performanceparameters
compare
pass/fail
• Current practice is specification testing
chip
test configurations
ATE
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Limitations
• Expensive ATE (multi-million dollar equipment)
• Specialized circuitry for stimuli generation and response measurement
Test Cost:
• Multiple measurements and test configurations
• Switching and settling times
Test Time:
• Fault-model based test – Never really caught on
• Machine learning-based (a.k.a. “alternate”) testing– Regression (Variyam et al., TCAD’02)
– Classification (Pan et al., TCAS-II’99, Lindermeir et al., TCAD’99)
Alternatives?
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Machine Learning-Based Testing
• Determine if a chip meets its specifications without explicitly computing the performance parameters and without assuming a prescribed fault model
General idea:
• Infer whether the specifications are violated through a few simpler/cheaper measurements and information that is “learned” from a set of fully tested chips
How does it work?
• Since chips are produced by the same manufacturing process, the relation between measurements and performance parameters can be statistically learned
Underlying assumption:
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Regression vs. ClassificationProblem Definition:
simple functions
performanceparameters
specification tests(T1, … , Tk)
designspecifications
compare
pass/fail
unknown,complex,non-linear functions
(no closed-form)
alternate tests(x1, … , xn)
Use machine-learning to approximate these functions
• Explicitly learn these functions (i.e. approximate f:x → )
Regression:• Implicitly learn thes
e functions(i.e. approximate f:x→Y,Y={pass/fail})
Classification:
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Overview of Classification Approach
specification tests
pass/fail labels
training set of chips
projection on measurement space -0.025 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
x1
x 2
Nominal patterns
Faulty patterns
simpler measurements
acquisition of measurement patterns
trained classifier
new (untested) chip measurement pattern
pass/fail label
TESTING
learn boundaryLEARNING
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Order of Separation Boundary
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
-1
-0.5
0
0.5
x1
x 2
Nominal patterns
Faulty patterns
• The boundary that best separates the nominal from the faulty classes in the space of the simple measurements can be highly non-linear
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Previous Work: Linear Methods(Lindermeir et al., TCAD’99, Pan et al., TCAS-II’99, Variyam et al., TCAD’00)
i n, allocate a hyper-plane bi that optimally separates
the patterns when labeled with regards to specification i
• Acceptance region is bounded by intersection
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
-1
-0.5
0
0.5
x1
x 2
Nominal patterns
Faulty patternsb2
b3
b1
b4
b5 b6
• Decomposition into n two-class problems solved individually
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Our Solution: Non-Linear Neural Classifier
• Allocates a single boundary of arbitrary order
• No prior knowledge of boundary order is required
• The topology is not fixed, but it grows (ontogeny) until it matches the intrinsic complexity of the separation problem
• Constructed using linear perceptrons only
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Linear Perceptron
1x dx
iy
1ox
0iw
1iw
diw
perceptron connectivity
synapses
d
jjx
0jiw
iy (x)
0
1
-1
perceptron output
threshold activation function
geometric interpretation
1x
2x
d
jjx
0jiw 0
1
Nominal patterns
Faulty patterns
iy (x) for nominal
-1iy (x)for faulty
adjustsji
wtraining
to minimizeerror
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Topology of Neural Classifier
11x dx
1y
ox
0iw1iw
diw
• Every newly added layer assumes the role of the network output
iy
, yi
iy
2i
iy
1
2w
, yiw w
1ox
1y
1y
1
y3iy
2
w, iyi
1i0i
1iw
diw
1diw
1ox
y
d
iid xx
1
21
2
1ox
• Pyramid structure– First perceptron receives
the pattern x Rd
– Successive perceptrons also receive inputs from preceding perceptrons and a parabolic pattern xd+1=xi
2, i=1…d
• Non-linear boundary by training a sequence of linear perceptrons
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Training and Outcome• Weights of added layer are adjusted through the
thermal perceptron training algorithm
• Allocated boundary is non-linear in the original space x Rd
• Each perceptron separates its input space linearly
• Weights of preceding layers do not change
Theorem: • The sequence of boundaries allocated by the neurons
converges to a boundary that perfectly separates the two populations in the training set
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Boundary Evolution Example (layer 0)
Faulty patterns erroneously classifiedFaulty patterns correctly classified
Nominal patterns erroneously classifiedNominal patterns correctly classified
x1
x 2
-2 -1.5 -1 -0.5 0 0.5 1 1.5-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
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Boundary Evolution Example (layer 1)
Faulty patterns erroneously classifiedFaulty patterns correctly classified
Nominal patterns erroneously classifiedNominal patterns correctly classified
-2 -1.5 -1 -0.5 0 0.5 1 1.5-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
x1
x 2
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Boundary Evolution Example (layer 2)
Faulty patterns erroneously classifiedFaulty patterns correctly classified
Nominal patterns erroneously classifiedNominal patterns correctly classified
-2 -1.5 -1 -0.5 0 0.5 1 1.5-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
x1
x 2
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Boundary Evolution Example (output layer)
Faulty patterns erroneously classifiedFaulty patterns correctly classified
Nominal patterns erroneously classifiedNominal patterns correctly classified
-2 -1.5 -1 -0.5 0 0.5 1 1.5-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
x1
x 2
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Matching the Inherent Boundary Order
• Monitor classification on validation set
• Prune down network to layer that achieves the best generalization on validation set
• Evaluate generalization on test set
Finding The Trade-Off Point (Early Stopping)
• No! The goal is to generalize
• Inflexible and over-fitting boundaries
Is Higher Order Always Better?
0 2 4 6 8 10 12 1470
75
80
85
90
95
100
number of layers
rate
(%
)
training setvalidation set
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Are All Measurements Useful?
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2-3
-2
-1
0
1
2
3
4
Nominal patterns
Faulty patterns
Non-Discriminatory
x1
x 2
-4 -3 -2 -1 0 1 2 3 4-4
-3
-2
-1
0
1
2
3
4
Nominal patterns
Faulty patterns
Linearly Dependent
x1x 2
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Curse of Dimensionality
• Several possible boundaries exist – choice is random
• By increasing the dimensionality we may reach a point where the distributions are very sparse
New patterns
• Random label assignment to new patterns
Nominal training patterns
Faulty training patterns
Nominal training patterns
Faulty training patterns
Nominal training patterns
Faulty training patterns
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Genetic Measurement Selection• Encode measurements in a bit string, with the k-th bit
denoting the presence (1) or the absence (0) of the k-th measurement
0 1 1 0 1 1 1 0 0 1
0 0 0 0 1 1 1 0 0 1
1 1 1 0 1 1 0 0 0 0
0 1 1 1 1 0 1 0 0 0
1 0 1 0 1 1 1 0 0 0
0 1 0 0 1 0 1 0 1 1
0 0 1 0 1 1 1 0 1 1
0 0 1 0 1 1 1 0 0 1
0 1 1 0 1 1 0 0 0 0
0 1 1 1 1 1 0 0 0 0
1 0 1 0 1 1 1 0 0 0
0 1 0 0 1 0 1 0 0 0
ReproductionCrossover &
Mutation
GENERATION
tGENERATION
t+1
NSGA II: Genetic algorithm with multi-objective fitness function reporting pareto-front for error rate (gr) and number of re-tested circuits (nr)
Fitness function:
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Two-Tier Test Strategy
Low-Cost Tester
All ChipsSimple
AlternativeMeasurements
Neural Classifier
Most Chips
Highly AccuratePass/FailDecision
MeasurementPattern in
Guard-band
Few Chips
High-Cost Tester
SpecificationTest
Measurements
Compare
Highly Accurate Pass/Fail Decision
DesignSpecs
Inexpensive Machine Learning Test
Expensive Specification Test
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Reasons for Non-Zero Classification Error
2.25 2.3 2.35 2.4 2.45 2.5 2.551.65
1.7
1.75
1.8
1.85
1.9
x1
x 2
Nominal patterns
Faulty patterns
test hypersurface
• Continuity of analog signals and parametric drifts
• Finite training set
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Guard-bands
2.25 2.3 2.35 2.4 2.45 2.5 2.551.65
1.7
1.75
1.8
1.85
1.9
nominal guard-band
faulty guard-band
x1
x 2
Nominal patterns
Faulty patterns
test hypersurface
Guard-banded region
• Introduce a trichotomy in the measurement space in order to assess the confidence of the decision
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Testing Using Guard-bands
• Examine measurement pattern with respect to the guard-bands
2.25 2.3 2.35 2.4 2.45 2.5 2.551.65
1.7
1.75
1.8
1.85
1.9
nominal guard-band
faulty guard-band
x1
x 2
Nominal patterns
Faulty patterns
test hypersurface
Guard-banded region
Classify chip to dominant class
Re-test viaspecification test
• Identify circuits that need to be re-tested via specification tests
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Guard-band Allocation
D
• Identify the overlapping regions
• Guard-bands are allocated separately
• The ontogenic classifier allocates the guard-band
D
• Clear the overlapping regions
D
Nominal patterns
Faulty patterns
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Guard-band Allocation
D
D D
D
• The guard-banded region can been varied by controlling D
Nominal patterns
Faulty patterns
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Experiment 1: Switch-Capacitor Filter
C1A
C2A
C2B
C4A
C4B
C5A
C1
C2
C3
C4
C5
C1C
C3A
C3B
C5B
C5C
C3D
C1D
C3C
C1BVin
Vout
1
2 2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
1
2
2
2
2
Specifications considered
• Ripples in stop- and pass-bands
• Gain errors• Group delay• Phase response• THD
Experiment Setup
• N=2000 instances• N/2 assigned to the
training set, N/4 to the validation set and N/4 to the test set
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White-Noise Test Stimulus
CLK
Din QnQm
LP filter
Type-1 LFSR
DUTsignature
DUT digitizer
pseudo-random bit sequence white noise
Time (ms)0
-2.0
0
2.0
4.0
Vol
tage
(V)
2 4 6 8 10 12 14 16 18
DUTsignature
pseudo-random bit sequence
white noise
t1 t2 t30
tr
ts
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Test Time vs. Test Accuracy Trade-Off
(0%,4%)
(8.1%,2%)
(15.6%,0.6%) (20.7%,0%)
0 5 10 15 20 25 30 35 40 450
1
2
3
4
5
6
7
8
retested circuits (%)
test
err
or
(%)
f2
f1
f3
guard-bands test time=15msspecification test time >0.5s
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Experiment 2: RFMD2411
Gain 3rd Order Intercept
Noise Figure
Other S Parameters
LNA x x x x x xMixer x x x x - -
LNA + Mixer (Cascade)
x x x - - -
• 541 devices (training set 341, validation set 100, test set 100)• Considered 13 specs @850MHz (7 different test configurations)
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Test Configuration
Stimulus
DUT Response
0 1 2 3 4 5 6 7 8 9 10
x 107
0
50
100
150
200
250
300
350
400
450
frequency
FF
T o
f D
UT
re
spon
se
noise floor
28 tones
FFT
DUT
TestSignal
xt(t)
f1 f2
Mixer
DUTsignature
xs(t)LPF
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0 5 10 15 20 25 30 35 40 45 500
1
2
3
4
5
6
7
8
retested circuits (%)
test
err
or
(%)
f2 (gr<2)f2 (gr<4)f3
f1
(0%,3.92%)
(11.67%,1.96%)
(27.62%,0%)
Test Time vs. Test Accuracy Trade-Off
guard-bands test time=5msspecification test time ~1s
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Analog/RF Specification Test Compaction
• Instead of “other, alternate measurements” use existing inexpensive specification tests to predict pass/fail for the chip and eliminate expensive ones
Non-disruptive application:
• RFCMOS zero-IF down-converter for cell-phones
• Fabricated at IBM, currently in production
• Data from 944 devices (870 pass – 74 fail)
• 136 performances (65 non-RF – 71 RF)
• Non-RF measurements assumed much cheaper than RF, aim at minimizing number of measurements
Case-Study:
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Setup and Questions Asked
• How accurately can we predict pass/fail of a device using only a subset of non-RF measurements?
Question #1:
• How does this accuracy improve by selectively adding a few RF measurements to this subset?
Question #2:
• Split 944 devices into training and test set (472 devices each, chosen uniformly at random.
• Repeat 200 times and average to obtain statistically significant results
Setup:
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Results
Only non-RF performances:
• 15 measurement suffice to predict correctly over 99% of the devices (in our case 4 out of 472 are on average mispredicted
Adding RF performances:
• By adding to these 15 non-RF performances 12 RF performances, error drops to 0.38% (i.e. 1 out of 472 devices mispredicted)
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What’s Next? Neuromorphic BIST
• On-chip generation of simple test stimulus
• On-chip acquisition of simple measurements
• On-chip implementation of trainable neural classifier
A stand-alone BIST method for mixed-signal/RF circuits:
On-ChipStimulus
Generator
AnalogMux
Mixed-Signal
/RF
Circuit
ProgrammableResponseAcquisition
TrainableOn-Chip Neural
Classifier
Input
Output
BIST Input
BIST Output
BIST Control
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Summary
• A non-linear neural classifier supporting a novel paradigm for testing analog/RF circuits – Achieves significant reduction in test cost
without sacrificing accuracy of specification test– Enables exploration of trade-off between
test cost and test accuracy via guard-bands
Contribution:
• Non-disruptive: Specification test compaction• Disruptive: Machine learning-based test • Futuristic: Neuromorphic BIST
Applications:
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More Information
• E-mail: [email protected], [email protected]
Contact:
• H-G. D. Stratigopoulos, Y. Makris, “Constructive Derivation of Analog Specification Test Criteria,” Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 245-251, 2005
• H-G. D. Stratigopoulos, Y. Makris, “Non-Linear Decision Boundaries for Testing Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T.CAD), pp. 1360-1373, Nov. 2005
• H-G. D. Stratigopoulos, Y. Makris, “Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing,” Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 406-411, 2006
• H-G. D. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, “Non-RF to RF Test Correlation Using Learning Machines: A Case Study,” Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 9-14, 2007
• H-G. D. Stratigopoulos, Y. Makris, “Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing ,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T.CAD), pp. 339-351, Feb. 2008
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