a novel 12-bit _isa_ for introducing novice students to instruction set

1 of 28Copyright © 2013 File: WESE‐Presentation‐20131004B.pptx Title: WESE‐2013 ‐ VIP

A novel 12‐bit ISA for introducing novice students to instruction set paradigms,

their use and implementation

WESE‐ October 3rd 2013, Montreal, CanadaDr. David C. Dyer BSc (Hons) PhD (Warwick)

CPhys MInstP CEng FIET CITP MBCSSchool of Engineering, University of Warwick, UK

People Framework Tools Mind‐set

VIP : Various Instruction Paradigms


Topics – What comes first? Holistic?

Why develop VIP ?• Background – why ‘doing’ is so important• Some personal experiences

Comparisons with other ISAs – Hardcore vs Softcore• Commercial• Educational – are there any educational ISA softcores?

Technical characteristics of VIP – with slides from classes• Why 12 bits?• Programmer’s Model• Assembly level, Compilers, Algorithms and HDLs

Examples of code usage Demonstration of simulator – time permitting?


NXP SmartMX2 – year 2010


Dale’s Cone of Experience

Source: Computer Strategies, LLC, 1998

10% of what they read

90% of what they say, discuss, and do

70% of what they say and write

50% of what they hear and see

30% of what they see

20% of what they hearRead

Hear

View Images

Watch Videos

Attend Exhibit/Sites

Watch a Demonstration

Participate in Hands‐on Workshop

Design Collaborative Lesson

Simulate or Model Lesson or Experience

Design/Perform a Presentation – Do the “Real Thing”

•Demonstrate

•Apply

•Practice

•Analyze

•Design

•Create

•Evaluate

•Define

•List

•Describe

•Explain

People (students) generally remember: People (students) are able to:

Introduced by Edgar Dale (1946) in his textbook on audio‐visual methods in teaching.


What is there to learn about ISAs?

Half empty ?

Half full ?

Do (novice) students see how much they have learned orhow much they have yet to learn?• Is the glass half full of half empty?

Unknown %Principle or Idea %

Detail %

UnknownDetail

Principle or Idea


Why be concerned with ISA encoding ?

Encoding instructions efficiently can• Save memory = increase reliability• Increase ‘performance’• Reduce energy• Reduce costs

Program

Application Execute


Which ISA should we teach?

Manufacturers often have unique ISAs or licenced them from each other.• Having multiple suppliers is an important commercial consideration.

The Intel 8051 (from 1980) and x86 families are multiply sourced and latterly so too the ARM’s Cortex series.• All are very different. • ARM* and MIPS and PowerISA are non‐trivial

Many processors have been designed to assist teaching and learning of ISAs. E.g. MARIE, ANT8, XTOY and TinyCPU.• But which has a ‘carry’ bit ? – None ! ?• How does ‘carry’ behave during subtract?


Capabilities of PIC16 Microcontroller

PIC1640 ARCHITECTURAL DESCRIPTION“... The primary purpose of the Programmable Interface Controller (PlC) is to perform logical processing, basic code conversions, formatting, and to generate fundamental timing and control signals for I/O devices. The emphasis is on control and interface functions as opposed to computing functions.”(General Instrument MOS Databook 1976 Page 211)


Capabilities of PIC16 Microcontroller

PIC1650 ARCHITECTURAL DESCRIPTION“... The primary purpose of the Programmable Interface Controller (PlC) is to perform logical processing, basic code conversions, formatting, and to generate fundamental timing and control signals for I/O devices. The instruction set also supports computing functions as well as these control and interface functions.”(General Instrument MOS Databook 1976 Page 214)

PIC1650 instruction set is identical to PIC1640. Therefore, no more capable. What did the designers intend?


Block Diagram vs Programmer’s Model of a CPU

Generic data flow but no information about data width or number of registers. Von‐Neumann model

8‐Bit data, 16‐bit address => 216=65536 BytesNo Register file, named accumulators A and B. Could have been called R0 and R1? It’s a matter of convention. Fundamental interface signals.


What is ARM* ARM7 vs ARMv7 (includes Thumb‐2)

ARM7 in 1993 = ‘device’ ‐ ARMv7 (2005) = architecture

From “Improving ARM Code Density and Performance New Thumb Extensions to the ARM Architecture by Richard Phelan of ARM June 2003”


ARM’s big.LITTLE – too much for a novice

Heterogeneous multi‐processors designed to save power • Dynamic redistribution of software between Cortex‐A7 and A15 cores in real‐time to meet time and energy targets


ARM’s big.LITTLE – too much for a novice

Note: Cortex‐A7 Core (left) has fewer recourses than the A15 (below) but the net effect of each instruction is identical. The logical outcomes are the same but the physical realisations are different. A15 has more execution units with longer pipelines


Various Instruction Paradigms – VIP ‐ architecture

Paradigm means• “an example that serves as a pattern or model for something, especially one that forms the basis of a methodology or theory” Encarta Dictionary.

VIP is a 12‐bit processor especially designed for teaching multiple principles in Instruction Set Architectures.

Its ISA is formed from easy‐to‐read 4‐bit fields.

11 10 9 8 7 6 5 4 3 2 1 0

0‐7 Dual operand d s8 Short Move d n9‐A Unary or Control Operation s/d or nB‐F JMP 2’s complement ‐128 to +127 relative displacement


Why 12 bits? – a few reasons – refer to full paper

Not only 12 bits but field boundaries are in 4s• Desire is to make op‐codes and encoding schemes easy to remember, question and re‐invent

If processing text in ASCII, memory is wasted but it is efficient for 2 DEC 6‐bit codes as used in credit cards.• Allows discussion about non‐ASCII representations

Students/Tutors may consider extensions to 16‐bit op‐codes• with, say, 3 operands or more registers etc.

Not only 12‐bit op‐codes but with a ‘modest’ number of non‐trivial instructions.• May be managed in subsets for exercises and quizzes.

Reverse the question – why not 12 bits ?


Programmer’s Model and Addressing modes

VIP has registers R0 to R3, AR, SR, SP and PC, but with overlaid names and mnemonics A, B, X, and Y. This enables ‘register‐based’ and ‘accumulator’ models.

Register Assembler Syntax MeaningR0 or A R0 or [R0] Register or register indirect respectivelyR1 or B R1 or [R1] Register or register indirect respectivelyR2 or X R2 or [R2+n] Register or register with offset indirectR3 or Y R3 or [R3+n] Register or register with offset indirect

AR AR Auxiliary Register for special instructionsSR SR Status RegisterSP SP or [SP+n] Stack Pointer or Stack Pointer relativePC PC or [PC+n] Program Counter or Program Counter relativeImmediate #n Data is in next wordAbsolute [n] Data is at given memory address


What does a VIP program look like?

E.g to compute the first 16 Fibonacci numbers.• F(0)=0; F(1)=1; F(n)=F(n‐2)+F(n‐1) ‐Where are these used?• 0, 1, 1, 2, 3, 5, 8, 13, …

Adr Opcodes Mnemonic000 01C 100 MOV R1,#0x100002 850 MOVS [R1],#0003 901 INC R1004 851 MOVS [R1],#1005 88E MOVS AR,#0xE006 901 INC R1007 021 MOV R2,R1008 006 FFE MOV R0,[R2+0xFFE]00A 406 FFF ADD R0,[R2+0xFFF]00C 050 MOV [R1],R000D A88 JDAR -8

R1 = Address of F(0)F(0)=0R1 = Address of F(1)F(1)=1Loop counter AR = 14R1 = Address of F(n)Copy of current addressR0 = F(n-2)R0 = R0 + F(n-1)F(n)= F(n-2) + F(n-1)Decrement AR and ifnon-zero jump back 8

5 instruction types, but how many does a processor need?

E.g. 0 means MOVe, 4 means ADD


What does a VIP program look like?

E.g to compute the first 16 Fibonacci numbers.• F(0)=0; F(1)=1; F(n)=F(n‐2)+F(n‐1)• 0, 1, 1, 2, 3, 5, 8, 13,

Adr Opcodes Mnemonic030 00C 100 LDA #0x100032 810 LDB #0033 821 LDX #1034 041 STB [A]035 012 LDB X036 424 ADDX [A]037 900 INCA038 70C 110 CMPA #0x11003A DF9 JNZ -7

A = Address of F(0)B = F(0)=0X = F(1)=1 Store F(n)??Next addressLimit?Repeat


How is MOV R1,#0x100 executed ?

This slide has animations – see*.pptx ‐ not *.pdf

R1 000 R2 000 R3 000

R0 000

AR 000 SR 000

SP 000 PC 000

100 850 901

000 01C

851 88E 901 etc

001

002

003 004005006

etc

MemoryAddress Content

001

MOV R1,#0x100

MOVS [R1],#0

INC R1

MOVS [R1],#1

??? 101

???100

Registers

Fetch Decode

And Execute

01C100

002

ALU

VIP

Memory Interface

and Timing


Instructions in Group F1

VIP’s instructions are encoded in 3 groups. This is F1Bits 11 to 8 7 to 4 3 to 0Hex mnemonic destination source operation Flags affected0 MOV d s d ← s NZ1 AND d s d ← d .AND. s NZ2 OR d s d ← d .OR. s NZ3 EOR d s d ← d .EOR. s NZ4 ADD d s d ← d + s VNZC5 ADDC d s d ← d + s + carry VNZC6 SUB d s d ← d + (.NOT. s) + 1 VNZC7 CMP d s d + (.NOT. s) + 1 VNZC8 MOVS d 0 to 15 d ← n9 F2 Op1 s/d or n Op1 : 0 to 15 See F2 tableA F3 Op2 s/d or n Op2 : 0 to 15 See F3 tableB JMP = BRA ‐128 to +127 PC ← PC ± nC JEQ = JZ ‐128 to +127 If Z=1, PC ← PC ± nD JNE = JNZ ‐128 to +127 If Z=0, PC ← PC ± nE JHS = JC ‐128 to +127 If C=1, PC ← PC ± nF JLO = JNC ‐128 to +127 If C=0, PC ← PC ± n

See next slide


Status Register

VIP’s Status Register and Flags

SR bit NameState at Reset

Description

7 U * User flag

6 R 1 Reset occurred

5 M 0 Memory type: 0=Von‐Neumann and 1=Harvard,

4 IE 0 Interrupt Enable

3 V 0Set if sign of result is incorrect using 2’s complementFor addi on: if msb(s)=msb(d) and msb(result)≠msb(d)For subtrac on: if msb(s)≠msb(d) and msb(result)≠msb(d)

2 N 0 Corresponds to most significant bit of the result

1 Z 0 Set if result of an operation was zero, otherwise cleared

0 C 0 Set if carry out, otherwise cleared


Instructions in Group F2 ‐ but not all

VIP’s monadic operations ‐ Group F2 (=09xy)Bits x: 7 to 4 y: 3 to 0Hex mnemonic s/d/n operation Flags

0 INC d d ← d + 1 C1 DEC d d ← d + 0xFFF NZC2 ROR d Rotate d right : msb ← lsb; and C←lsb NZC3 ROL d Rotate d le : lsb ← msb; and C←msb NZC4 RRC d Rotate d right including carry NZC5 RLC d Rotate d left including carry NZC6 RAR d Rotate d ‘arithmetic’ right preserving msb NZC7 PRSG d Left shift lsb from EOR (bits 11,5,3,0) NZC8 INV d d ← .NOT. d NZ9 NEG d d ← (.NOT. d) + 1 NZCA DADD s AR ← AR + s + carry (3 BCD coded digits) ZCB UMUL s R1:R0 ← unsigned R0 mes unsigned s ZC TST s s + 0 NZD EXEC s Execute s as an instruction impliedE BCSR n, 0 to 15 SR (bits 3‐0) ← SR .AND. (.NOT. n) explicitF BSSR n, 0 to 15 SR (bits 3‐0) ← SR .OR. n explicit


Instructions in Group F3 ‐ but not all

Monadic operations and control ‐ Group F3 (=0Axy)

Bits x: 7 to 4 y: 3 to 0Hex mnemonic s/d/n operation Flags

0 PSH s SP ← SP‐1; (SP) ← s

1 POP d d ← (SP); SP ← SP+1 Explicit if d=SR.

4 CALL sSP ← SP‐1; (SP) ← Return AddressPC ← Effec ve address from s

5 RET n PC ← (SP)+n; SP ← SP+1

7 RCN nCount for next rotate instruction.if n=0 use bits 3:2:1:0 of AR

Semantics ?

8 JDAR n, ‐8 to +7 AR ← AR‐1, if AR != 0, PC ← PC ± n9 JPE n, ‐8 to +7 If parity of AR is even, PC ← PC ± n

D JLT n, ‐8 to +7 If N != V, PC ← PC ± nSigned < after CMP instruction

E JGT n, ‐8 to +7 If Z = 0 and N = V, PC ← PC ± n Signed >


Atomic operations

Protected instruction sequences• From interrupt requests and DMA using LOCK/ULCK

Adr Opcodes Mnemonic020 01C 100 MOV R1,#0x100 ; address022 02C 002 MOV R2,#0x002 ; flag024 A6A LOCK ; protect025 035 MOV R3,[R1] ; get flag026 252 OR [R1],R2 ; set flag027 A6B ULCK ; unlock028 132 AND R3,R2 ; test028 D?? JNZ label ; busy029 xxx ??? ; available


Other examples

Binary to BCD conversionConvert binary number in R0 to 4-digit BCD number in R3:R2 –R3 is most significant part. From 000:000 to 004:095A01 PSH R1 /* save R1 */830 MOVS R3,#0 /* initialize high */820 MOVS R2,#0 /* and low parts */81C MOVS R1,#12 /* 12 shifts */930 ROL R0082 MOV AR,R2 /* Decimal double */ 9A2 DADD R2 /* with carry in */028 MOV R2,AR /* and carry out */083 MOV AR,R3 /* repeated for */ 9A3 DADD R3 /* for high part */038 MOV R3,AR911 DEC R1 /* loop ? */DF7 JNE R1A11 POP R1 /* recover R1 */A50 RETRET


Other examples

Insertion sortuint12 index=R0,*pi=[R1],*pj=[R2],*pk=[R3]; /* Tested */pi=a; MOV R1,#startpk=a+n; MOV R3,#start+7while(pi++, pi!=pk){ m0: INC R1

CMP R1,R3JEQ m4

index = *pi; MOV R0,[R1]pj=pi; MOV R2,R1while(pj!=a && *(pj-1) > index){ m1: CMP R2,#start

JEQ m3CMP R0,[R2+0xFFF]JHS m3

*pj = *(pj-1); MOV [R2+0],[R2+0xFFF]pj--; DEC R2} JMP m1

*pj = index; m3: MOV [R2+0],R0} JMP m0return a[n>>1]; m4: MOV R0,[start+4]

} RET


VIPID Simulator – emulation of PRSG instruction

Simulator called VIPID : Courtesy School of Computer Engineering, Nanyang Technological University, Singapore


Thank you for your attention and interest

Any Questions?

Contact• Dr. David C. DyerSchool of EngineeringUniversity of Warwick, Coventry, CV4 7AL, United Kingdom

e‐mail• [email protected]

a novel 12-bit _isa_ for introducing novice students to instruction set

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