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A novel X-lling method for capture power reduction Heetae Kim, Hyunggoy Oh, Jaeil Lim, and Sungho Kang a) School of Electrical and Electronic Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul 120749, Korea a) [email protected] Abstract: This paper proposes a X-lling method that reduces capture power during scan-based testing. The proposed method classies scan cells for dividing the scan cells into some groups. Then, based on the divided groups, X-bits are lled simultaneously to reduce the computation time. Since the proposed method uses a novel grouping algorithm and lls X-bits based on groups, the proposed method reduces switching activity and computation time when compared with conventional X-lling methods. The simulation results show that the proposed method reduces the switching activity up to 70% and the number of simulations for the X-lling up to 52% compared with that of conventional X-lling methods. Keywords: X-lling, low power test, capture power reduction Classication: Integrated circuits References [1] T. Lee and J.-S. Yang: Physical-aware gating element insertion for thermal- safe scan shift operation,IEICE Electron. Express 14 (2017) 20161181 (DOI: 10.1587/elex.14.20161181). [2] M. M. Naeini and C. Y. Ooi: A novel scan architecture for low power scan- based testing,VLSI Des. 2015 (2015) 264071 (DOI: 10.1155/2015/264071). [3] D. Deng, et al.: A novel power-efcient IC test scheme,IEICE Electron. Express 14 (2017) 20170462 (DOI: 10.1587/elex.14.20170462). [4] S. Almukhaizim and O. Sinanoglu: Dynamic scan chain partitioning for reducing peak shift power during test,IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 28 (2009) 298 (DOI: 10.1109/TCAD.2008.2009159). [5] S. Kiamehr, et al.: A layout-aware x-lling approach for dynamic power supply noise reduction in at-speed scan testing,Proc. IEEE Eur. Test Symp. (2013) (DOI: 10.1109/ETS.2013.6569356). [6] M. Yoshimura, et al.: A dont care lling method to reduce capture power based on correlation of FF transitions,Proc. Asian Test Symp. (2015) 13 (DOI: 10.1109/ATS.2015.10). [7] X. Wen, et al.: A novel scheme to reduce power supply noise for high-quality at-speed scan testing,Proc. Int. Test Conf. (2007) (DOI: 10.1109/TEST.2007. 4437632). [8] S. Remersaro, et al.: Preferred ll: A scalable method to reduce capture power for scan based design,Proc. Int. Test Conf. (2006) (DOI: 10.1109/TEST.2006. 297694). [9] R. Sankaralingam and N. A. Touba: Controlling peak power during scan testing,Proc. IEEE VLSI Test Symp. (2002) 153 (DOI: 10.1109/VTS.2002. 1011127). © IEICE 2017 DOI: 10.1587/elex.14.20171093 Received November 1, 2017 Accepted November 10, 2017 Publicized November 27, 2017 Copyedited December 10, 2017 1 LETTER IEICE Electronics Express, Vol.14, No.23, 16

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Page 1: A novel X-filling method for capture power reductionsoc.yonsei.ac.kr › Abstract › International_journal › pdf › 150_A... · 2017-12-12 · A novel X-filling method for capture

A novel X-filling method forcapture power reduction

Heetae Kim, Hyunggoy Oh, Jaeil Lim, and Sungho Kanga)

School of Electrical and Electronic Engineering, Yonsei University,

50 Yonsei-ro, Seodaemun-gu, Seoul 120–749, Korea

a) [email protected]

Abstract: This paper proposes a X-filling method that reduces capture

power during scan-based testing. The proposed method classifies scan cells

for dividing the scan cells into some groups. Then, based on the divided

groups, X-bits are filled simultaneously to reduce the computation time.

Since the proposed method uses a novel grouping algorithm and fills X-bits

based on groups, the proposed method reduces switching activity and

computation time when compared with conventional X-filling methods.

The simulation results show that the proposed method reduces the switching

activity up to 70% and the number of simulations for the X-filling up to 52%

compared with that of conventional X-filling methods.

Keywords: X-filling, low power test, capture power reduction

Classification: Integrated circuits

References

[1] T. Lee and J.-S. Yang: “Physical-aware gating element insertion for thermal-safe scan shift operation,” IEICE Electron. Express 14 (2017) 20161181 (DOI:10.1587/elex.14.20161181).

[2] M. M. Naeini and C. Y. Ooi: “A novel scan architecture for low power scan-based testing,” VLSI Des. 2015 (2015) 264071 (DOI: 10.1155/2015/264071).

[3] D. Deng, et al.: “A novel power-efficient IC test scheme,” IEICE Electron.Express 14 (2017) 20170462 (DOI: 10.1587/elex.14.20170462).

[4] S. Almukhaizim and O. Sinanoglu: “Dynamic scan chain partitioning forreducing peak shift power during test,” IEEE Trans. Comput.-Aided DesignIntegr. Circuits Syst. 28 (2009) 298 (DOI: 10.1109/TCAD.2008.2009159).

[5] S. Kiamehr, et al.: “A layout-aware x-filling approach for dynamic powersupply noise reduction in at-speed scan testing,” Proc. IEEE Eur. Test Symp.(2013) (DOI: 10.1109/ETS.2013.6569356).

[6] M. Yoshimura, et al.: “A don’t care filling method to reduce capture powerbased on correlation of FF transitions,” Proc. Asian Test Symp. (2015) 13(DOI: 10.1109/ATS.2015.10).

[7] X. Wen, et al.: “A novel scheme to reduce power supply noise for high-qualityat-speed scan testing,” Proc. Int. Test Conf. (2007) (DOI: 10.1109/TEST.2007.4437632).

[8] S. Remersaro, et al.: “Preferred fill: A scalable method to reduce capture powerfor scan based design,” Proc. Int. Test Conf. (2006) (DOI: 10.1109/TEST.2006.297694).

[9] R. Sankaralingam and N. A. Touba: “Controlling peak power during scantesting,” Proc. IEEE VLSI Test Symp. (2002) 153 (DOI: 10.1109/VTS.2002.1011127).

© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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LETTER IEICE Electronics Express, Vol.14, No.23, 1–6

Page 2: A novel X-filling method for capture power reductionsoc.yonsei.ac.kr › Abstract › International_journal › pdf › 150_A... · 2017-12-12 · A novel X-filling method for capture

[10] P. Sismanoglou and D. Nikolos: “Low capture power dictionary-based test datacompression,” Proc. IEEE Int. Symp. Quality Electron. Des. (2016) 289 (DOI:10.1109/ISQED.2016.7479216).

1 Introduction

The growing complexity of very large scale integrated circuits demands difficult

constraints for timing defects and increases the power density. High power

dissipation can cause IR drops and additional timing failures. The effect of IR

drops is particularly problematic at near-threshold voltage condition which de-

creases the supply voltage to about the threshold voltage for the sake of energy

efficiency. Test operations consume more power than normal operations because

test patterns make large transitions in circuits under testing [1, 2, 3]. Timing failures

that don’t occur in normal operations can be generated by these test operations and

these make the overkill problem [4, 5]. For this reason, research on the reduction of

peak power during testing is required.

In a scan-based testing process, peak power consumption occurs in the launch-

on-capture cycle and the power consumption in the launch-on-capture cycle called

capture power. This paper proposes a X-filling method to reduce the capture power.

Several X-filling methods have been studied to reduce capture power by controlling

X-bits [6, 7, 8, 9, 10]. Justification based X-filling methods were proposed in [6, 7].

Although the methods find the exact solution by pattern justification, complex gate

level analysis is required for each pattern. Probability based method was proposed

in [8]. It calculates the probability to take 0 or 1, and fills X-bits with a value which

has the higher probability. However, to calculate the probability, the accurate

structure of the circuit under test is needed. Therefore, [6, 7, 8] cannot be applied

to circuits of which the exact structures are unknown [7].

In order to apply X-filling to the circuits of which structure are unknown,

X-filling methods which fill the X-bits randomly were proposed in [9, 10]. They fill

X-bits with random value until the test pattern has minimum Hamming distance

between its stimulus and response. One of the conventional X-filling methods is

single-bit correction (SBC) [9] which controls X-bits one by one. Because test

patterns have numerous X-bits, they have a long computation time. For reducing

the computation time, a multi-bit correction method called MBC that divides scan

cells into groups of constant size and controls X-bits in a group simultaneously has

been proposed [10]. However, due to the reduced search space, the patterns have

higher capture power than SBC. In order to overcome the computation time and

peak power consumption, a new X-filling method is proposed which is based on a

new group based multi bit correction.

2 Group-based multi-bit correction method

The motivation of proposed method is shown in Fig. 1. SA (Switching Activity)

shown in in Fig. 1 refers Hamming distance between the test pattern and the test

response, and it means how much capture power is consumed. The test vector© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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X1XX01 has three X-bits, and there are eight cases of assignment using SBC.

SBC searches all cases of assignment and test pattern 11101 is found as the solution

that has the minimum switching activity. Since MBC uses same size groups for

X-filling, MBC shown in Fig. 1 divides the six bits of the input vector into two

groups; one group consists of the first to third bits (X1X), whereas the other

contains the fourth to sixth bits (X01). Then MBC fills the X bits in a group to

corresponding bits of an adjacent filling or the opposite value of the adjacent filling

simultaneously; for instance, the first group, X1X, can either be filled to 110 or 011.

MBC reduces the search space from eight to four, but it cannot search the case

111101. To solve the problem by reduced search space, a new X-filling method

called group-based multi-bit correction (GMBC) is proposed. In this example,

GMBC divides only X-bits into two groups; one consists of the first and second

X-bits and the other consists of the third X-bit. Since GBMC has two groups as

same as MBC, GMBC also has four search space. However, GMBC can find the

solution 111101 that has smaller switching activity than the solution of MBC.

To get a better solution, an appropriate grouping is needed for a test pattern as

shown in Fig. 1. Since X-filling deals with only X-bits, care bits in a group are

redundant. For instance, the second bit of MBC group (X1X) is redundant because

it is always constant 1 for all cases. A scan cell can be classified into four types

which are denoted as A, B, C, and D in Table I. Since only test patterns of types A

and B are X-bits, a group consists of only types A and B. For the appropriate

Fig. 1. An example of SBC, MBC and GMBC.

Table I. The classification of cell types.

Cell type Test pattern ResponseResponse byadjacent filling

AA1 X 0/1 Match

A2 X 0/1 Conflict

BB1 X X Match

B2 X X Conflict

C 0/1 X X/0/1

D 0/1 0/1 0/1

© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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grouping, GMBC sub-divides types A and B as the patterns filled by the adjacent

filling and the expected responses of the adjacent filling. When the test pattern filled

by the adjacent filling is matched by the expected response of the pattern, the type

of the cell is classified as type 1. On the other hand, when the two bits conflict with

each other, then the cell is classified as type 2.

If a cell that is type A1 or B1 and another cell that is type A2 or B2 are in the

same group, then one of them must come into conflict. Therefore, type 1 and type 2

should be separated. Fig. 2 depicts a pseudo code for a grouping algorithm of

GMBC. When the size of the current group matches that of the maximum group,

or a current cell comes into conflict with the group, then a new group is generated

and the current cell is contained within the group.

Fig. 3 depicts an example of the classification of cell types and grouping

process. First, a classification using a test vector and its response vector is

conducted. The first, fourth, and eighth cells are type A, and the third, fifth, and

Fig. 2. A Pseudo code of grouping algorithm.

Fig. 3. An example of the cell type classification and grouping.

© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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ninth cells are type B. After this, a subdivision is performed with the test pattern

filled adjacent filling and its response pattern. In this step, an additional simulation

is needed for obtaining the expected response of the adjacent filling. Since the

values of the first and fourth cells with adjacent filling are 1 and 0, and the values of

their response vector are 0 and 1, respectively, conflicts are generated and the first

and fourth cells are classified as type A2. However, since the value of the eighth

cell in the adjacent filling is matched by the value of its response, the type of the

eighth cell is decided as A1. In the same way, B type cells are divided into types B1

or B2. There are six cells that have X-bit as the test pattern; the first, third, fourth,

fifth, eighth and ninth cells. At the beginning of grouping, since a group 1 which

denoted as G1 in Fig. 3 is empty, the first cell is included in G1. After that, because

the third cell which is the next X-bit cell conflicts with the first cell, a new

group G2 is generated and includes the third cell. The fourth cell conflicts with the

third cell but is compatible with the fifth cell. Therefore, a third group G3 consists

of the fourth and fifth cells. The eighth cell is also not compatible with the fifth cell,

but is compatible with the ninth cell. Consequently, the eighth and ninth cells are

included in G4 and grouping algorithm is terminated.

3 Simulation and discussions

A simulation was performed to compare the number of logic simulations and the

switching activity. ISCAS 89 circuits were used for circuit under test and Design

Compiler, TetraMax and Synopsys 32 nm library were used to implement the

simulation. Since test patterns of ISCAS 89 circuits are deterministic patterns,

they have more than 90% of X-bits.

The simulation compared three methods; SBC [9], MBC [10] and GMBC.

Table II compares the number of logic simulations and SA of the three methods

with the maximum group size 20. GMBC reduces the number of logic simulations

by an average of 39.7% and 0.8% when compared with SBC and MBC, respec-

tively. Since both MBC and GMBC reduce the search space, the number of

simulations of GMBC is not much different from that of MBC. However, GMBC

achieves a 58.2% reduction of switching activity on an average when compared

with MBC.

Table II. The number of simulations and switching activity.

Maximumgroup size 20

CircuitNumber oftest patterns

SBC [9] MBC [10] GMBC

S15850 3,509 30,980 14,829 14,858

Number of S35932 8,449 98,729 66,712 66,709

simulations S38417 8,251 36,862 21,564 20,874

S38584 11,279 106,993 74,071 74,025

S15850 3,509 2,760 8,111 2,760

SAS35932 8,449 4,544 15,014 4,544

S38417 8,251 10,433 21,045 10,433

S38584 11,279 9,038 16,979 9,038© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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Since GMBC divides the conflicting cells into different groups, it can reduce

the switching activity as much as that of SBC. From these results, the proposed

method achieved the advantages of SBC and MBC.

Table III shows comparisons the results of s15850 circuit for different max-

imum group sizes. Because SBC doesn’t use grouping, the results of SBC in

Table III are same. As the maximum group size increases, the number of groups

decreases and the effect of reducing search space increases. Therefore, the number

of simulations of MBC and that of GMBC are reduced as the maximum group size

increases. Since the large size of group has the large probability of containing

conflict cells, MBC has performance degradation as the maximum group size

increases. However, since GMBC considers conflicted cells and separates them, the

performance of GMBC is affected negligibly by the maximum group size.

4 Conclusion

GMBC is proposed to reduce capture power during scan-based testing. GMBC

divides scan cells into some groups by using cell type classification to avoid

formation of conflict cases. Our proposed X-filling method reduces switching

activity as much as SBC with a similar computation time to MBC.

Acknowledgments

This work was supported by the IT R&D program of MOTIE/KEIT. [10052716,

Design technology development of ultra-low voltage operating circuit and IP for

smart sensor SoC].

Table III. Comparison according to various maximum group sizes.

S15850Maximumgroup sizes

SBC [9] MBC [10] GMBC

5 30,980 23,383 23,760

Number of 10 30,980 18,639 18,486

simulations 15 30,980 16,275 16,152

20 30,980 14,829 14,858

5 2,760 3,270 2,760

SA10 2,760 4,964 2,760

15 2,760 6,379 2,760

20 2,760 8,111 2,760

© IEICE 2017DOI: 10.1587/elex.14.20171093Received November 1, 2017Accepted November 10, 2017Publicized November 27, 2017Copyedited December 10, 2017

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