A Quad-Channel 3.125Gb/s/ch Serial-Link Transceiver with Mixed-Mode

Adaptive Equalizer in 0.18µm CMOS

Authors :Jeongsik Yang, Jinwook Kim, Sangjin Byun, Cormac Conroy,Beomsup Kim

Provided By: SAEID MEHRMSNEDH

Outline

Why serial link? Transceiver Architecture Current Mode Logic Multiplexer Equalization Data recovery Conclusion

Why serial link?

Less Complexity Using Fully Differential Signaling Digital Data as an analog signal Equalization Methods Data recovery Asynchrony

Transceiver Architecture

Current Mode Logic•More Speed

•Noise Immunity

•No bad effect on supply

•Constant current

•High Power consumption

Input Multiplexer

Why Equalization?

Bandwidths Limitation of channel Channel Distortion If channel transfer function is

H(S) we can add H-1(S) in signal path

Avoiding inter symbol interference

Equalizer Circuits Equalization at Receiver Lower power

consummation Adaptive methods (LMS) Farjadrad methods

Clock Data Recovery

CDR Result

Results

Conclusion

Better Input multiplexer Input Equalization Delay Immune CDR

Achieving good power consumption characteristic (.18 W per channel)