a reverse engineering approach to generate a virtual plant model for plc simulation

ORIGINAL ARTICLE

A reverse engineering approach to generate a virtual plantmodel for PLC simulation

Sang C. Park & Minsuk Ko & Minho Chang

Received: 2 December 2012 /Accepted: 18 July 2013 /Published online: 7 August 2013# Springer-Verlag London 2013

Abstract A reverse engineering approach to generate a vir-tual plant model is proposed. The model can be used forprogrammable logical controller (PLC) simulation. The virtu-al plant model for the PLC simulation consists of virtualdevice models and must interact with the input and outputsignals of a PLC. The behavior of a virtual device modelshould be the same as that of real device. Conventionally,the discrete event system specifications (DEVS) formalismhas been used to represent the behavior of a virtual devicemodel. Modeling using DEVS formalism, however, requiresin-depth knowledge of the simulation area, as well as a sig-nificant amount of time and effort. One of the key ideas of theproposed methodology is to provide a method to generate avirtual plant model using both log data (time-stamped signalhistory) and a PLC I/O signal table extracted from the existingproduction system. The proposed reverse engineering ap-proach provides two major benefits: (1) significant reductionin the time and effort for the construction of a reliable virtualplant model of a current production system, which can bereferenced for newly planned production systems, and (2)reduction in the stabilization time of a production systemthrough PLC simulation. The proposed approach wasimplemented and applied to an automated production line.

Keywords Virtual plant model . Virtual devicemodel .

DEVS . PLC simulation

1 Introduction

In the manufacturing industry, there are various concepts andsolutions used to reduce the time and costs of product devel-opment [1]. In the “production ramp-up” trend in the automo-tive industry, a general paradigm shift from cost to timemanagement can be found [2]. Recently, in order to respondto demands including high productivity and production flex-ibility, the use of the concept of virtual commissioning (VC)has beenwidely accepted [3–5]. In the past, VCwas applied tosmall-size (cell) manufacturing system. However, due to therecent development in computer technology, it is possible toapply VC technology (VCT) to a large-scale manufacturingsystem (lines and factories). As a part of this shift, offlineprogramming for robots and verification of control programs[6–8] along with virtual device models have emerged invarious industries.

Generally, a modern production line is a highly integratedsystem composed of automated workstations such as robots,fixtures, conveyors, and so on. These are usually controlled byprogrammable logical controller (PLC) programs for the shopflow. However, since conventional simulation languages, in-cluding ARENA® and AutoMod®, roughly describe the con-trol logic with independent entity flows between processes,their simulation models are not suitable for utilization indetailed design or for implementation purposes. To success-fully achieve the implementation of the production line at thecontrol level (sensors and actuators), PLC simulation has beenwidely accepted both in industry and in academia. PLC sim-ulation for VC is considered to be an essential tool in thedesign and analysis of complex control systems that cannot beeasily described by analytical or mathematical models. It isuseful for analyzing the control logic in various ways andrecognizes hidden errors more intuitively.

Figure 1 shows the procedure for running the PLC simula-tion for the production line. There are two major design activ-ities: mechanical design and electrical design. The mechanical

S. C. Park :M. KoDepartment of Industrial Engineering, Ajou University, San 5,Woncheon-dong, Yeongtong-gu, Suwon, South Korea

M. Chang (*)Department of Mechanical Engineering, Korea University,Anam-Dong, Seongbuk-Gu, Seoul 136-701, South Koreae-mail: [email protected]

Int J Adv Manuf Technol (2013) 69:2459–2469DOI 10.1007/s00170-013-5209-1

design phase produces a physical model which includes thehardware configurations of a production system, whereas theelectrical design phase describes the ‘control program’ of thesystem as a logical model (discrete event model). Usually,electrical design involves PLCs, which are currently a basicand universal tool for the automation of manufacturing pro-cesses. Traditionally, the development of PLC-controlled appli-cations, mechanical design, and electrical design have beenperformed sequentially [8], and partly online. So, before acontrol engineer can proceed with programming, verification,and optimization of the control code, the mechanical workmustfirst be completed. This manufacturing process is inefficientand it increases the time required for a product to reach themarket. So, many manufacturing companies have adoptedmore attractive methods for totally offline PLC simulation, inwhich both the mechanical and the control engineers worksimultaneously.

As shown in Fig. 1, to construct a PLC simulation envi-ronment, it is necessary to build a corresponding virtual plantmodel (the counterpart system) required to interact with theinput and output of the PLC. The behavior of the plant modelshould be the same as that of the actual production line toachieve PLC verification. Since a production line consists ofvarious devices, we can consider a plant model as a set ofvirtual device models.

Previous approaches to PLC simulation can be categorizedinto three groups: (1) framework for the PLC simulation, (2)verification of a given PLC program, and (3) automatic gen-eration of a PLC program. In the first group, several haveproposed a PLC simulation framework for the verification ofthe control logic with commercial software. Some of theresearchers have proposed the architecture of a PLC programenvironment [9–12]. This environment enables visual verifi-cation of the PLC program integrated into a PLC with corre-sponding virtual plant models. This approach mainly focuseson the development of the theoretical background, whichindicates how to construct the PLC simulation environment.In the second group, various software tools have been devel-oped for the verification of PLC-based systems by using timedautomata, such as UPPAAL2k, KRONOS, Supermia, andHyTech. Moreover, this type of approach is mainly for pro-grams that are written in a state list language, which are alsoreferred to as “Boolean.” As they mainly focus on checkingthe theoretical attributes (safety, liveness, and reachability), itis not easy for users to determine whether or not the PLCprograms actually achieve the intended control objectives[13–15]. In the third group, many researchers have focusedon the automatic generation of PLC programs from variousformalisms, and this includes state diagrams, Petri nets, andIDEF0 [16–20]. These formalisms can help the design processof the control logic, but it is still difficult to determine thehidden errors, which is the most difficult part of verifying acontrol program. Considerable work has been undertaken inthe field of PLC simulation and validation for a long period oftime, but limitations remain in efficiently constructing adjust-ed simulation models.

In order to overcome the aforementioned problems, it isnecessary to utilize simulation techniques for PLC simulation.Although PLC simulation can be a very powerful method forthe detailed verification of a production system, the accompa-nying construction of a virtual plant model, which is a set ofvirtual device models, is a major obstacle. As PLC programscontain only the control information, without device models, itis necessary to build a corresponding virtual plant model toperform simulation, as shown in Fig. 1. However, constructinga virtual plant model requires an excessive amount of time andeffort. Sometimes, the virtual plant model construction requiresmore time compared to the PLC programming. This serves asthe motivation for exploring the possibility of finding anefficient method for the generation of a virtual plant model inthe reverse engineering approach.

The objective of this paper is to develop an efficient meth-od for the construction of the model for PLC simulation,which is able to generate a virtual plant model of the produc-tion system automatically. The proposed method employs areverse engineering approach to extract general log data fromthe existing production system, which is described at the levelof sensors and actuators. The method can reduce the time and

Plant simulation

Mechanical Design & simulation

Virtual Plant

Physical model(3D Model with kinematics)

Logical Model(Discrete Event Model)

Virtual device model(Physical + Logical)

Control logic design

PLC programming

Electrical design

PLC PLC program

Real controller

PLCOutput Symbols

(to actuators)

PLCInput Symbols(from sensors)

PLC Simulation

Fig. 1 Virtual commissioning for a manufacturing system (PLCsimulation)

2460 Int J Adv Manuf Technol (2013) 69:2459–2469

effort required to construct a virtual plant model for PLCsimulation. Traditionally, research on virtual engineering hasfocused on the forward engineering approach, which is thetraditional process of moving from high-level abstractions andlogical designs to physical implementation of a system [20].In contrast, the proposed reverse engineering approach forPLC simulation is defined as a process of obtaining physicalor logical implementation data from PLC log data acquired bydigitizing an existing production system. This approach canreduce the construction time and effort required to obtain avirtual plant model of a newly planned production system thatreferences an existing production system and uses it to analyzethe process of a production system at the control (sensor andactuator) level.

The overall structure of the paper is as follows. Section 2presents the overall approach to the automatic generation of avirtual plant model of a production system using reverseengineering, while Section 3 details an algorithm of the pro-posed method. Section 4 shows an example and illustrations.Finally, concluding remarks are given in Section 5.

2 A reverse engineering approach for PLC simulation

Various machines that operate simultaneously in a productionline are usually controlled by PLCs, which is currently themost suitable and widely employed industrial control technol-ogy [12, 18, 19, 21]. A PLC emulates the behavior of anelectric ladder diagram. PLCs use an input/output signal tableand a scanning cycle, as they are sequential machines, toemulate the working of parallel circuits that respond instanta-neously. When a program is run on a PLC, it continuouslyexecutes a scan cycle. The program scan solves the Booleanlogic related to the information in the input table with that inthe output and internal relay tables. In addition, the informa-tion in the output and internal relay tables is updated duringthe program scan. In a PLC, this Boolean logic is typicallyrepresented using a graphical language, known as a ladderdiagram [22].

As depicted above, to implement a VC-based PLC simu-lation model, it is necessary to construct a virtual plant modelfor all behaviors of a real production system. In a conventionalimplementation procedure of the virtual plant model, theanalyzing and modeling phases are performed sequentially,as shown in Fig. 2. In the analyzing phase, a set of tasks thatare assigned to the device can be identified, after which a pairof PLC I/O signals (input and output) can be allocated for eachtask. The activation of each task is normally triggered by anexternal signal from the PLC program. Once both the set oftasks and PLC I/O signals are defined for the device, it ispossible to extract the state transition diagram, which definesan atomic model of the discrete event systems specifications(DEVS) formalism [21, 23]. The semantics of the formalism

are highly compatible with object-oriented specifications forsimulation models. A brief explanation is given below.Withinthe DEVS formalism, an atomic model M is specified by aseven-tuple:

M ¼ ⟨X ; S; Y ; δint; δext;λ; ta⟩

X Input events setS Sequential states setY Output events setδint S→S: internal transition functionδext Q*X→S: external transition

functionQ={(s,e)| s ∈ S 0≤e≤ta(s)}

Total state ofM

λ S→Y: Output functionta S→Real: time advance function.

The atomic model consists of three sets and four functions.The four functions in the seven-tuple, namely δint, δext, λ, andta, are called the characteristic functions of an atomic model.The atomic model of the DEVS formalism can be consideredas a timed finite-state automata (FSA), and it is suitable fordescribing the behaviors of a device model.

Figure 3 shows a simple example of an automatic-guidedvehicle (AGV) with two tasks, task 1(movement from p1 top2) and task 2(movement from p2 to p1). As the two tasksshould be triggered by external events, the virtual devicemodel of the AGV must have two input ports, referred to hereasX1 and X2which are connected with the PLC output signalsO_X1 andO_X2. For this example, there are four states: S_P2,DO_TASK1, S_P1, and DO_TASK2. While S_P2 and S_P1

Task List

Identify tasks

I/O signals

Virtual Device Model

Virtual Plant Model

PLC Simulation

Implementation

Ana

lyzi

ng P

hase

Mod

elin

g P

hase

A Task

For

war

d E

ngin

eeri

ng A

ppro

ach

Fig. 2 An implementation procedure of a virtual plant model

Int J Adv Manuf Technol (2013) 69:2459–2469 2461

take external events from the input ports for state transitions,DO_TAKS1 and DO_TASK2 take internal events that are theend events of the two tasks. When the internal transitionoccurs from either DO_TAKS1 or DO_TAKS2, the outputfunction sends a signal to the output ports (Y1 or Y2) that areconnected to the PLC input signal (I_X1 or I_X2). Once thevirtual device models are constructed, the virtual plant modelcan be defined by combining a set of virtual device models.Then, the constructed virtual plant model can be used for PLCsimulation to fix various errors that are not properly adjustedcaused by control programming, as well as faults in the controlprograms. We can minimize the stabilization time after theactual implementation, since most errors are fixed through thePLC simulation. Since the virtual device model should beconstructed manually in the modeling phase, much effortand in-depth knowledge of the simulation is necessary in thisphase, which is a main cause of delays in the PLC simulation.

We propose an automated generation method of the virtualplant model by a reverse engineering approach for the PLCsimulation, as shown in Fig. 4, to cope with the problem. Weseparated the proposed implementation procedure into twophases, production system data collection phase, and an auto-mated generation phase. In the data collection phase, we caneasily obtain both log data (time-stamped signal history) and anI/O signal table from the existing production system. Then, wecan simply construct a set of virtual device models automati-cally by the proposed generating algorithm. Since the obtained

p1 p2Task1: move from p1 to p2

Task2: move from p2 to p1Sensor S2Sensor S1

Task ListTask1: move from p1 to p2 Task2: move from p2 to p1

Device Signal Address Description

AGV O_T1 O1 Execute “Task1”

AGV I_T1 X1 Arrived at the Position “P2”

AGV O_T2 O2 Execute “Task2”

AGV I_T2 X2 Arrived at the Position “P1”

I/O Signal table for an AGV

I_X1

I_X2

O_X1

S_P1 S_P2

DO_TASK2

DO_TASK1

X1

X2

Y1

Y2O_X2

Virtual Device ModelI_X2 O_X1I_X1

I_X2 O_X2I_X1

Ο

Ο

Input

Output

M = < X, S, Y, δint, δext, λ, ta>X:{ X1, X2}; S:{ S_P1*, DO_TASK1, S_P2, DO_TASK2 } Y:{ Y1, Y2};δ int (DO_TASK1) = S_P2; δ int (DO_TASK2) = S_P1δ ext (S_P1, X1 ) = DO_TASK11; δ ext (S_P2, X2) = DO_TASK2λ (DO_TASK1) = Y1; λ (DO_TASK2) = Y2ta(S_P1)=∞; ta(DO_TASK11)= T1 ; ta(S_P2)=∞; ta(DO_TASK2)= T2

PLC Program

Fig. 3 An implementationprocedure of a virtual devicemodel (AGV)

PLC PLC program

Real controller

Log data I/O table

Virtual Device Model

Virtual Plant Model

PLC Simulation

Aut

omat

ed g

ener

atio

nC

olle

ctin

g da

ta

Implem

entationRev

erse

Eng

inee

ring

App

roac

h

Production System

Input signal Output signal

Fig. 4 A reverse engineering approach to construct a virtual plant model


log data contains signals with the stamped time that indicatewhen the signal was turned on and off, we can define asequence of signals and the duration for each signal. The I/Osignal table identifies an input signal set and an output signal setinvolved in a device. Since both data are obtained from theexisting production system in the reverse engineering approach,we can construct a reliable plant model for the PLC simulation.

To obtain a proper algorithm, it is necessary to focus on theinherent attributes of a device in an automated manufacturingsystem, considering that: (1) each device has a set of repetitivetasks; (2) a task is triggered by an output signal of a PLC; (3) adevice performs tasks one at a time; (4) the completion of a taskis notified through an input signal of a PLC; and (5) a work cellcan start its work cycle by the ‘WORK_CELL_RESET’ signalindicating all devices have completed assigned tasks.

From the inherent attributes of a device model, we canintuitively recognize that a task of a device has two relatedPLC signals, an output signal and an input signal. Triggering atask is done by an output signal of a PLC and the completion ofthe task is notified through an input signal of a PLC. Since thetime value can be used for interacting with another device, it isnecessary to define the time duration (ta) for each task. Forexample, consider the AGV model shown in Fig. 3. The AGVmodel has two tasks, T1 and T2. To execute each task, it isnecessary to define the duration time at DO_TASK1 (orDO_TASK2) for T1 (or T2), after which an output functionmakes an output signal Y1 (or Y2). At the same time, an internaltransition is executed to transit to the next state. However, bothS_P1 and S_P2 cannot escape the state without an externalsignal trigger.

The log data and I/O signal table are obtained from theexisting production system, and the generating phase isperformed automatically, as shown in Fig. 4. Thus, we canconstruct a reliable virtual plant model, and in-depthknowledge of the simulation is not required. The key ideaof this paper is to generate the full behavior model of adevice from the information of the existing productionsystem. As a result, a virtual plant model for the PLCsimulation can be easily constructed. An algorithm togenerate a virtual device model (atomic model) from thelog data and I/O signal table is addressed in the followingsection.

3 Virtual device model generation

This section presents an algorithm to generate a virtual devicemodel for the PLC simulation. One of the key ideas in theproposed algorithm is to utilize the concept of reverse engi-neering. Reverse engineering is the process of discovering thetechnological principles of a device, object, or system throughanalysis of its structure, function, and operation. As men-tioned already, in the data collection phase, we can obtain

the log data and I/O signal table easily from an existingproduction system. Then, a virtual device model can be gen-erated by the proposed algorithm automatically in the gen-eration phase. Since the proposed method discovers thedevice behavior model as a virtual device model usingthe collected data, we can consider the generated modelsas reliable models for the PLC simulation. To do so, it isnecessary to go through two important steps: (1) identifi-cation of a set of device I/O signal pairs from the timesignal chart of the log data, denoted as SIGNAL; and (2)generation of a virtual device model.

For the first step, we extract a set of input and output signals ofthe device from SIGNAL based on the ‘WORK_CELL_RESET’signal. Asmentioned, the ‘WORK_CELL_RESET’ signal plays arole in indicating that all devices have completed assigned tasks,as well as informing that a new work cycle will be started.Formally, the I/O signal table (a set of input signals and outputsignals) involved in a device is described as:

DEVICE_IO {DEV_I, DEV_O} // I/O signals of a device// DEV_I A set of device input signals used for

notifying device states.// DEV_O A set of device output signals used for

executing device tasks.

Then, we have to sort two sets,DEV_I andDEV_O, by thetime of occurrence. Since we extract signal sets by cuttingSIGNAL based on the WORK_CELL_RESET signal, DEV_IandDEV_O are non-redundant signals involved in the device.Once the sorted DEVICE_IO is obtained, it is possible toidentify two signal sets I and O.

// I is a set of sorted input signals of a device. I={I1, I2 …Ip}, p is the number of input signals of the device.

//O

is a set of sorted output signals of a device. O={O1, O2

… Oi}, i is the number of output signals of a device.

Then, we have to find an input signal In of the device thatflickers on and off betweenOn andOn+1. Once an input signalIn is found, we can make a set of I/O signal pairs IO_PAIR (In,On), as shown in Fig. 5.

DEVICE IO PAIR ¼ IO PAIR1; IO PAIR2…IO PAIRif g;

The second step is generating a virtual device model (atom-ic model) with the identified device I/O signal pair set. Thevirtual device model generation algorithm is as follows:

& Generation of a virtual device model from an identifieddevice I/O signal pair set

// Input an identified device I/O signal pair set,DEVICE_IO_PAIR

//Output

an atomic model of the device,M=⟨X,S,Y,δint,δext,λ,ta⟩

// i is the number of I/O signal pairs


Step 1. Input event set: Define an external event for each pair

X ¼ O1;O2…Oif g:

Step 2. Sequential state set: Define two states for each pair‘READY_On’ and ‘DO_On’. While ‘READY_On’indicates both the device is waiting for a triggeringevent (Xn) and the completion of a post event (Xn-1),‘DO_On’ means the execution of the task triggeredby Xn from the controller.

S ¼ fREADY O1;DO O1;READY O2;DO O2…

READY Oi;DO Oig;

Step 3. Output event set: Define an output event for eachpair to notify the controller of the end of the task.

Y ¼ I1; I2…I if g:

Step 4. Internal transition functions: Define an internal tran-sition function for each pair.

δint DO Onð Þ ¼ READY Onþ1;

If On is the last output signal of the device, the followinginternal transition function must be defined.

δint DO Onð Þ ¼ READY O1;

Step 5. External transition functions: Define an externaltransition function for each pair.

SIGNAL

WORK_CELL_RESET

On

In

On+1

In+1

Work cycle

IO_PAIRn

IO_PAIRn+1

Time

SignalsFig. 5 A device I/O signal table

O1

O2

I1

I2

Oi Ii

READY_O1 DO_O1 READY_O2

DO_O2

READY_O3

DO_Oi

READY_Oi DO_Oi-1

O2 Ii-1

READY_On READY_On+1

DO_On

δ ext(READY_On, On) = DO_On

t a (READY_On ) = ∞δ int( DO_On ) = READY_On+1

λ(DO_On) = In

t a (DO_On ) = t n

On In

..…

Fig. 6 A virtual device modelexpressed by the state diagram


δext READY On;X nð Þ ¼ DO On;

Step 6. Output functions: Define an output function for eachpair.

λ DO Onð Þ ¼ Yn;Step 7. Time advance functions: Define a time advance

function for every state. The duration for a‘READY_On’ becomes infinite (∞), because it

cannot escape the state without an external trigger.However, the duration for a ‘DO_On’ can beobtained from the difference between the start timeof Xn and the end time of Yn.

ta READY Onð Þ ¼ ∞;

ta DO Onð Þ ¼ △tn ¼ End time of theYn–Start time ofX n

It is possible to generate a virtual devicemodel from the I/Osignal pair set of a device. As shown in Fig. 6, since the

Welding Robot (WR)

Handling Robot (HR)

Idle jig for Output Part

(IOP)

Idle jig forInput Part

(IIP)

Idle jig for Working Part

(IWP)

X

Y

XZ

Y

XZ

Y

Fig. 7 A robot cell

(a) Work cell initialized (b) IIP Loads a part (c) H-Robot move a part to IWP

(d) W-Robot welds a part(e) H-Robot move a part to IOP(f) IOP Loads a part

Fig. 8 Awork cycle for the robotcell


generation algorithm is described as a general term (n), itshould be applied to multiple times (i). The three sets of anatomic model can be intuitively extracted (steps 1, 2, and 3)from the input (I) and output (O) signals. In the case of thefour functions of an atomic model, they are extracted (steps 4–6) from the signals of the log data. In this way, we caneffectively construct a precise virtual plant model which issuitable for the virtual commissioning of a PLC.

4 Example and illustrations

The prototype of the proposed algorithm has been imple-mented and tested with several examples. The C++ languagein a Visual Studio environment was used, with OpenGL forthe graphical rendering. The robotic cell shown in Fig. 7consists of an input station (IIP: Idle jig for an input part), aworking station (IWP: Idle jig for a working part), an outputstation (IOP: Idle jig for an output part), a handling robot(HR), and a working robot (WR). As shown in Fig. 8, ifa part arrives at the input station (IIP), the handling robot(HR) moves the part to the working station (IWP). Afterwelding of the part by the welding robot (WR), the han-dling robot moves the part from the working station to theoutput station (IOP).

As shown in Table 1, we can obtain an I/O signaltable from the PLC program of the current robot cell.This table and the log data of the cell are obtained fromthe work cell, as shown in Fig. 9. The table in Fig. 9shows the start and end time of the signal, and averageduration of each signal. As shown in Fig. 9 with Table 1,we can identify two I/O signal pairs of the handlingrobot: IO_PAIR1=(O_Y1C, I_X1C): moving a part fromIIP to IWP, IO_PAIR2=(O_Y1D, I_X1D): moving a partfrom IWP to IOP. For each I/O signal pair IO_PAIRn,we can define the execution sequence of tasks. By usingthe time sequence chart of the log data, I/O signal table,and the proposed generation algorithm, a virtual devicemodel of the handling robot can be generated asfollows:

Virtual device model of the robot: M=⟨X,S,Y,δint,δext,λ,ta⟩

X {O_Y1C, O_Y1D}S {READY_Y1C, DO_Y1C, READY_Y1D,

DO_Y1D}Y {I_X1C, I_X1D}

SIGNALCYCLE 1 CYCLE 2 CYCLE 3 AVG

( t)TSTART TEND TSTART TEND TSTART TEND

Y1C 14.3 16.5 48.4 50.6 82.5 84.72.73

X1C 17.03 35.16 51.13 69.26 84.3 102.43

Y1D 30.8 33 64.9 67.1 99 100.22.63

X1D 34.1 44 67.2 78 101.3 112.3

Y10 11 14.3 45.1 48.4 78.2 81.53.3

X10 14.3 14.3 48.4 48.4 81.5 81.5

Fig. 9 Log data for the robot cell

Table 1 I/O signal table for the robot cell

Device Symbol Address Description

CELL I_X0 X0 [Work cell initialize] done

O_X0 O0 Work cell initialize all devices

IIP I_X10 X10 [IIP Loads A Part] done

I_X11 X11 [iip unloads a part] done

O_Y10 Y10 IIP Loads A Part

O_Y11 Y11 IIP Unloads A Part

IWP I_X14 X14 [IWP Loads A Part] done

I_X15 X15 [IWP Unloads A Part] done

O_Y14 Y14 IWP Loads A Part

O_Y15 Y15 IWP Unloads A Part

IOP I_X18 X18 [IOP Loads A Part] done

I_X19 X19 [IOP Unloads A Part] done

O_Y18 Y18 IOP Loads A Part

O_Y19 Y19 IOP Unloads A Part

H-Robot I_X1C X1C [H-Robot Task1] done

I_X1D X1D [H-Robot Task2] done

O_Y1C Y1C H-Robot Do Task1 (Moves a partfrom IIP to IWP)

O_Y1D Y1D H-Robot Do Task2 (Moves a partfrom IWP to IOP)

W-Robot I_X21 X21 [W-Robot Task1] done (Welds apart at IWP)

O_Y21 Y21 W-Robot Do Task1


δint ( DO_Y1C) READY_Y1Dδint (DO_Y1D) READY_Y1Cδext(READY_Y1C

O_Y1C), DO_Y1C

δext(READY_Y1D

O_Y1D), DO_Y1D

λ (DO_Y1C) I_X1Cλ (DO_Y1D) I_X1Dta (DO_Y1C) 2.73 (sec)ta (DO_Y1D) 2.63 (sec)ta(READY_Y1C)

∞

ta(READY_Y1D)

∞

In this way, we can extract atomic models (behavior-al models) of virtual devices. On the other hand, thephysical model of a virtual device is a 3D CAD modelincluding kinematics [24]. To imitate the kinematics ofa real device, it is necessary to define the moving jointsand the attributes of each joint. A task of a device isrepresented as the set of consecutive unit motions, andconsumes a specific amount of time according to thespeeds of moving joints. Each task is triggered by aPLC output symbol. Our final goal is to provide a librarycontaining all standard manufacturing devices, such as ma-chining stations, AGVs, and robots. Therefore, users caneasily instantiate virtual devices, without making efforts formodeling virtual devices.

Fig. 10 Generated virtual device models of the robot cell


Once the virtual devicemodels are constructed, we can easilydefine a virtual plant model by using a coupled model whichcombines all virtual device models. As shown in Fig. 10, wechanged the state names of the generated virtual devicemodels for a better understanding. As shown in Fig. 11, theconstructed virtual plant model enables the virtual commis-sioning to validate control programs prior to real implemen-tation. There are various PLC vendors on the market, andthey provide hardware PLCs as well as PLC emulators. Forhardware PLCs, it is possible to communicate by using openconnectivity technology (http://www.opcfoundation.org/),which provides open connectivity in industrial automation. Inthe case of the PLC emulators, the communication can bedone by using component object model technology (http://www.microsoft.com/COM/), which allows software compo-nents to communicate.

5 Discussion and conclusions

Although, there have been many research results [2–5, 12] onthe general framework of a virtual plant for virtual commis-sioning, the automatic generation of a virtual plant for anexisting production system has rarely been brought into thefocus. This paper proposes an automated generation methodof a virtual plant model that enables virtual commissioning fora PLC simulation based on a reverse engineering approach.Design changes of a production system are inevitable, andhappen very frequently in an automated manufacturing sys-tem. It is necessary to redesign related virtual device models

when a design change occurs. This requires an excessiveamount of time for the construction of a precise virtual plantmodel consisting of multiple virtual device models. In addi-tion, the atomic model of the DEVS formalism has conven-tionally been used to represent the behavior of a virtual device.The modeling using DEVS formalism, however, requires in-depth knowledge in the modeling and simulation. To copewith this problem, an algorithm has been presented for gener-ating the virtual device model based on the log data of thecurrent production system to reduce the time and effort ofvirtual device modeling. The method of the proposed algo-rithm consists of two steps: (1) identification of a set of I/Osignal pairs of a device using the log data and PLC I/O signaltable, and (2) generation of a virtual device model. Particular-ly, the proposed algorithm only deals with the non-redundanttask set within a work cycle. However, it is also possible toextend the algorithm to include a redundant task set.

Since the proposed method discovers the device behaviormodel as a virtual device model using the collected data, wecan consider the generated models as reliable for PLC simu-lation. The generation algorithm of an atomic model is devel-oped and demonstrated for a robotic cell. The generatedatomic model of a virtual device acts as an interface forcommunicating with PLC programs.

Acknowledgments This work was partially supported by the DefenseAcquisition Program Administration and the Agency for Defense Devel-opment under the contract no. UD120035JD, UD100009DD &UD110006MD. Also, the research was partially supported by a Koreauniversity grant, and the National Research Foundation grant (2010-0021040) funded by the Ministry of Education, Science and Technology,Korea.

Signal HistoryVirtual Plant Model

HMI

States of the virtual device models

PLC program

S/W PLC

Fig. 11 A PLC simulation for the robot cell


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a reverse engineering approach to generate a virtual plant model for plc simulation

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