A SoC Simulatorthe newest component in

Open64

Wendong Wang, Tony Tuo, Kevin Lo

Dongchen Ren, Gary Hau, Jun zhang, Dong Huang SimpLight Nanoelectronics Ltd

http://svn.open64.net/svnroot/open64/sim/fsim/

Background

ISS

PSIM

Simulation for

Peripherals

Open64 CompilerApplications

Application Developer

Hardware Designer

Compiler Designer

System Designer

SoC Simulator

Challenges

Flexible Easy to change ISA and modify micro-archit

ecture Speed

Fast enough for software development and compiler correctness verification

Co-verification To speed up chip design cycle

Overview of SSIM

ISS

Performance simulator

Instruction distribution

Sh

ell

TCL asInterface

GDB

Profiler

Devices

Challenges

Flexible

Speed

Co-verification

Flexibility

Decoupling implementation function simulator implements the part

which can be seen by programmer, and performance simulator implements the parts cannot be seen by programmer

Each component is defined as one class

Case Study

Sl1 and Sl2 retarget

RISC DSP

RISC Multimedia

SL1Reg

SL2Reg

+

+

+

+

=

=

SL1Exec

SL2Exec

Challenges

Flexible

Speed

Co-verification

Speed

Use template most references are solved at compile time

Instruction caching

Page2

Page1

Page3

PC Instr A

Page2 is non-decoded When PC points to instr

A, decoder invokes Decoder will decode all

instructions within the page

So all access of Page2 in the future will not invoke decoder

Speed Results for SSIM

EDGE Equalization AAC decoder MPEG4 decoderMatrix

Decomposition 

With instruction caching

17060748 16243558 15879146 16826678

Without instruction caching

9748999 9163032 9283193 9707699

Table 1: Speed of SSIM with/without instruction caching (instructions per second)

Challenges

Flexible

Speed

Co-verification

Co-verification

ChipTargeted

Applications

FPGA/Chip

Products

Full-chip

Test suit

EclipseGDB

Compare

Targeted Applications

SSIM

RTL module

Open64 Compiler

Example: RTL module verification

PLI

Status

Testbench

Exec Unit

RegisterMemory

Fetch

Peripherals

SysCtrl

Interrupt Ctrl

MMR

Cmodel

Put all together

　 DFT 8PSK VectorAcc Cholesky PrefilterMatrix

(add/sun etc)

Complex operation

Total

C codes

206,216 201,138 219,976 111,778 72,744 169,064 107,900 1,088,816

18.939% 18.473% 20.203% 10.266% 6.681% 15.527% 9.910% 100.000%

Use C3

183,852 129,468 123,912 66,061 72,744 27,992 4,860 608,889

30.195% 21.263% 20.351% 10.849% 11.947% 4.597% 0.798% 100.000%

Table 1: Instruction count for each component in Equalization

I nst ruct i on di st r i but i on C versi on

DFT 19%

8PSK 18%

VectorAcc 20%Chol esky 10%

Prefi l ter 7%

Mat r i x(add/ sun etc)

16%

Compl exoperat i on 10%

Other features -- debug

Use GDB+Eclipse for application debugging.

Embedded debug ability can accelerate system/driver software development.

Other features -- Profiling

ISS

Performance simulator

Instruction distribution

Sh

ell

TCL asInterface

GDB

ProfilerEvent

Status

Devices

ISS

SSIM

Profiling module can turn on/off.

Can used lots of tools

PSIM Instruction

distribution tool Branch analysis

tool

Future Work

SoC architecture simulation Current SSIM does not simulate bus

traffic, hence it is not suitable to study SoC system performance issues Accelerators Power usage Bus contention

MDL Make SSIM can be retarget automatically

Thank You!