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  • Scientia Iranica D (2016) 23(6), 2845{2861

    Sharif University of TechnologyScientia Iranica

    Transactions D: Computer Science & Engineering and Electrical Engineeringwww.scientiairanica.com

    Invited/Review Article

    A survey of bandgap and non-bandgap based voltagereference techniques

    V. Hande� and M. Shojaei BaghiniDepartment of Electrical Engineering, Indian Institute of Technology (IIT)-Bombay, Mumbai, MH, India.

    Received 10 April 2016; received in revised form 1 July 2016; accepted 29 October 2016

    KEYWORDSBandgap;Sub-1 V;Survey;Temperaturecoe�cient;Voltage reference.

    Abstract. The design challenges of voltage reference generators in CMOS technology haveincreased over the years in low-voltage low-power CMOS integrated circuits, constitutinganalog, digital, and mixed-signal modules. The emergence of hand-held power autonomousdevices pushes the power consumption limit to nW regime. Along with these confronta-tions, limited full-scale range of data converters at low supply levels demands accuratereference voltage generators. This paper reviews the allied design challenges and discussesthe evolved methodologies to tackle them. This paper also prominently surveys the sub-1 Vvoltage reference topologies presented in the literature along with classic bandgap basedvoltage reference topologies. Non-bandgap (only CMOS) based reference architectures areproven to be area- and power-e�cient, but always have to be accompanied with auxiliaryon/o� chip trimming mechanism for high accuracy. We also provide insightful analysis ofthe voltage reference topologies required by the designers.© 2016 Sharif University of Technology. All rights reserved.

    1. Introduction

    An accurate voltage reference is an important block inmost of the Integrated Circuits (ICs). It establishes areference voltage point for the rest of the circuit blocksin a complete system to achieve reliable and predictableperformances. It can be used with a regulator to builda power-supply, in an operational ampli�er to set upbias voltages, and/or in data converters to establisha standard voltage for comparison. The accuracyof the reference voltage often decides on the overallperformance of a system.

    Operating principle of the circuit adds a volt-age that decreases linearly with temperature to onethat increases linearly with temperature to producea reference voltage that is constant with respect totemperature in the �rst order. The base-emitter

    *. Corresponding author.E-mail addresses: [email protected] (V. Hande);[email protected] (M. Shojaei Baghini)

    voltage (VBE) of a bipolar transistor decreases linearlywith temperature, i.e. it has a Complementary-To-Absolute-Temperature (CTAT) dependence. The volt-age that increases linearly with temperature, i.e., theProportional-To-Absolute-Temperature (PTAT) volt-age, is produced through the di�erence in the valuesof VBE in two bipolar transistors operating underdi�erent current densities. A bandgap reference circuitadds these CTAT and PTAT voltages to produce atemperature-invariant voltage VREF. The value of thereference voltage is close to the bandgap voltage ofsilicon (1.2 V).

    This paper is a survey of voltage referencetopologies since they were presented in the year1971. We would like to explain the terminology, inwhich bandgap/sub-bandgap voltage references are thetopologies that give the output voltage � 1:23 V orup/downscaled version of that. Also, non-bandgapvoltage references or voltage references generally do notconstitute any bi-polar device/s. Therefore, these volt-age reference circuits are not bound to give � 1:23 V

  • 2846 V. Hande and M. Shojaei Baghini/Scientia Iranica, Transactions D: Computer Science & ... 23 (2016) 2845{2861

    or scaled versions of 1.23 V. That means, non-bandgapvoltage references mainly have only MOSFETs and/orresistors. The paper is basically divided into threeparts. In the �rst part, we have discussed the classicreference generator topologies. These topologies aregenerally bandgap based. The second part of the paperdeals with the reference topologies broadly proposedafter 1997. Researchers started working on sub-1 Vbandgap voltage as technology started shrinking andresulted in drastic fall of operating supply voltage.Finally, the third part of the paper discusses the curva-ture correction techniques that improve the accuracy.

    2. De�nition of performance indices

    There are several di�erent performance indices used tospecify and compare voltage references. They are listedbelow:

    1. Temperature Coe�cient (TC);

    2. Minimum operable supply voltage;

    3. Power consumption;

    4. Noise;

    5. Line Sensitivity (LS);

    6. Power Supply Noise Attenuation (PSNA);

    7. Area consumption.

    Some of these parameters like area, power con-sumption, and minimum supply voltage are quietstraight- forward, while others require explanations.Many of the indices are vulnerable to the characteristicsand variations of the fabrication process.

    Actually, the TC of a voltage reference has beenpresented in many ways. However, researchers com-monly use the e�ective Temperature Coe�cient (TC).It is given in Eq. (1). It measures the maximumvariation of the voltage reference across a speci�c tem-perature range �T and normalizes this value againstthe nominal VREF at room temperature. Its unitis ppm/�C.

    TC =VREFmax � VREFmin

    VREFnom�T: (1)

    Another important performance index is the ability ofthe voltage reference to reject supply variations. Thismeasurement at DC is called Line Sensitivity (LS) orLine Regulation (LR), given by Eq. (2), and measuredin mV/V. Its frequency behavior is given by Eq. (3),called Power Supply Noise Attenuation or PSNA [1],and measured in dB. The PSNA response is primarilyevaluated at two frequencies, i.e. 100 Hz and 1 MHz(as low-frequency and high-frequency responses).

    LS =VREFmax � VREFmin

    �VDD; (2)

    PSNA(!) =VREF (w)VDD(w)

    : (3)

    As with every electronic circuit, the intrinsic devicenoise is one of the limiting accuracy factors. For recentvoltage references, its power spectral density is usuallyspeci�ed at 100 Hz (low frequency) for comparisonpurposes, while the total RMS noise depends on thechosen bandwidth. Noise parameters are not discussedhere, as all the mentioned papers did not mentioned itspeci�cally.

    Above discussed are the main performance indicesused to specify and compare voltage references. Wewill use them extensively in the review of recent cir-cuits. Besides the obvious design considerations, thereare other design considerations in a voltage referencecircuit that are important and that, at the same time,also a�ect the above performance parameters. Amongthese are circuit size and power dissipation. These twoare becoming more important parameters as hand-helddevices are becoming popular. We have extensivelyconsidered these parameters for our study.

    3. Classic voltage references

    One of the �rst bandgap voltage reference circuits waspresented by Robert Widlar of the National Semi-conductor in 1971. It is well-known as the Widlar'sbandgap voltage reference circuit [2]. The Widlarbandgap voltage reference circuit was implementedwith the conventional bipolar technology, of which thecomplete circuit is shown in Figure 1.

    The Widlar bandgap voltage reference circuit gen-

    Figure 1. Widlar voltage reference: 1971.

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    erates a stable low-TC reference voltage at 1.23 V. Thisimplementation of a bandgap voltage reference circuitwas successfully applied in the National Semiconduc-tors voltage regulator integrated circuit LM 113, whichproved capable of achieving an output voltage withlow TC. Since then, it has been applied in manyvoltage regulator ICs to generate the internal referencevoltage/s.

    3.1. Robert Widlar's voltage reference: 1971One of the oldest VBE and �VBE compensated bandgapvoltage reference circuits is the Widlar bandgap voltagereference circuit introduced by Robert Widlar in 1971.These bandgap circuits are based on the principleshown in Figure 1. The transistors Q1 and Q2are operated at di�erent current densities to producetemperature-proportional voltages across R3 and R2.A third transistor Q3 is used to sense the outputvoltage through R2. As a result, Q3 drives the outputto a voltage which is the sum of VBE of Q3 andthe temperature-dependent voltage across R2. Whenthe output voltage is set to approximate the bandgapvoltage of silicon, the voltage across R2 will compensatethe temperature coe�cient of VBE, and the outputvoltage will be temperature-invariant.

    Furthermore, the thermal voltage (VT ) extractedfrom the �VBE of two BJTs with di�erent emitter areasand, hence, di�erent current densities will form thePTAT voltage, while the base-emitter voltage (VBE)of the BJT will form the CTAT voltage. The circuit issimple, but not easy to implement in modern CMOSprocess or to control the output, because the BJTsimplemented in the CMOS process are sensitive toprocess variation.

    In this circuit, Q1 is operated at a relatively highcurrent density. The current density of Q2 is about10 times lower and the emitter-base voltage di�erence�VBE between the two devices appears across R3,de�ning the emitter current and the collector current ifthe transistor gain is high. Q3 then works as a currentgain stage, also providing the VBE voltage necessary toform the output. A simpli�ed analysis of the circuitfollows.

    The collector current IC of a BJT is written as:

    IC = I0�exp


    � 1��

    : (4)

    where I0 is a process-dependent constant, VBE is thebase-emitter voltage, � is the emission coe�cient, andVT is the thermal voltage. If two transistors areoperated with di�erent collector current densities, Ji,then the di�erence of their base-emitter voltages isgiven by Eq. (5).

    �VBE = VT ln�J1J2

    �: (5)

    In Figure 1, one can see that the output of thebandgap reference (BGR) proposed by Widlar is givenby the sum of the base-emitter voltage of Q3 and themultiplied PTAT term on R2, as shown by Eq. (6):

    VREF = VBE +R2R3

    �VBE: (6)

    For the time being, we consider that VBE can beexpressed by the linear expression VBE = VBGCT ,where VBG is the silicon bandgap voltage at 0 K,C is a constant, and T is the absolute temperature.Other higher-order temperature e�ects will be studiedextensively in Section 7. Therefore, R1 and R2 can bescaled together with the current density di�erence ofQ1 and Q2 to achieve dVREF=dT = 0.

    3.2. Kuijk's voltage reference: 1973Among the various existing bandgap voltage referencearchitectures to date, one of the most ubiquitousones is the Kuijk bandgap reference circuit, shown inFigure 2 [3]. Reference voltage VREF is evaluated asthe sum of the voltage drops across R1, R3, and thebase-emitter voltage of D1 (VBE;1). If opamp gain isvery high, reference voltage is:

    VREF = VBE + VT�

    1 +R1R3


    �; (7)

    where IS1 and IS2 represent the saturation currents ofD1 and D2. The �rst term in Eq. (7) is ComplementaryTo Absolute Temperature (CTAT) and the second termis VT -based, i.e. Proportional To Absolute Temperature(PTAT). The sum of both is trimmed with scalingfactor (selecting proper resistor values) to achievetemperature-insensitive reference voltage.

    3.3. Brokaw's voltage reference: 1974The important fact is that the Widlar's circuit neglectsthe e�ect of base current owing in R1 and R2.The variability in this current due to processing andtemperature e�ects on beta (feed-forward current gain)

    Figure 2. Kuijk voltage reference: 1973.

  • 2848 V. Hande and M. Shojaei Baghini/Scientia Iranica, Transactions D: Computer Science & ... 23 (2016) 2845{2861

    Figure 3. Brokaw voltage reference: 1974.

    gives rise to an output voltage error and drift. Thise�ect is particularly severe when the current in D1 ismade much smaller than currents in D1 and D2 toproduce the required current density di�erence. Toresolve this issue, Paul Brokaw introduced the well-known BGR circuit, shown in Figure 3 [4].

    The Brokaw bandgap voltage reference circuitis simple and the compensation performance can beeasily adjusted by post-processing, such as trimmingresistors R1 and R2, thus overcoming the processvariation problem. On the contrary, trimming resistorsR1 and R2 in the Widlar bandgap voltage referencecircuit alter the currents owing through the BJTs and,hence, the performance of the voltage reference circuit.As a result, adjusting performance of the Widlarbandgap voltage reference circuit by trimming is noteasy to implement. Nevertheless, a Brokaw bandgapvoltage reference circuit that applies an opamp has theadvantage of a large output driving power, which makesit suitable to be applied in circuits with heavy loads,while the Widlar bandgap voltage reference circuitrequires an extra bu�er stage to provide the drivingpower for large loads.

    In this circuit, the operational ampli�er makesIC1 = IC2 through resistances R, and the �VBE thatappears across R2 is then multiplied by 2R1, since bothemitter currents of Q1 and Q2 ow into this resistor.The reference output is the sum of VBE, Q1, andV R1. The author also introduces some compensationschemes for the base currents of Q1-Q2 through the useof auxiliary base resistances, not shown in Figure 3.

    4. Sub-1 V voltage references

    The IC fabrication trend shows reduction in channellength, which leads to overall decrement in the geom-

    etry size of transistor. Reduction in the geometry sizeleads to increase in circuit capacity and speed. Astransistor size decreases, the circuit functionality of agiven area of substrate increases. Smaller device sizealso yields lower parasitic capacitance, which increasesspeed and decreases power consumption. Simultane-ously, operating supply voltage must also be scaleddown due to the increased electric �eld and reducedbreakdown voltage caused by the higher doping pro-�le required by small device. Decreased operatingvoltage facilitates low power consumption, which isincreasingly important as circuit complexity increases.However, the voltage reference circuit becomes moredi�cult to design with the lower supply voltage.

    The low operating voltage imposes two designchallenges on voltage reference circuit designing. The�rst constraint is the output of the voltage referencecircuit. The output voltage of the voltage referencecircuit must be lower than the supply voltage. Theoutput voltage of most of the conventional bandgapvoltage reference circuits discussed in Section 3 is1.23 V. When the supply voltage is lowered to below1 V, how can one achieve a reference voltage withmagnitude below 1 V. The voltage reference circuitcapable of generating a lower output voltage is referredto as sub-1 V voltage reference circuit, which literallymeans that the output of the voltage reference circuitis lower than 1 V. The second design challenge is theoperating supply voltage. The voltage reference circuitis required to be able to work with a low supply voltage.When the voltage reference circuit can operate at asupply voltage lower than 1 V, it is known as sub-1 V supply voltage reference circuit. Obviously, a sub-1 V supply voltage reference circuit can only generatereference voltage that is lower than the supply voltage.As a result, it is also a sub-1 V voltage reference circuit.

    The conventional bandgap voltage reference cir-cuits presented in Section 3 are suitable neither for lowvoltage applications nor for generating low referencevoltage. The constraint on achieving a sub-1 Vreference voltage is the bandgap voltage itself. In thesubsequent section, we study some of the popular sub-1 V voltage reference generation circuits.

    4.1. Neuteboom's voltage reference: 1997While designing a DSP-based hearing instrument inte-grated circuit, Neuteboom et al. [5] were limited withsupply voltage of 0.9 V. It was clear that with thislimited supply voltage of 0.9 V, a conventional referencevoltage of 1.23 V could not be realized. Neuteboomet al. proposed the reference circuit illustrated in Fig-ure 4, which is based on the resistive division techniqueand provides an output voltage lower than 1.23 V.Their reference circuit makes use of three vertical PNPtransistors with emitter ratio of 1 : N : N . The opampcontrols the emitter current and maintains a �VBE

  • V. Hande and M. Shojaei Baghini/Scientia Iranica, Transactions D: Computer Science & ... 23 (2016) 2845{2861 2849

    Figure 4. Neuteboom voltage reference: 1997.

    across the resistor R1 in the PTAT current generationloop. Operation under low supply voltage operationcondition is achieved by connecting the resistor R3across the bandgap reference, and the resulting outputvoltage becomes a fraction of the bandgap voltage,which is given by:

    VREF =R3

    R2 +R3(VBE + IPTATR2); (8)

    that can be scaled to any value. A down-scaling ofthe bandgap voltage is obtained by proper choice ofresistors R2 and R3. The proposed circuit achievesan output voltage of 0.67 V under a minimum supplyvoltage of 0.9 V. Basically, the result is a simpleresistive division of the bandgap reference voltage, i.e.1.23 V.

    4.2. Banba's voltage reference: 1999Similar to Neuteboom et al. [5], Banba et al. [6]have also proposed a technique to overcome theselimitations to implement sub-1 V bandgap voltagereference circuits in CMOS technology. They have usedresistive sub-division technique to reduce the minimumrequired supply voltage. The operation of the sub-1 Vopamp based bandgap voltage reference circuit withresistive division is similar to that of the conventionalopamp based bandgap voltage reference circuit, wherean opamp will form an inverted feedback loop to forcethe two input nodes of the opamp to have the samevoltages. Consider the case of R2 = R3, such thatI1 = I2; N is the emitter area ratio between Q1 and Q2.The current I2 is mirrored to form I3 and, therefore,the output voltage of the bandgap voltage referencecircuit is given by:

    VREF =R4R3

    �VBE1 +


    VT ln(N)�: (9)

    It can be observed that the performance of thisvoltage reference circuit should be comparable to that

    Figure 5. Banba voltage reference: 1999.

    of the conventional bandgap voltage reference circuit,at least in theory. At the same time, we should alsonotice that VREF can be scaled by the resistor ratioR4=R3, thus, achieving an arbitrary VREF.

    As observed from Figure 5, the minimum operat-ing supply voltage of such a circuit is found to be 1.4 V,which is almost the same as that of the conventionalbandgap voltage reference circuit. This is due to thelimitation of the input common mode of the opamp.This limitation makes the sub-1 V bandgap voltagereference circuit with resistive division not applicablefor low supply voltage applications. Moreover, suscep-tibility of the bandgap voltage reference circuit to noiseincreases because of the low output impedance of thebandgap voltage reference circuit, which is basically theoutput impedance of M3. Finally, the transistor, M3,has to be biased in saturation mode to form a propercurrent mirror; thus, the resistor value of R4 will becon�ned to a certain region of values. The last, but notleast, important fact is that the load regulation of thecircuit is very low because of the low output impedanceof the voltage reference circuit, which equals the outputimpedance of the current mirror.

    Nevertheless, the resistive division technique doesdemonstrate that there are circuit topologies that canalleviate the common-mode input voltage constraint ofthe opamp in the reference circuit and, hence, inspirea lot of sub-1 V bandgap voltage reference circuitdesigns. Banba's architecture is the most commonamong industries as well as academic researchers. Thefollowing sections present modi�cations to this sub-1 Vbandgap voltage reference circuit by resistive division,where the input voltage constraint to the opamp islowered and, thus, overcomes the common-mode inputvoltage range problem to achieve sub-1 V opamp basedbandgap voltage reference circuits.

    4.3. Divided resistive VBE-Leung and Mok'svoltage reference: 2002

    Although the resistor factor R4=R3 can help to over-come the sub-1 V output voltage problem, such thatthe output voltage can be smaller than 1.2 V, thebandgap voltage reference circuit in Figure 5 stillcannot work with a sub-1 V supply voltage. The

  • 2850 V. Hande and M. Shojaei Baghini/Scientia Iranica, Transactions D: Computer Science & ... 23 (2016) 2845{2861

    Figure 6. Leung and Mok voltage reference: 2002.

    reference core circuitry proposed by Banba et al. [6] ismodi�ed by Leung and Mok [7]. The main di�erencesare that an ampli�er with a PMOS input stage isused and the inputs of the ampli�er are connectedto nodes N1 and N2 instead of N3 and N4. If aP-channel di�erential input stage opamp is used, thesupply voltage is limited by the common-mode inputvoltage of the opamp. As a result, the input voltageto the opamp has to be low enough to make sure theP-channel input MOSFET pair are operating in thesaturation region. Modi�ed bandgap voltage referencecircuit is shown in Figure 6 to lower the input voltagesof the opamp by applying resistive voltage divider [7].Assume R1A = R2A and R1B = R2B . When theopamp has large gain, the inverted feedback loop of theampli�er will ensure VA = VB . As a result, referencevoltage yields:

    VREF =R4R1

    �VBE1 +


    VT ln(N)�: (10)

    The minimum operating supply voltage of this voltagereference circuit is given by Eq. (11) with VBE beingreplaced by the resistive sub-divided VBE as:

    VDDmin =R2BR2

    VBE1 + jVthp j+ 2jVDSsat j: (11)As a result, the minimum operating supply voltage ofthe voltage reference circuit is being lowered by a factorof R2B=R2 acting on VBE;1. We can almost concludethat the circuit has alleviated all the sub-1 V voltagereference circuit design problems.

    4.4. Independent biased resistive divided VBE:Ker's voltage reference: 2002

    This circuit has a similar beta-multiplier circuit struc-ture as the conventional opamp based bandgap voltagereference circuit where the current mirror transistors

    are directly connected to the temperature-sensitiveBJTs [8]. As a result, when the temperature variesfrom 20�C to 100�C, the VBE voltage of BJT variesfrom 812.55 mV to 646 mV, while the bandgap voltagereference circuit output stays almost the same. Asa result, the drain to source voltages of M1, M2,and M3 will not be the same and the transistorsin the current mirror will su�er from the channel-length modulation e�ect. Hence, the above di�erencein source to drain voltages will cause the outputcurrent di�erences in the current mirror formed by M1,M2, and M3. However, such mirror output currentmismatch problems exist in all source-to-drain voltageconditions when VDD is high. On the contrary, whenVDD is low and close to 1 V, M will be working closeto the linear region. As a result, the IDS currentmismatch problem of the current mirror will be severe.Although the current mirror mismatch problem canbe corrected by using a cascode current mirror, theextra layer of transistors in the cascode current mirrorwill increase the minimum operating supply voltage.Therefore, cascode current mirror is not applicableto correct the current mirror mismatch problem ofthe sub-1 V voltage reference circuit. Ker et al. [8]presented a modi�cation to alleviate the current mirrormismatch problem by independently biasing the BJTs,instead of directly connecting the MOSFETs of thecurrent mirror in the beta-multiplier circuit to theBJTs.

    To alleviate the channel-length modulation e�ectthat a�ects the performance of the current mirror, andhence the performance of the overall voltage referencecircuit, Figure 7 shows a modi�ed schematic, wherethe two BJTs are biased independently with two inde-pendent current sources instead of the opamp drivencurrent sources. The independent biased resistivedivided VBE opamp based beta-multiplier bandgap sub-1 V voltage reference circuit was �rst proposed by Keret al. [8].

    Figure 7. Ker's voltage reference: 2006.

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    Similar to the Banba's voltage reference circuit,resistive sub-division is applied to reduce the inputvoltage to the opamp. When implementing the circuit,any current source that can operate with sub-1 V VDDcan be applied. Note that although the current gener-ated by the Widlar current source is PTAT, applying itto the sub-1 V opamp based beta-multiplier bandgapvoltage reference circuit by resistive sub-division withindependent biased VBE will not a�ect the performanceof the system as long as I1 = I2, and the two currentsources have the same thermal property. The referencevoltage is:

    VREF =


    R1B +R1A+R4


    + VBE2


    R1B +R1A: (12)

    Nevertheless, all resistive division voltage refer-ence circuits require resistors with large resistance toscale down the reference voltage. The use of resis-tors with large resistance causes the resistive divisionvoltage reference circuit to su�er from the problemsof large silicon area. Use of dummy resistors foravoiding process variations results in additional areaconsumption. Area related problem is aggravated dueto implementing resistor-matching techniques used ofresistors, such as inter-digitization; which is area con-suming. The production cost of this kind of bandgapvoltage reference circuit is high, which prohibits theirimplementation in many existing applications.

    4.5. Annema's voltage reference: 2012Most of the sub-1 V bandgap voltage reference designs

    are based on the structure introduced by Banba etal. [6]. For low-power operation, high-ohmic resistors(occupying a large area) must be used in all thesetechniques, leading to an immediate trade-o� betweenpower consumption and chip-area, as we have discussedin the previous subsection. However, this trade-o�prevents the local generation of reference voltageswhere they are required: either the power penalty orthe area penalty would be too signi�cant. Alternativetopologies that do not require high-ohmic resistors typ-ically are non-bandgap based reference circuits, relyingon threshold voltages, and hence require trimming toachieve low spread.

    This paper presents a sub-1 V bandgap voltagereference that circumvents the power-area trade-o�of conventional sub-1 V bandgap voltage reference,aiming at local reference voltage generation wherevera reference voltage is needed in a die [9]. To break thepower-area trade-o�, no resistive averaging or subdivi-sion can be used to get sub-1 V operation, while a driveto minimum area results in avoiding any topology usingopamps, high ohmic resistors, or multiple diodes. Thetopology of the bandgap voltage reference by Annemaet al. [9] is shown in Figure 8. The PMOS transistorsMP1 and MP2 are biased in subthreshold region. MP1is wider than MP2, which is the necessary conditionfor PTAT voltage generation if currents are equal inboth branches. Along with this condition, Annema etal. have used shorter-length MP1 compared to MP2.By this technique, they have exploited reverse-shortchannel e�ects and yielded temperature-independento�set voltage �Vth.

    VREF = VT ln(A)N + VBE �N�Vth= VREFconven �N�Vth: (13)

    Figure 8. Principle of Annema's voltage reference: 2012.

  • 2852 V. Hande and M. Shojaei Baghini/Scientia Iranica, Transactions D: Computer Science & ... 23 (2016) 2845{2861

    The proposed circuit operates at supply voltage of1.1 V over temperature range of -45 to 135�C forthe reference voltage value of 944 mV. The mostattractive aspect of this circuit is it consumes only1.4 �W of power along with 0.0025 mm2 of siliconarea and produces 30 ppm/�C of accuracy with lesserspread in reference voltage across process variations.Due to these unique low area and power consumptioncombination along with process tolerance quality, itcoins a new concept as local generation of referencevoltage.

    4.6. Naja�zadeh's voltage reference usingFilanosky's ZTC: 2004

    A conventional band-gap voltage reference is generallyused since its output voltage is stable against tem-perature and process variations. Banba and otherresearchers have �gured out the solutions for sub-1 Vbandgap reference circuit, which also operates at below1 V. However, It was predicted in the ITRS roadmap that in year 2010, the mainstream power supplyvoltage would be around 0.6 V. Therefore, to solvethis issue, many researchers have moved towards MOSbased voltage reference. MOS based voltage referencesare not very much process-friendly, but good in termsof power and area consumption. Among the manytopologies of CMOS based voltage reference circuits,ZTC based reference design is a quite uncommon butinnovative concept.

    As in the study of Filanosky et al. [10], ifMOSFET is biased at a speci�c gate-source voltageand drain current (i.e. bias point), the bias pointdoes not change irrespective of change in temperature.It is called a ZTC point. Figure 9 shows the ZTCpoint. ZTC point arises due to the e�ect of mutualcompensation of mobility and threshold voltage. Thistechnique is implemented by Naja�zadeh along withFilanosky in 2004 [11]. The presented voltage referencecircuit is shown in Figure 10.

    Low-voltage standard PTAT current generator is

    Figure 9. Filanosky's concept of ZTC: 2001.

    implemented using M1 �M4 and RB . The referencecore circuit consists two diode connected transistorsM7 and M8 operating below the ZTC point, and tworesistors, R1 and R2. Transistors M5 and M6 supplyPTAT PTAT currents to the transistors M7 and M8.The output reference voltage is given by:

    VREF =VGS7

    1 +R1=R2+

    VGS81 +R1=R2

    : (14)

    4.7. Leung and Mok's voltage reference: 2003In their paper, Leung and Mok presented a voltage ref-erence based on weighted gate-source voltage di�erencebetween an NMOS and a PMOS [12]. The proposedCMOS voltage reference is shown in Figure 11. Thecircuit has 3 sections:

    i. A bias circuit (M1 �M4 and RB);ii. Start-up circuit (MS1 �MS3);iii. Reference core (MP , MN , R1, and R2).

    Long channel lengths are selected for eliminating thechannel modulation e�ect and biasing the transistorsin saturation region at lower VGS values.

    Figure 10. Naja�zadeh voltage reference: 2004.

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    Figure 11. Leung and Mok's voltage reference: 2003.

    Assume the current owing through R1 and R2 isnegligible; the bias current to MP and MN is M timesIB . The reference voltage is given by:

    VREF =�

    1 +R1R2

    �VGSn � VGSp : (15)

    A key factor in designing reference is keeping both MPand MN in deep saturation region. Therefore, the gate-source voltage is governed by the fundamental equationof MOS transistors in saturation region.

    The minimum supply voltage should be consid-ered at the minimum operable temperature as thresh-old voltages are at maximum. The minimum supplyvoltage VDDmin is given by:

    VDDmin =�

    1 +R1R2

    �VGSn + jVDS5;sat j: (16)

    The minimum supply voltage is 1.4 V and it can bereduced if lower threshold voltage devices are used.Iannaccone and his research group have presented aseries of articles from 2005 to 2014.

    These papers are the extended version of thetopology, which was presented by Leung and Mok in2003.

    5. Iannaccone's series of voltage references

    Iannaccone has signi�cantly contributed to referencecircuits. He has proposed few important topologies,which span almost over a decade, i.e. from 2005 to 2014.We have tried to study his work in this section.

    5.1. Reference voltage: CICC-2005In CICC'2005, Iannaccone and Vita presented a voltagereference, which could be implemented in any standardCMOS technology, based on the weighted gate-sourcevoltage di�erence between two NMOS transistors [13].

    Figure 12. Vita-Iannaccone voltage reference:CICC-2005.

    Such solution leads to a perfect cancellation of the ef-fect of the temperature dependence of carrier mobility,which was a drawback in Leung and Mok's topology.

    The presented voltage reference generator isshown in Figure 12. It has a supply-independent cur-rent generator, I0; such current is then ampli�ed andinjected into an active load to generate the referencevoltage. A temperature-invariant voltage reference isobtained by compensating the temperature dependenceof the generated current with the temperature de-pendence of the NMOS threshold voltage. The �nalreference voltage is:

    VREF =�

    1 +R1R2

    �VGS8 � VGS7 : (17)

    The minimum supply voltage limitation is imposed bythe VDD independent current generator circuit. Theminimum allowable supply voltage is:

    VDDmin = jVGS6 j+ VDS2;min + VGS4 : (18)The supply voltage must be larger then 1.5 V for theused AMS 0.35 �m CMOS process.

    Unfortunately, in this design, the temperaturecoe�cient degrades due to non-ideal e�ects, i.e. channellength modulation and body e�ect. An experimentaltemperature coe�cient of 25 ppm/�C is achieved.

    5.2. Reference voltage: VLSI Symposium-2006As the battery-operated systems have gained popular-ity after 2005, the reference circuit must consume lowpower and area with reasonable accuracy. The series ofDe Vita and Innaccone [13] consumes 2.25 �W of powerat the supply voltage of 1.5 V with the consumptionof 0.08 mm2 chip area. The major reason behind thisperformance is power and area trade-o� due to presence

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    Figure 13. Vita-Iannaccone voltage reference: VLSISymposium-2006.

    of resistors. Therefore, De Vita et al. [14] have replacedthe resistors with MOSFETs to break the power andarea trade-o�. The enhanced reference circuit is givenin Figure 13.

    Similar to De Vita and Iannaccone [13], the activeload is used to generate the reference voltage in thisstudy. It consists of two NMOS transistors, M7 andM8, biased by I0, and a voltage divider formed by M9and M10. All transistors in the active load operate inthe saturation region. The �nal reference voltage is:

    VREF =Vth+




    !� 1p




    where, k = �CoxW=L and I0 is supply independentcurrent.

    This reference circuit consumes 0.12 �W of powerat the supply voltage of 1.5 V with the consumption

    of 0.015 mm2 chip area. The improvements are 5 and18 times with regards to power and area, compared tothe topology of De Vita and Iannaccone [13]. Moreover,this design provides both a complete suppression of thetemperature dependence of mobility and a compensa-tion of non-ideal e�ects, i.e. channel length modulationand body e�ect. Hence, temperature insensitivity isalso enhanced twice, i.e. � 12 ppm/�C. Unfortunately,the minimum supply voltage is still quite high, thatis, larger than 1.5 V, and thus it is not suitable forlow-voltage applications.

    5.3. Reference voltage: JSSC-2007In their paper, De Vita and Iannaccone [15] presenteda CMOS voltage reference with a minimum supplyvoltage smaller than 1 V, really enabling low-voltageoperation, which still provides a very good temper-ature coe�cient. Let us consider the active load ofthe proposed reference voltage generator, shown inFigure 14.

    Assuming that all transistors of the active loadwork in the saturation region, the output referencevoltage would be given by:

    VREF = Vth10 +�VTN � 1




    The minimum supply voltage is imposed by the currentgenerator circuit. It is given as:

    VDDmin = jVGS5 j+ VDS1;min : (21)The minimum supply voltage is 0.9 V in the AMS0.35 �m CMOS process. The accuracy achieved in thisarchitecture is 10 ppm/�C along with improvement inpower consumption. Power consumption is limited toonly 0.0036 �W.

    Figure 14. Vita-Iannaccone voltage reference: JSSC-2007.

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    5.4. Reference voltage: JSSC'2011 andjournal of circuit theory and applications,i.e. JCTA'14

    An ultra-low voltage and ultra-low power voltage ref-erence circuit was presented by Magnelli et al. inJSSC'2011 [16]. They fabricated the circuit in theUMC 180 nm CMOS process. Importantly, the circuitworks with all transistors in subthreshold region, thusallowing a drastic reduction of minimum supply volt-age and power consumption. The proposed solutionrepresents a signi�cant advance in low-power, low-voltage reference circuit design, which chooses a newmilestone for extremely low power operation. Thepower consumed by the circuit is only 2.6 nW, whichis about one order of magnitude lower than that of thebest results found in the literature at the time, and theminimum supply voltage for correct operation falls to0.45 V. However, across the process, the circuit is alittle vulnerable; thus, external trimming is requiredto achieve the speci�ed accuracy and DC voltagelevel.

    Even after achieving power dissipation down to2.6 nW, Iannaccone and his group were working aggres-sively on reduction of power dissipation. Iannacconeet al. [17] presented a voltage reference consisting ofonly two nMOS transistors with di�erent thresholdvoltages. Measurements performed on 23 samplesfrom a single batch show a mean reference voltage of275.4 mV. The subthreshold conduction and the lownumber of transistors enable us to achieve a meanpower consumption of only 40 pW. The minimumsupply voltage is 0.45 V, which is considered withone of the ultra-low power reference topologies. Themean TC in the temperature range of 0 to 120�Cis 105.4 ppm/�C. The occupied area is 0.018 mm2.The power supply rejection rate without any �lter-ing capacitor is -48 dB at 20 Hz and -29.2 dB at10 kHz.

    6. Voltage reference circuits based onsubthreshold MOSFETs

    During 1995 to 2000, the demand for analog integratedcircuits that had to operate under lower supply voltagesand ultra-low power rapidly increased, especially inapplications like portable equipment (e.g., watches,handheld gadgets, smart phones, etc.). Fortunately, forthe analog engineer, the sub-threshold voltage charac-teristics of MOSFET devices mimic the characteristicsof Bipolar devices. Therefore, subthreshold-basedMOSFET was an potential replacement for BJTs.Therefore, the nanopower regime opened up a wideperspective for reference circuits using a subthresholdtransistor. Even though these transistors are quitedependent on process, they have become famous dueto their ultra-low power and low area consumptioncapabilities. We will see some reference circuits basedon subthreshold biasing principle.

    6.1. Ytterdal's voltage reference: 2003As discussed in Section 4.6, Naja�zadeh and Fi-lanovsky [11] have designed MOSFET-based referencecircuit to solve the problem of supply voltage reductiondue to shrinking technology. Ytterdal [18] also solveda similar supply-related problem using MOS devices;however, he used subthreshold biased MOS transistorsfor replacing BJTs, where Naja�zadeh used a conceptof ZTC.

    Ytterdal basically used the technique presentedby Banba. However, he replaced bipolar devices withsubthreshold-based MOSFETs. As a consequence,Ytterdal was able to reduce the supply voltage wellbelow 1 V. He also used low-threshold voltage NMOStransistors to reduce VDDmin . Moreover, he alsoreduced the threshold voltages of PMOS by bulk-biasing. The proposed topology is given in Figure 15.

    Due to these techniques, the reference voltagecircuits operate at 0.6 V for 0.13 �m digital CMOS

    Figure 15. Ytterdal voltage reference: 2003.

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    technology. The reported temperature coe�cient is93 ppm/�C.6.2. Reference voltages by Giustolisi et al.,

    2003, and Huang et al., 2006Similar to Ytterdal, Giustolisi et al. [19] have also usedidentical principle to develop a reference circuit. Theyexploit the fact that the gate-source voltage decreaseslinearly with temperature, if it is biased with a constantdrain current.

    As shown in a Figure 16, the current IR1 isthe minimum supply voltage imposed by the currentgenerator circuit. It is given as:

    IR1 =VGS1R1

    : (22)

    This current is then provided for the second sub-circuits M5 and M6 and the output voltage is givenby:

    VREF = K1VGS +K1VT ; (23)

    where K1 and K2 are the combinations of transis-tor aspect ratios and resistor ratios. After selectionof proper values for resisters and MOSFETs, theproposed architecture achieves an output voltage of0:2953 � 0:0108 V and a temperature coe�cient of119� 35:7 ppm/�C for the temperature range of -25 to125 �C. Operable minimum supply voltage is 1.2 V withline regulation of 2 mV/V. The current consumption is3.6 �A.

    The circuit presented by Giustolisi et al. is com-plex and consumes larger area and power comparedto the reference circuit proposed by Huang et al. [20].The circuit by Huang et al. is given in Figure 17.The comparison is done on the basis of identicalworking principle, i.e. gate-source voltage compensatedby thermal voltage (core transistors are operating insubthreshold region). The presented circuit by Huang

    Figure 16. Giustolisi et al.: voltage reference, 2003.

    Figure 17. Huang et al.: voltage reference 2006.

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    et al. is a less complicated low-voltage, low-powerCMOS reference circuit using subthreshold biasingconcept.

    They have also compensated the channel-lengthmodulation e�ect to improve the performance. Themean reference voltage is � 222 mV with line regula-tion of 2 mV/V (for VDD varies from 0.9 to 2.5 V).Peak-to-peak variation of 6 mV is reported for tem-perature from -20�C to 120�C. The chip area is lessthan 0.0238 mm2 with minimum power consumptionof 3.3 �W.

    7. High-order curvature correction

    Precision bandgap references are signi�cantly necessaryfor many applications ranging from solely analog, tomixed-mode and purely digital circuits, such as dataconverters, digital data RAMS, power converters, andmemory controlling circuits. They are known for theirhigh accuracy and temperature-independent behavior.The reference voltage is required to be stable over thesupply voltage and temperature variations. It shouldalso be implemented without any modi�cation of thestandard fabrication process.

    A conventional bandgap reference circuit is �rst-order temperature compensated. Basically, it is anappropriately scaled sum of negative TC voltage VBEand positive TC voltage VT , which is the thermalvoltage. With regard to nonlinearity of the voltageVBE, TC of �rst-order temperature compensated refer-ences is always limited between 20 and 100 ppm/�C.Therefore, to overcome this limitation, many high-order temperature compensation approaches have beenpresented. Compensation of the high-order temper-ature dependent terms of the reference voltage (non-linear terms) is therefore referred to as curvaturecorrection or curvature compensation. The primarycurvature correction techniques used in practice are,for example, the quadratic temperature compensationproposed by Song and Gray [21], the exponentialtemperature compensation developed by Lee et al. [22],the piecewise linear curvature correction presented byRincon-Mora and Allen [23], and the temperaturedependent resistor ratio with a high resistive polyresistor and a di�usion resistor proposed by Leunget al. [24]. The accuracy of bandgap references hasbeen enhanced with these techniques; however, theyalso increase the requirements of precise matching ofthe current mirror. Some of the popular curvaturecorrection techniques will be discussed in the nextsubsections.

    7.1. Song's voltage reference: 1983The nonlinear relationship between VBE(T ) and tem-perature is expressed as:

    VBE(T ) =VBG � [VBG � VBE(Tr)] TTr� (� �m)VT ln


    �; (24)

    where VBG is the bandgap voltage of Si as a functionof temperature, Tr is the reference temperature, �is a temperature constant dependent on technology,and m is the order of the temperature dependence ofthe collector current. The third term of Eq. (24) isproportional to PTAT2 voltage.

    Song et al. proposed to add a PTAT2 term tothe linear PTAT term to compensate for the junctioncurvature. The concept is clearly demonstrated bySong et al. The optimum values of the PTAT2correction voltage, the �rst-order corrected VREF, andsecond-order corrected VREF at 25�C were measuredand recorded 61 mV, 1.256 V and 1.192 V, respectively.

    7.2. BJT current subtraction - Gunawan'svoltage reference: 1993

    As discussed by Gunawan et al. [25], a current sourcewith second-order temperature dependency can beconveniently obtained by the BJT in the same wayas that in the output stage of the opamp based beta-multiplier bandgap voltage reference circuit. (Thesecond-order temperature dependent nature of the BJTVBE voltage is one of the major reasons for the needto implement second-order temperature compensationto obtain a low TC reference voltage over a widetemperature range.) The presented circuit is shownin Figure 18. When this BJT current source is appro-priately connected to the voltage reference circuit, itforms a current sink and, hence, functions as second-order current subtraction circuit to achieve second-order curvature correction. Consider the schematic ofBanba's opamp based bandgap voltage reference circuitwith the BJT current subtraction. This topology isan extension of Banba's concept. The resistors in the

    Figure 18. Gunwan's voltage reference topology: 1993.

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    circuit satisfy R3 = R8, R4 = R7, and R5 = R6. Theemitter areas of Q1, Q2, Q3, and Q4 are in the ratioof 1 : N : 1 : 1. Note that the negative feedbackcon�gured opamp will bias the input voltages to bethe same; therefore, we write:

    VA = VB : (25)

    Therefore, with R5 = R6, the currents that owthrough R5 and R6 will be the same and equal to I2.Assume the opamp is ideal; no current will be owingin/out of V+ and V . As a result, the currents that

    ow through R4 and R7 will be the same; hence:

    I1 =VT ln(N)

    R1; (26)


    I2 =VBE1

    R4 +R5; (27)


    I3 =VT ln(T=Tnom)

    R3: (28)

    The KCL at node C implies I = I1 + I2 + I3, and thecurrent mirror pair formed by M2 and M3 copies thecurrent to the output branch. By selecting S2 = S3,we shall obtain:

    VREF = K1(VREFconven +K3 ln(T=Tnom)VT ); (29)


    K1 = R2=(R4 +R5); K2 = (R4 +R5)=R1;


    K3 = (R4 +R5)=R3:

    Furthermore, it is clear that when T = Tnom, thevoltage reference obtained by Eq. (29) will have thesame form as that of the conventional bandgap voltagereference circuit at Tnom (as studied in the previoussections).

    At other temperatures, the high-order tempera-ture dependent term K3 ln(T=Tnom)V T will compen-sate the second-order temperature dependent term ofVBE;1. This is achieved by appropriate selection of theresistor R3 to drive Q3.

    7.3. Piecewise curvature correction - byRincon-Mora and Phillip E. Allen: 1998

    Around the year 1998 and onwards, the demand forlow voltage references appeared, especially in mobilebattery-operated products such as cellular phones,pagers, camera recorders, and laptops. Consequently,low-voltage and low-quiescent current ows are intrin-sic and required characteristics for increased battery

    e�ciency. Along with that, �nancial considerationsalso require these circuits to be realized in relativelysimple processes, such as standard CMOS. Owingto this requirements, Rincon-Mora and Phillip E.Allen have designed and fabricated a low-voltage,micropower, curvature-corrected bandgap circuit in arelatively inexpensive process, MOSIS CMOS 2 �mN-well technology with an added P-base layer [23].The P-base layer is used to create NPN transistors.However, a vanilla CMOS version of the circuit canalso be designed by using lateral PNP transistors.The circuit implements a novel current-mode piecewise-linear curvature-correction technique.

    Piecewise-linear curvature-correction is a novelconcept implemented by Rincon-Mora and Phillip E.Allen. Afterwards, many researchers have used en-hanced techniques based on this concept. Operationprinciple is given in Figure 19(a) and (b).

    The curvature correction is based on the additionof a nonlinear component to the output of a �rst-orderbandgap reference. This is used to o�set the nonlinearbehavior of VBE with respect to temperature. Thenonlinear component, in this case, is realized by INL inthe current-mode topology of the circuit described inFigure 19(a). It is basically a current-mode piecewise-linear form of compensation. The essence of the circuitcenters on current subtraction and the characteristicsof non-ideal transistors. Figure 19(b) graphicallyillustrates the operation of the circuit throughout thetemperature range. The INL behavior is described by:INL = 0 if; IVBE > IPTAT; (30)

    or:INL = K1IPTAT �K2VBE if, IVBE < IPTAT;


    where K1 and K2 are constants and de�ned by currentmirroring ratios.VREF = K1(K2 + VBE1 +K3 ln(T=Tnom)VT )

    = K1(VREFconven +K3 ln(T=Tnom)VT ); (32)

    where K3 is multiplication constant.Finally, the reference voltage (VREF) is tempera-

    ture compensated to exhibit a behavior that is graph-ically described by Figure 19(c) and (d). The lowertemperature range is essentially a �rst-order bandgap,since the nonlinear component (INL) is zero. At highertemperatures, the resulting behavior is similar to thatof the lower temperatures, but the operation is not.The nonlinear behavior of INL attempts to cancelnon-linearity of IVBE . Therefore, addition of AIVBE ,BIPTAT, and CINL gives the curvature correctionoperation as shown in Figure 19(d). The measuredresults show that the achieved accuracy is less than20 ppm/�C and minimum operable supply voltage of1.1 V.

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    Figure 19. (a) and (b) Generation of the nonlinear current component. (c) and (d) Temperature dependence of thecurvature-corrected bandgap reference.

    7.4. Curvature correction - by Malcovati's:2001

    The circuit proposed by Malcovati et al. [26] is shownin Figure 20. It is one of the classic voltage referencesfor curvature correction. Di�erent values of VBE can beobtained by di�erent temperature-dependent collectorcurrents. In this circuit, Q2 is biased by a PTATcurrent:

    VBE2 =VBG(Tr) +TTr

    [VBE(Tr)� VBG(Tr)]

    + (� � 1)kTq


    �; (33)

    Figure 20. Schematic of the proposed bandgap circuitwith curvature compensation by Malcovati.

    while Q3 is biased by a temperature-independent cur-rent and VBG is bandgap voltage of silicon:

    VBE3 =VBG(Tr) +TTr

    [VBE(Tr)� VBG(Tr)]

    + �kTq


    �: (34)

    A non-linear current INL, which is the current owingthrough R4, is generated and given by:

    INL =VBE2 � VBE3



    �: (35)

    Therefore, VREF is given by:

    VREF = (I1 + I2 + I3)R3


    VT ln(N)+R3R2

    VBE2� R3R4VT ln�TrT


    When the easy-control resistor ratio R2=R4 = ��1, thenon-linear voltage in VBE;2 is canceled. A theoreticalzero TC VREF can be obtained. However, it cannotalways be achieved due to the non-ideal PTAT andtemperature-independent currents from the tempera-ture dependence of resistors. In addition, errors due tomismatch of current mirrors worsen the accuracy.

    The proposed bandgap reference circuit by Mal-covati et al. was fabricated in a 0.8 �m Bi-CMOStechnology. It achieved a temperature coe�cient of7.5 ppm/�C. The line regulation was 212 ppm/V,with a power consumption of only 92 �W at roomtemperature.

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    7.5. Brief discussion of curvature correctiontechniques after 2001

    In 2003, Leung et al. [24] presented a low-voltageCMOS high-order curvature compensated bandgap ref-erence based on a temperature-dependent resistor ra-tio. The proposed bandgap reference utilizes the nega-tive temperature-coe�cient high-resistive poly resistorin the CMOS process and the positive temperature- co-e�cient di�usion resistor to implement a temperature-dependent resistor ratio. This resistor ratio can ef-fectively reduce the temperature drift of the bandgapreference voltage. The achieved temperature coe�cientis 5.3 ppm/�C at a 2 V supply voltage, which consumes23 �A current. In 2005, Mitrea et al. [27] proposed acurvature-correction technique based on compensationof the base-emitter voltage nonlinearity, using it tocorrect the drain current of a MOS transistor workingin weak inversion. Cancellation of the �rst- and second-order terms of the polynomial expansion of the base-emitter voltage allows the reduction of the temperaturecoe�cient of the bandgap reference. The measuredtemperature coe�cient is about 10.5 ppm/�C overa temperature range of 10�C to 90�C, while powerconsumption is subtly at higher side, i.e. � 1:4 mW.In 2006, Ker and Chen [28] proposed a curvature-compensation technique, which had two output ref-erence currents. These currents were generated bytwo current-mode bandgap references (the similar ar-chitecture to that of Leung and Mok in 2002 [7]).Both currents acted with concave and convex curves.Addition of these curves gave curvature compensatedperformance. The experimental results showed thatthe minimum operable supply voltage was 0.9 V andthe output reference voltage was 536.7 mV with atemperature coe�cient of 19.55 ppm/�C from 0�Cto 100�C. In 2010, Guan et al. [29] presented anadvanced version of Malcovati's design. They usedcurrent-mode curvature compensation technique. Thecircuit delivered an output voltage of 1.09 V andachieved the lowest reported temperature coe�cientof 3.1 ppm/�C over a temperature range of -20�Cto 100�C. However, power dissipation was 110 �W.Nowadays, many researchers use derived versions of theabovementioned curvature correction technique withminor modi�cations.

    8. Conclusion

    Bandgap/non-bandgap based voltage reference is animportant building block in analog circuit design.Evolution of voltage reference circuits is explicitlyprovided in chronological order to build-up a better un-derstanding of reference circuit. We have drafted an in-depth survey of classic and recent reference topologies.The design trend and current design methodologies ofbandgap voltage reference have been discussed. This

    survey will give insight to designers while buildingvoltage references.


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    Vinayak Hande received PhD degree in ElectricalEngineering from Indian Institute of Technology Bom-bay (IIT-Bombay), India, in 2015. Before joiningthe PhD program, he worked in GDA TechnologiesLimited, India, as an analog IC designer. After com-pleting PhD, he joined the Department of ElectricalEngineering as an Assistant Professor at Indian Insti-tute of Technology Ropar (IIT-Ropar). His researchareas include analog and mixed-signal circuit designfor noise-tolerant system design.

    Maryam Shojaei Baghini received MS and PhDdegrees in Electrical Engineering from Sharif Univer-sity of Technology, Tehran, Iran, in 1991 and 1999,respectively. In between, she worked in the industry assenior analog IC design engineer. In 2001, she joinedIndian Institute of Technology Bombay (IIT-Bombay)as a post-doctoral fellow, where she is currently a pro-fessor in the Department of Electrical Engineering.Dr. Maryam Shojaei Baghini is author/co-author ofmore than 160 international journal and conferencepapers, inventor/co-inventor of 7 granted US patentsand one issued Indian patent, and inventor/co-inventorof 34 more �led patent applications. She is also joint-recipient of 10 awards. She has served in technicalcommittees of many conferences, including IEEE A-SSCC, for several years. Her research areas includeanalog, mixed-signal, and RF circuit and system designfor emerging applications; instrumentation and low-noise circuit and system design for sensor applications;device-circuit co-design; and energy harvesting.