IEEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986

A Survey of Multivalued MemoriesDAVID A. RICH, MEMBER IEEE

Abstract- Techniques of storing multiple bits of information ina single memory location are reviewed. Any of several states canbe stored in ROM's by adjusting the threshold voltage or the sizeof a particular memory device. In dynamic RAM's, this can beachieved by varying the charge-stored on the cell capacitor. Theperipheral circuitry required to distinguish between the statesstored in the memory areas is discussed.

Index Terms -Multivalued logic, random access memory,read-only memory.

INTRODUCTION

T HE traditional way to achieve high-density memorieshas been to shrink the memory's cell size by developing

advanced processes which allow the use of smaller geometrydesign rules. An alternative approach to increasing density,which will be reviewed in this paper, is to encode multiplestates of information in a single memory cell. Conventionalmemories store one bit of information in the memory cell astwo states. These states correspond to the presence (absence)of a transistor in the case of a ROM or the presence (absence)of charge in a storage capacitor in the case of a dynamicRAM. If the number of states in a single memory cell isdoubled, then the storage capacity of the memory cell isdoubled, i.e., four states represent two bits of information.

In the case of ROM's, the states can be encoded into amemory cell by varying the threshold voltage (the minimumvoltage which must be applied to the gate of a transistorbefore the device will turn on) of the memory transistor or byvarying the transistor's length to width ratio in order tochange its current gain. For RAM's, the amount of chargestored in the memory cell capacitor is varied. Novel periph-eral circuitry is required to retrieve the information stored insuch a cell. In this paper we will first examine the design ofmultistate ROM's and then examine the case of multistateRAM's.

MULTIPLE STATE ROM CELLS

Fig. 1 shows the layout of a conventional ROM matrix.The memory matrix, also referred to as the array, is thesection of the memory where the encoded data are stored. Theword lines (rows) drive the gates of the memory devices. Thesources of the memory devices are grounded and the drainsof the devices are connected to the bit line (columns) of thematrix. Thus, all the devices attached to a given bit line areconnected in a NOR-like structure. When a particular memorylocation is to be addressed, its word line is pulled high by the

Manuscript received May 5, 1985; revised August 21, 1985.The author was with General Instrument Corporation, Hicksville, NY. He is

now with the Department of Electrical Engineering, Polytechnic Institute ofNew York, Farmingdale, NY 11735.IEEE Log Number 8406755.

3] T L NE

B B

GLP, INEI N E

K E Y

---

mLORPD L IN E

- - -DI FAUN aN- PE L Y

- ON T AC 1

ME TAL--- RDM YPLAt

v AN T Tts A -I1 FV4

Fig. 1. Layout of a standard ROM matrix programmed by selective ionimplantation.

row decoder and its column is connected through a columndecoder to a sense amplifier which determines the state of thecell by the presence (absence) of current flow in the bit line.Current flows if a normal enhancement transistor (with arelatively low threshold voltage) is present at the addressedlocation. If however, the transistor at that location has beenprogrammed by having its threshold voltage raised above theword-line voltage, then the transistor is always off; evenwhen it is selected, no current flows [ 1 ]. The simplest methodto create this programmed transistor is to disconnect the drainof the transistor from the bit line.The ROM organization of an 8 bit/word ROM is shown in

Fig. 2. From this figure, it can be seen that the columns of theROM matrix are divided into 8 sections. Each section has acolumn decoder, sense amplifier, and output driver. One bitof data is available from each section for each address input.Thus, this configuration gives an 8 bit word output for eachaddress input. As an example, an 8K x 8 (64K) ROM wouldhave 256 rows and 256 columns with the columns dividedinto 8 sections of 32 columns each.The encoding of multivalued data in the ROM matrix is

more complicated than encoding a binary ROM and there aretwo basic methods by which multiple values of data can bestored in the ROM matrix transistor. The first of these meth-ods is to vary the threshold voltage. The threshold voltage ofa MOS transistor can be changed by ion implantation ofdopant atoms into the substrate of the channel of the transis-tor. For n channel devices, p type ions (boron) raise the thresh-old and n type ions (phosphorous) lower the threshold[1]. This method has been used in two state ROM's to encodethe bit positions in the matrix. A high-dose boron implant isused to achieve a transistor with a threshold greater than theword line. This method requires the introduction of an addi-tional mask step into the process, which determines whichtransistors in the ROM matrix are to receive the boron im-plant (Fig. 1). In a four-state ROM, four different memorytransistor thresholds are required. An example of one combi-nation of implant sequences, which results in four different

0018-9340/86/0200-0099$01.00 © 1986 IEEE

99

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986

Ir

I I1OUTPUT DRIVRS

SENSI I M

I I SEN= IMCOLUNSECODECOLUMN DECODER

31T LI NP

-I I ,, I I I' s

RO RTIXIOWROM MATRIX DECODER

DRIVER

II I II

VSS

Fig. 2. Organization of a standard ROM.

memory device thresholds, uses two mask steps, a low-doseboron implant yielding a threshold of 2.2 V, and a high-doseboron implant with a resulting threshold of 3.2 V. The com-

bination of both implants results in a threshold of 4.1 V andthe use of neither implant results in a normal enhancementthreshold of 0.7 V (Fig. 3) [2]. In Fig. 3, the E0 (E3) devicerepresents the device with the lowest (highest) threshold.

This method requires an additional mask and an additionalimplant step when compared to the processing of a two-stateROM program using the ion implant technique previouslydiscussed. Extra implanting steps may be eliminated by usingimplant steps from other parts of the wafer manufacturingprocess for matrix encoding. The disadvantage of this ap-

proach is that the number of masking steps used in pro-

gramming the ROM code is increased [3]. The method alsorequires ROM programming to occur early in the process.The resulting increase in turnaround time for ROM manu-

facture is a drawback to ion implant programming. The major

advantage of this approach is that the cell size is the same

as a two-state ROM. This means a full 50 percent reductionin matrix size is possible for a four-state ROM using thisapproach.The alternate method of programming multiple bits in a

ROM is to adjust the length to width ratios of the transistorsin the ROM memory array. This length to width ratio deter-mines the amount of current that can flow through the deviceand this current value can be measured to determine the typeof device at the selected location. This variable device cell isoften called a geometry-variable cell. It is possible to adjustthe width of the device by varying the geometries of thediffusion mask alone [4]-[6] [Fig. 4; DO (D3) device rep-resents the device with the largest (smallest) width] or byvarying the channel length alone [7]. The latter allowsprogramming using only the polysilicon mask which occurs

later in the process. Programming on the polysilicon maskreduces the time between receipt of an order and shipment offinal product because the part of the manufacturing processwhich takes place prior to the polysilicon layer can occur

before the ROM code is available. This approach is sensitiveto geometric variations in the process at the ROM encod-ing step and also it prevents a full 50 percent reduction in

ADDRESSBUFFERS

W E Y

m-- - DI F F U 5I G N

- F U2 L Y

-- N T ACT

- ME T AL

--- BDR LON

i MP L AN T #- - - B LIR N

...L ! E 3 IMPLANT # 2

Fig. 3. Layout of a multivalued ROM matrix programmed by multipleselective ion implantations.

BI T L[ NE

D 2

R O U N D

LI NE

-. ji. -4,-410L

W O R DLI NE

L

D 0 D 3

Fig. 4. Layout of a multivalued ROM matrix programmed by varyingmemory cell channel width.

memory matrix size since some devices must be larger thanthe minimum cell size.

DETECTION OF MULTIVALUED DATA

Direct Current Sense Approach

The most direct method of detecting the type of device ina matrix is to sense the amount of current drawn through thebit line when a particular memory cell in the matrix is ad-dressed. The simplest method to sense current is to place a

resistor in series with the selected bit line and measure thepotential drop across the bit line. This drop is proportional tothe amount of current being drawn by the selected memorydevice. The current flowing in the bit line decreases with thesquare of the threshold voltage and increases linearly withthe width to length ratio of the transistor as seen from theMOSFET drain current equation:

WK'

ID 2L {VGS VT}2

where K' is the normalized gain of the transistor (K' =A,)and VGS equals the word line voltage which is usually the supplyvoltage. The voltage on the side of the resistor (R) connectedto the bit line is given as:

VR= VDD -IDR.

The voltage across the transistor is then compared to a

reference voltage to determine which device type is presentin the matrix. This reference voltage can be preset based on

the expected range of current each device will generate over

the full operating voltage, temperature, and processing varia-tions expected for a given design. The problem with thisapproach is that the spread between device types must be

100

%

-------9----I

: El..

-;

RICH: MULTIVALUED MEMORIES

made wide to ensure that the reference voltage falls betweenthe voltage generated by the two matrix device types. Abetter approach is to generate the reference voltage fromdevices in the matrix itself. This is accomplished by placingan extra column of each device type in the matrix and gener-

ating the reference voltage by placing a resistor in each of thereference bit lines as was done for the memory array bit linecarrying program data. The voltage of each of the referencecolumns is compared to the voltage at each matrix columnresistor.The system diagram of a direct current sensing four-state

ROM with an 8-bit wide output is shown in Fig. 5. Thecolumns of the ROM matrix array are grouped into foursections instead of the 8 sections of the two-state ROM ofFig. 2. The columns have to be divided into only 4 sectionsin a four-state ROM since two bits of information are encodedinto each memory cell and the data on the single selectedcolumn can be decoded to give two of the 8 bits of data whichare to be available for each address input. As an example, an

8K x 8 (64K) ROM would have 256 rows and 128 columnswith the columns divided into four sections of 32 columns each.As can be seen from Fig. 5, three comparators are required

for each selected column since three reference voltages are

needed to uniquely distinguish between the four cell types.For the system in Fig. 5 to work properly, it is necessary toprevent the reference voltages from being equal to a voltagewhich could be generated by a programmed matrix device.This is accomplished by introducing a voltage offset betweenmatrix and resistor voltages. This offset can be introduced inthree ways: 1) the value of the current sensing resistor in thecolumn can be made slightly different in value from theresistor in series with the matrix device, 2) the comparatorscan be designed to have an internal fixed offset voltage or

3) the width to length ratio of the reference cells can be setto fall between the sizes of the program devices (in the case

ofmemory cells encoded by the geometric variation method).Care must be taken in establishing the offset voltage to pre-vent it from becoming large enough to cause false errors inthe detection process.An example of the system operation will clarify the con-

cepts previously discussed. The ROM matrix can containfour device types which are designated DO, D 1, D2, and D3,with the DO (D3) device sinking the most (least) current in thebit line. The device type placed in a given location in theROM matrix is dependent on the 2 bit data to be encoded inthat location. The reference columns contain DO, D 1, and D2devices and it is assumed that a positive offset voltage isintroduced in these references by one of the three methods.Each of the three reference voltages V2, V1, and VO are

compared to the voltage produced by the memory matrixdevice. The resulting outputs Q2, Q1, and QO are then de-coded to produce the two output data bits stored in the de-vice. For example, suppose the selected device is a type D2.The voltage V2 will be higher than that produced by any

memory device except a type D3. Consequently, the corre-

sponding output (Q2) will be low. The voltage V1 will belower than that produced by a type D2 or D3 device, buthigher than the voltage produced by a type DO or D I device.Hence, the corresponding output (Q 1) is low. The voltage VO

VDD

V2

VI

IvOUTPUT DRIVER I I IBiIBO I I IIDECODER 1 I I

vo

Q21 Q1 QO

Iz4

\

VDD

ILOA

II III

PARATORScoI

COLUMN DECODER

ADDRESSBUFFER

1. 1. ., 5.II ~~~II EOE

z v ROWROM MATRIX

A: A__ DRIVER

Q~ Z; 00 0~~~~

I1vss

Fig. 5. Organization of a 4-state ROM using direct current sensing.

TABLE ISTATES OF COMPARATORS AND DECODED BINARY-CODED OUTPUT FOR EACH

MATRIX DEVICE TYPE FOR SYSTEM IN FIG. 5

ROMDevice Q2 Q1 QO B11 BO

D3 0 0 0 0 0D2 0 0 1 0 1Di 0 1 1 1 0DO 1 1 1 1 1

will be lower than that produced by all devices except thoseof type DO. A type D1 memory device will force the corre-

sponding output (QO) high. The 3 bit code from the com-

parator (00 1) is converted to the 2 bit code (0 1) by thedecoder as shown in Fig. 5. Table I shows the possible rela-tionships between the matrix device types (DO-D3), the com-parator outputs (Q2-QO), and the decoder outputs (B 1 andBO). The Boolean equations which describe the logic in thedecoder are:

Bl = Q2

B2 = Q2 + QlQO.

The choice of relationship between the Q's and the B's isarbitrary and other decoder realizations could be chosen.

In practical implementations of the direct current sensingscheme, a resistor is not used as the load device because it isdifficult to implement a resistor in a standard MOS process.If a CMOS process is used, the resistor can be replaced by a

p channel device which is biased into the linear region. If an

NMOS process is used, a multiple transistor circuit can beused to generate an output voltage proportional to the currentflow in the column. Details of this circuit are given in [4],[8], and [9].

101

1EEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986

The direct current sense approach has been used in ROM'swhich are programmed by the geometric cell variationmethod [4]-[7]. This method is usually not practical forROM's which are programmed using ion implantation tech-niques. This is because the current between encoded states inthe ion implanted approach varies with a square law re-lationship instead of the linear relationship exhibited by thegeometric variation approach. For the ion implanted ap-proach, it is more desirable to sense the threshold of thematrix transistor directly since the change in threshold be-tween encoded states is approximately linear.To date, the largest device developed using direct current

sensing and geometric cell variation programming is256 kbits [7]. The typical access time of this chip is 200 nswith a 1000 ns cycle time.

Threshold Detection Using Ramped Word Line [3]A system which directly senses the threshold of the MOS

devices in a ROM memory array is now discussed. Thissystem operates to distinguish between the threshold of thedevice in the memory array by turning each matrix devicewith a different threshold on individually at different pointswith respect to a timed reference. This is accomplished byramping the word line from 0 V to 5 V. Once a device is turnedon, the sense amplifier detects current flow on the bit line andthe output of the sense amplifier changes state from a zero toa one. Consequently, the type of device can be determined bythe length of time it takes for the word line to rise to the pointwhere the sense amplifier switches. The sense amplifier used inthis system is similar to that found in two-state ROM's since itmust detect only the presence of current flow in the bit line anddoes not need to determine the magnitude of this current.A system diagram of this approach is shown in Fig. 6. In

this example, as was the case for the direct current senseROM (Fig. 5), the columns are grouped into four sections.Each group of columns enter a column decoder and the outputof each column decoder is connected to a sense amplifier. Thememory cells in the memory matrix each contain two bits ofinformation encoded by the choice of the four availablethresholds. Thus, by dividing the ROM's columns into4 sections, eight bits of data are available from the output ofthe ROM. The four device types in the matrix are defined EO,El, E2, and E3 where EO is defined to be the lowest thresholddevice and E3 the highest. There are three reference columnsconsisting of EO, El, and E2 devices. Each reference columnis directly connected to a sense amplifier. The output from thesense amplifiers on the reference columns are then delayed bya value t. After passing through the delay stages, the signalsare used to clock the three latches in each of the 4 sections ofthe ROM.The output of a sense amplifier is connected to the data

input of each of the three latches. Data are latched by atransparent latch when the reference lines go high. The datathat each latch has at the end of the word line ramp depend onthe type of device that has been addressed in the memorymatrix. If the device in the memory matrix has a thresholdgreater than the threshold of the reference device, then thelatch associated with that device will store a "0" since the

ivss RAMP E

RAPGENERATOR RAMP ON

(STARTREAD)

Fig. 6. Organization of a 4-state ROM with threshold detection usingramped word line voltage.

V

E2 TURNON

El TURNON

EO TURNON

wCl

,V}En

0.H

I}P4

< < 4:_ > e

:I oI ).1 4: 4:

Fig. 7. Timing relationships of a 4-state ROM using a ramped word line.

value on the latch's data input had not yet risen to a "1" atthe moment it was clocked. Fig. 7 graphically shows the tim-ing relationships of this system. The output of the latches L3,L2, and L1 are, respectively, denoted as Q2, Q1, and QO.

As an example of this system's operation, suppose that anEl memory device is addressed in the matrix. Since thethreshold voltage of the EO reference is lower than that of anEl memory matrix device, the memory device will turn onafter the EO reference turns on. Thus, the EO reference clocksthe LI reference latch before the El memory device candeposit a "1" on the LI's data input, causing a "0" to appearon the QO output. Although the El reference has approxi-mately the same threshold voltage as an El memory device,the reference device is delayed slightly, giving time for any

102

RICH: MULTIVALUED MEMORIES

El memory device to place a "1" on the L2 latch. A "1,"therefore, appears at the Qi output as well. The thresholdvoltage of the E2 reference is higher than that of an Elmemory matrix device. Thus, the memory device will turn onbefore the E2 reference does, providing a " 1" at the data inputof the L3 latch before the L3 latch is clocked. This results ina "1" at the Q2 output. A summary of the possible states thelatches may assume are given in Table II. The three-bit codein Table II is converted to the desired 2 bit binary code BIand B2 by the decoder circuit as described above. After theE2 reference line has gone low and Q3 has been latched,the system can be reset. The reset pulse is derived from thesystem itself by again delaying the E2 reference line. Duringreset, the binary coded data (B 1, BO) is latched to the outputbuffer and the ramp signal resets as shown in Fig. 7. Bringingall word lines low during reset puts all reference lines at a"0," and resetting the data latches.

The access time of the system is primarily controlled by theramp speed. The rate of rise of the ramp is limited by theability of the peripheral circuitry to distinguish each devicetype in the memory matrix. As an example, if the ramp is toosteep, an El device in the memory matrix may trigger thesense amplifier before the EO reference pulse arrives. An-other source of error results from the resistive word linewhich has a large, distributed capacitance to ground. Thiscauses the word line to behave like a transmission line. Theword line rises quicker near the row driver than it will atthe opposite end of the row. This delay is usually not signifi-cant in two-state ROM design or in the direct current senseapproach (described above). It is significant, however, whenthe ramp technique is used since the system is dependent onthe relative delays between the reference stages and the de-vices in the matrix. The word line moves faster near the rowdecoder and hence the bit lines closest to the row decoder willcharge more quickly than the bit lines further away from therow decoder. Since the reference devices are a fixed distancefrom the row decoder, it is possible for a reference device tocome up too late (or early) in relation to the selected bit line,resulting in a detection error. In the implementation of thesystem just described, the polysilicon word line was replacedwith a metal word line which does not suffer from this trans-mission line effect. To date, the largest device implementedhas been a 128 kbit device. The die size was 208 x 213 milsin 6 Am metal gate technology. A smaller 40 kbit device hada worst case access time of 500 ns.

Threshold Detection Using Source-Follower Configuration[2]

Another approach to sensing the threshold of a MOS de-vice in the ROM memory matrix is to use a source-followerconfiguration. The organization of the matrix and referencecolumns, shown in Fig. 8, is the same as in the previousexample with the columns grouped into four sections, re-sulting in an 8 bit/word output. However, the memory matrixdevices are wired in a source-follower configuration by con-necting the drain of all the devices in the memory matrix toVDD, and by connecting the source of each device to the bitlines which are routed through the column decoder to the

TABLE IISTATES OF DATA LATCHES AND DECODED BINARY-CODED OUTPUT FOR EACH

MATRIX DEVICE TYPE FOR SYSTEM IN FIG. 6

ROMDevice Q2 Q 1 QO B I BO

E3 0 0 0 0 0E2 0 0 1 0 1El 0 1 1 1 0EO 1 1 1 1 1

VDDFig. 8. Organization of a 4-state ROM with threshold detection using a

source-follower configuration.

comparators. In a source-follower configuration, the bit linecan go no higher than a threshold below the power supply.Thus, it is possible to make a direct comparison between thefinal voltage of the column decode output and the final volt-age of the reference column. The problem with this directapproach is that the bit lines will charge to their final voltagevery slowly. The reason for this is that the matrix device,which is pulling up the bit line, is slowly being turned offsince the voltage between its gate (the word line voltage) andits source (bit line voltage) is decreasing. The magnitude ofthis gate to source voltage is proportional to the amount ofcurrent the MOS device can conduct. Thus, this current de-creases as the bit line is pulled up, and eventually goes to zeroas the bit line voltage approaches one threshold drop belowthe word line voltage. To decrease the access time of a mul-tivalued ROM using this source-follower approach, one cansample the voltages on the bit line and reference line beforethe final bit line values are reached. This is achieved by firstpulling the selected bit line and the reference lines to zero(VSS = 0) through an enhancement device shown in Fig. 8.At the start of a read operation, these enhancement devicesare turned off, allowing both the bit lines and reference lines

103

1EEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986

to begin to rise. The data from the output of the comparatorsare latched by the output drivers at a specified time t after theconversion cycle has been initiated. If this approach is taken,the differential voltage between the different matrix deviceswill be reduced (as shown in Fig. 9), making the sensingdecision vulnerable to noise on the bit and reference lines.The voltage differences between the reference voltages andthe matrix voltage are created by incorporating a fixed inter-nal offset between the two inputs of the comparators.The approach of making a decision before the bit lines have

settled is also vulnerable to the previously discussed wordline delay problem. This is because the rate of rise of aselected bit line in the memory matrix array is dependent onits distance from the word line. It is thus possible for thematrix bit line voltage to cross the adjacent reference linevoltage. One solution to this problem, which has been usedin the implementation of this system, is to use multiple refer-ence columns spaced appropriately across the array. Each setof references is placed close enough to the set of bit lines towhich the reference set will be compared, to ensure that theword line delay difference across the set of bit lines andreference lines is not large enough to cause a detection error.These additional reference columns will increase the size ofthe matrix array; the penalty, however, will not be significantprovided the number of additional reference columns is smallin comparison to the number of columns in the memory array.A 64K device with a die size of 171 x 155 mils was imple-mented using this system.

MULTIVALUED RAM [10]

A dynamic RAM cell can also be used to store multiplevalued data [10]. In a two-state dynamic RAM the presenceof a bit is represented by a voltage stored across a capacitorin the memory matrix. If no voltage is present across the ca-pacitor, then the capacitance memory element holds a valueof zero. The two-state RAM cell is addressed by turningon a transistor in series with the capacitor (Fig. 10). The gateof this device is connected to the word line, the drain is-connected to the bit line, and the source is connected to thecapacitor. In a RAM, unlike a ROM, data must be writteninto a memory matrix before it can be read. The WRITE opera-tion in a dynamic RAM cell is accomplished by selecting abit line and bringing a word line high. If the bit line is low,the capacitor will discharge through the series transistor (withsource acting as drain) into the bit line and a "0" will bewritten into the capacitor. If the bit line is high, a voltage onethreshold drop below the word line voltage will be storedacross the capacitor and a "1" will be written into the capaci-tor. To read the RAM, the word line is brought high (as in theWRITE operation) and charge from the capacitor is transferredonto the bit line. Because the capacitance of the memory cellis significantly lower than the capacitance of the bit line,complex voltage sensing is required to determine if a one ora zero has been read from the addressed location [11].

In a multivalued RAM, the amount of voltage placedacross the capacitor is varied to represent the multiple states.The combination of the capacitor and the pass transistor ofthe memory cell may be thought of as a single transistor with

BIT VDDLINEVOLTAGE

VT3

VT2

VT I

VTO

I----

DECI SIONPOINT

E3

t-- - E2

- El

-.EO

t TIME

Fig. 9. Family of bit line response curves for a ROM matrix configured as asource-follower.

BIT LINE

Fig. 10. Circuit diagram of a single-transistor dynamic RAM storage cell.

a threshold which can be controlled by varying the voltageplaced across the capacitor. Using this analogy we will see

that the READ operation for a multivalued RAM is similar toone of the techniques used in multivalued ROM's.The WRITE operation (Fig. 10) in a multilevel RAM is ac-

complished by initially lowering the bit line, bringing theword line of the selected row high, and then stepping theword line fromn its maximum voltage through a descehdingstaircase of voltages. The rate of descent is controlled by a

timing generator, and since the bit line for the selected col-umn is initially low, the capacitor discharges (with source

acting as drain). When the bit line (connected to the drain ofthe series transistor) is brought high, the voltage written intothe capacitor is one threshold drop below the present value ofthe word line voltage. By bringing the bit line high at the rightmoment, we can store any of several unique values across thecapacitor, each exactly one threshold drop below the currentstep level of the word line voltage.As an example, we consider a four-state RAM whose word

line will step through four descending voltages (+X3 through+XO). Each of these voltages represents one of the four com-binations possible from two binary bits. If the highest voltageis to be written into the cell, then the bit line is brought upimmediately. The next highest voltage is written into the cellby delaying the time that the bit line is brought high by one

WORD LINE

STORAGE ,.-rCAPACITOR

vSS

104

RICH: MULTIVALUED MEMORIES

TIMlING F RAMP -2CONTROL DRIVER

4 START WRITE

Fig. 11. Organization of a 4-state multivalued RAM in the write mode.

clock interval. Thus, the voltage written into the memorycapacitor is now equal to the voltage of the word line at itssecond step minus a threshold drop. This process continuesfor the last two bits by further delaying the rise of the bit lineuntil the word line descends to the required voltage to bewritten into the memory. The bit line, once raised, need notbe lowered since subsequent lower word line voltages willturn off the charging transistor without effecting the memorycapacitor's charge. The logic which controls the bit line isshown in Fig. 11, as is the overall system configuration of theRAM in the write mode. The two-bit input data are latchedand converted by a decoder circuit into a four-bit code asshown in Table III. This code is sent to the bit line controllogic which, under the control of the sequential timing sig-nals 4W3 through 4W0, determines when the bit line is to bebrought high. The timing signals 4W3 through 4W0 comefrom the timing generator which also controls the ramp de-scent rate.

During the READ operation of a four-state RAM (Fig. 10),the word line is stepped from its lowest value (¢X0) to itshighest value (¢X3) in an ascending staircase pattern. Whenthe value of the word line exceeds the capacitor voltage of theselected memory cell by a threshold, the cell device con-ducts, lowering the bit line and the sense amplifier switches.The time when the sense amplifier switches determineswhich state had previously been written into the memory cell.One can see tbe similarities of this READ operation with theramp word line technique for ROM's discussed above. Thedifference is that it is not necessary to use references togenerate the timing control signals as was done for the caseof the ROM. This is shown in the system diagram of the RAMin the read mode (Fig. 12). This is because the voltage which

Fig. 12. Organization of a 4-state multivalued RAM in the read mode.

TABLE IIICODE CONVERSION PERFORMED BY WRITE LoGic DECODER IN

DYNAMIC RAM

Il I0 C3 C2 C1 Co

O 0 0 0 0 1O 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0

was written into the memory cell of the RAM was producedby the same ramped word line that is being used in the READoperation, and the threshold voltage of the memory cell in theRAM is fully determined by the word line voltage. As seenin Fig. 11, the control signals (4R3-4RO) for the data latchescome from the same timing generator that controls the rampascent rate.

After a memory cell has been read, the data in that cell aredestroyed since any charge in the storage capacitor is trans-ferred to the bit line. The data in the storage cell will alsodecay due to leakage in the diffused junctions to which thecapacitor is connected. Both these effects result in a require-ment for rewrite logic in a dynamic RAM. A simple circuitis described in [10] which combines the latches used in theREAD and wRrrE operations allowing the rewrite operation tooccur without additional logic overhead.A 4 kbit memory using the system just discussed has been

implemented in silicon. This memory is a 16-level designallowing four bits of information to be encoded into one cell.This 4 kbit memory is intended to be a test circuit for a 4 MbitRAM, which is expected to have an access time of50-100 ,s. The authors of [10] have found the limit on thestaircase pulse step size to be in the range of 100-120 mV, ifacceptable detection error rates are to be achieved. The prin-

105

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-35, NO. 2, FEBRUARY 1986

cipal limiting factor of the staircase pulse step size is thesubthreshold leakage of the memory cell transistor.

CONCLUSION

The methods to encode multiple states of information in amemory matrix have been discussed. Four state ROM's ofdensities as high as 256 kbits have been developed. A16-state dynamic RAM, which is a test vehicle for a 4 Mbitdynamic RAM, has also been discussed. The novel periph-eral circuitry which determines which of the n states has beenread from a particular location in the memory matrix has beendescribed. The principle tradeoff for the increased matrixdensity is an increase in the memory's access and cycle time,due to the more complex peripheral circuitry. Yields of mostof the multivalued devices have been comparable with two-state devices of similar sizes. Multiple state memories willbecome increasingly attractive as the cost of developing newprocesses to reduce design rule geometries becomes in-creasingly expensive.

[4] M. Stark, "Two bit per cell ROM's," in Proc. IEEE COMPCON, Spring1981, Feb. 1981, pp. 209-211.

[5] J. Bayliss et al., "The interface processor for the intel VLSI 432 32 bitcomputer," IEEE J. Solid-State Circuits, vol. SC-16, pp. 522-530, Oct.1981.

[6] D. Etiemble, B. Nathegi, and J. Erlich, "A four-valued IK ROM de-signed with Lamda-rules," in Proc. 15th Int. Symp. Multivalued Logic,Kingston, Ont., Canada, 1985.

[7] B. Donahue, P. Holly, and K. Ilgenstein, "256K HCMOS ROM using afour-state cell approach," IEEE J. Solid-State Circuits, vol. SC-20,pp. 598-602, Apr. 1985.

[8] E. Lavelle and D. Etiemble, "Improved sense amplifier for 4-valuedROMS," in Proc. 14th Int. Symp. Multivalue Logic, Winnipeg, Canada,1984.

[9] V. Agarwal, J. Pugsley, and C. Silio, "Multiple-valued ROM outputcircuits," in Proc. 14th Int. Symp. Multivalue Logic, Winnipeg, Canada,1984.

[10] M. Aoki et al., "A 16-level/cell dynamic memory," in ISSCC Dig. Tech.Papers, pp. 246-247, 1985.

[11] K. Stein, A. Sihling, and D. Oering, "Storage array and sense/refreshcircuit single-transistor memory cells," in Digital MOS Integrated Cir-cuits, M. Elmasry, Ed. New York: IEEE, 1981, pp. 310-314.

ACKNOWLEDGMENT

The author wishes to thank J. Lakos and R. Doino for theirhelpful suggestions and assistance in preparing this paper. J.Virzi and S. Morley are also thanked for their careful reviewsof this paper.

REFERENCES

[1] D. Hodges and H. Jackson, Analysis and Design of Digital IntegratedCircuits. New York: McGraw-Hill, 1983.

[2] R. Adlhoch, "Quaternary ROM design utilizing variable-threshold stor-age cells," in Proc. 15th Int. Symp. Multivalued Logic, Kingston, Ont.,Canada, 1985.

[3] D. Rich, K. Naiff, and K. Smalley, "A four-state ROM using multilevelprocess technology," IEEE J. Solid-State Circuits, vol. SC-19,pp. 174-179, Apr. 1984.

David A. Rich (S'79-M'81) was born on January 7,1958 in Brooklyn, NY. He received the B.S. degreein engineering science from Hofstra University,lHempstead, NY, in 1980 and the M.S.E.E. degreefrom Columbia University, New York, NY in 1981.He is currently pursuing the Ph.D. degree in elec-

trical engineering at Polytechnic Institute of NewYork, Farmingdale. He joined the General Instru-ment Corporation, Hicksville, NY in 1981 and wasengaged in the design of read-only memories. He iscurTently involved in the design of application spe-

cific integrated circuits. His present fields of interest are the design of analogMOS integrated circuits and commnunication electronics.

106