Upload File

a top down approach to mixed signal soc verification

  • Home
  • Documents
  • A Top Down Approach to Mixed Signal SoC Verification
prev
next
out of 15
Download A Top Down Approach to Mixed Signal SoC Verification

Upload: sathish-kumar

Post on 25-Feb-2018

343 views

Category:

Documents


6 download

Report

TRANSCRIPT

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    1/15

    S Bangalore, India

    Insert CompanyLogo Here

    Copyright 2011 Magma Design Automation, Inc.

    A Top-Down Approach toMixed-Signal SoC Verification

    Sudarshanam Kommanaboyina

    Microchip Technology India Pvt. Ltd.

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    2/15

    2 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Agenda

    Challenge Traditional flow to simulate analog, digital blocks

    Mixed-signal simulation Co-Sim observations Feasibility of Finesim for Co-Sim

    Example

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    3/15

    3 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Challenge

    Mixed-signal SoC design Polarity issues at the interface between

    analog and digital blocks Functional issues at the interface Approach suggested to avoid re-spin

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    4/15

    4 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Standalone Analog Simulations

    en

    reset_nstart

    trim[4:0]

    sel[2:0]

    an_in1

    an_in2

    an_in3

    control[4:0] an_out5

    an_out1an_out2

    an_out3

    an_out4

    dig_out3

    dig_out1

    dig_out2

    ANA

    LOG

    NETLIST

    SPICE

    Stimulus from analog testbench

    Stimulus from RTL simulations

    or

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    5/15

    5 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Observations

    Analog stimulus generated from designers with human errors indesign can carry the same perception to analog testbench that mayresult in polarity issuesEg. Control signal polarity getting inverted at the analog-digitalinterfaceStimulus from RTL simulation has controllability and it is possibleto catch the polarity issues

    It is tedious to check the results manually from the above twomethods

    Almost no verification done after integration of standalone blocks (simulated in spice) causing possible functional failuresEg. missing level shifter in multi-supply designs

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    6/15

    6 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Full-Chip RTL Simulations

    en

    reset_n

    starttrim[4:0]

    sel[2:0]

    an_in1

    an_in2

    an_in3

    control[4:0] an_out5

    an_out1

    an_out2an_out3

    an_out4

    dig_out3

    dig_out1

    dig_out2

    RTL

    BLOCK

    1

    BL

    OCK

    2

    ANALOG

    MODE

    L

    B

    EHAVIO

    RAL

    R

    TL

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    7/15

    7 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Observations

    Behavioral models of analog modules used(Verilog/VHDL)Uses full-chip testbench to simulate full-chip RTL +

    analog behavioral modelsBehavioral model may not match with analog spicenetlist since it cannot capture spice device/modelcomplexityGenerates stimulus for standalone analog simulationswhich are then used to run block level spice simsNot possible to catch polarity issues, functional bugs

    at the interface

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    8/15

    8 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Full-Chip Spice Simulations

    enreset_nstart

    trim[4:0]

    sel[2:0]

    an_in1

    an_in2

    an_in3

    control[4:0] an_out5

    an_out1an_out2

    an_out3

    an_out4

    dig_out3

    dig_out1

    dig_out2

    NETLIS

    T

    BLOC

    K

    1 NE

    TLIST

    BLOCK

    2

    ANA

    LOG

    NETL

    IST

    SPI

    CE

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    9/15

    9 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Observations

    Digital gates equivalent spice netlist + Analog spice netlist usedfor full-chip simulation

    Takes weeks to run in true-spice and several days in fastSpice

    Very few test cases are run at this stage, may not be possible tocatch the interface bugs

    No standard verification methodology exists currently confirmingthe verification coverage/closure.

    Bugs caught at this stage may postpone the tapeout

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    10/15

    10 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Full-Chip Co-Sim Simulation

    enreset_nstart

    trim[4:0]

    sel[2:0]

    an_in1

    an_in2

    an_in3

    control[4:0] an_out5

    an_out1an_out2

    an_out3

    an_out4

    dig_out3

    dig_out1

    dig_out2

    BLOC

    K

    1

    BLOCK

    2

    ANA

    LOG

    NETLIST

    SPICE

    RTL

    RTL

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    11/15

    11 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Full-Chip Co-Sim Simulation (Contd)

    RTL + Analog Spice netlist simulationRTL simulation by QuestaSim

    Analog spice simulation by Finesim

    Digital-to-Analog (D2A) & Analog-to-Digital(A2D) interface

    Logic D2A A2D

    1 vdd >vdig1

    0 gnd

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    12/15

    12 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Observations

    Start Co-Sim by plug-and-play analog blocks as and when theblock gets ready, without waiting for all the blocks to get ready

    Compared to full-chip Spice simulation, Co-Sim takes very less

    time to simulate the whole chip as the digital blocks are in RTLformEg. fastSpice Vs spice - ~10-30X

    Cosim Vs spice ~100X

    Functional bugs and polarity issues between analog and digitalblocks can be caught at the early stage of design

    Uses the existing full-chip RTL test bench infrastructure to verifyanalog modules under real conditions

    Feasibility to choose among analog Spice, fastSpice modes,verilogA models all spice or mixed spice+verilogA

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    13/15

    13 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Feasibility of Finesim for Co-Sim

    Features Magma (Finesim)Verilog support Yes

    System Verilog support Yes

    Changes to behavioral models Required/optional

    VerilogA Yes

    VerilogAMS Underdevelopment

    Spice netlist Yes

    All advanced features of Finesim can be used for Co-Sim( multi-cpu simulations, spice mode, fast mode etc)

    Finesim supports all major RTL simulation tool vendors( Modelsim, Ncsim, VCS)

    Finesim has a provision to specify the voltage levels to each pinseparately, supports multi-voltage domain

    Also supports instance based replacement

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    14/15

    14 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Co-Sim Example Using Finesimmodule top;// logic/reg/wire declaration

    test1 inst_test1(.in1 (out1 ),.in2 (out2 ),.in3 (in3 ),.in4 (in4 ),.out1 (out1 ),

    .out2 (out2 ),

    .out3 (out3 ),

    .inout1(inout1),

    .inout2(inout2));

    test2 inst_test2(.in1 (in1 ),.in2 (in2 ),.out1 (out1 ),.out2 (out2 ),.out3 (out3 )

    );initialbegin//{

    //testbench

    end//}initial

    $finesim_config(config.inc);endmodule

    module test2(input logic in1 ,input logic in2 ,output logic out1 ,output logic out2 ,output logic out3);

    assign out1 = in1 && in2;assign out2 = in1 || in2;assign out3 = in2;

    endmodule

    module test1(input logic in1 ,input logic in2 ,input logic in3 ,input logic [1:0] in4 ,output logic out1 ,output logic out2 ,output logic out3 ,

    inout inout1,inout inout2

    );parameter finesim_a2d=avdd";parameter finesim_d2a=dvdd";parameter finesim_d2a$in1="dvdd1";parameter finesim_d2a$in4[1]="dvdd1";parameter finesim_d2a$inout1="dvdd1";parameter finesim_a2d$inout1="avdd1";parameter finesim_a2d$out1="avdd1";initial $finesim_module;

    endmodule

    config.inc.a2d avdd vl=0.9 vh=0.9.d2a dvdd vl=0 vh=2.8 vx=1.4 tr=0.3n tf=0.3n.a2d avdd1 vl=1.4 vh=1.4.d2a dvdd1 vl=0 vh=1.8 vx=0.9 tr=0.3n tf=0.3n.finesim test1.sp.option dump_ie=1.option port_map_by_name=1 bus_format=[%d].option minimize_ie=1

    test1.spvvdd VDD 0 dc 1.8vvss VSS 0 dc 0.global vss vdd.inc ./model.inc.inc finemix.sp*Default name of spice instance netlist file

    .subckt test1 in1 in2 in3 in4[0] in4[1]+ out1 out2 out3 inout1 inout2*Spice netlist.ends test1

    *can specify any number of subckt*or specify paths for other spice netlist

    .option post

    .tran 1p 100ns

    .end

  • 7/25/2019 A Top Down Approach to Mixed Signal SoC Verification

    15/15

    15 Insert CompanyLogo HereCopyright 2011 Magma Design Automation, Inc.

    Q&A

    Note: The Microchip name and logo are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries.All other trademarks mentioned herein are property of their respective companies.


DENSITY MEASUREMENT VERIFICATION FOR HOT MIXED …

Mixed signal verification challenges - slides

Extending Proven Digital Verification Techniques for · PDF fileExtending Proven Digital Verification Techniques for Mixed-Signal SoCs ... Digital Verification Techniques for Mixed-signal

SoC Level Formal Verification - Test and Verification Solutions

SoC Verification HW #2

SoC Security Verification

ARM Based SoC verification v1 - T&VS€¢ ARM based SoC Verification challenges ... • RISC processor cores for portable devices and mobile ... • Pre-empts verification done with

Metrics in SoC Verification - Amazon S3...1 Metrics in SoC Verification Not just for coverage anymore Andreas Meyer and Harry Foster Design and Verification Technology Division Mentor

SoC/ASIC/SoC-FPGA/S-ASIC Design and Verification Methodology · SoC/ASIC/SoC-FPGA/S-ASIC Design and Verification Methodology i n t e l o p Intelop Corporation 4800 Great America Pkwy

Interconnect Verification for SOC - UCLAcadlab.cs.ucla.edu/icsoc/.../ICSOC_03282002_Verification.pdf · --EE NCTU EE NCTU ----~ EDA lab ~ Interconnect Verification for SOC Jing-Yang

End-to-end Verification with Portable Stimulus on a Mixed ......Mixed Signal, Automotive Audio SoC Dual Core DSP SoC with Analog Front -End • Layer PSS effectively into existing

경종민 [email protected] 1 IP & SoC Verification

Zilker Labs Mixed-Signal Verification

SoC Verification Strategies for Embedded Systems Design

System and SoC Verification Trends - T&VS - Cadence - Ni… · System and SoC Verification Trends Nick Heaton, Senior Solution Architect Verification Futures 19th stNov (Windsor),

Approaches for Power Management Verification of SOC

ARM Based SoC verification v1 - Test and Verification … • About ARM and ARM IP • ARM based SoC Verification challenges • Verification planning and strategy • IP Connectivity

SOC Testing - University of Cincinnatiwjone/soc.pdf · SOC testing.26 SOC Testable Design Flow ... Verification SOC Testable Design Rules. SOC testing.27 Conclusions! SOC testing

SoC Level Formal Verification - Test and Verification … Verification and SoC‐Level Verification • Formal verification – Traditionally operates at block level – Focuses on

Simplifying SoC Verification using a Generic Approach Verilab are simplifying SoC verification A self generating eVC for generic SoC verification •Provides automatic bus verification

Accelerated SOC Verification Using UVM … SOC Verification Using UVM Methodology for a Mixed-Signal Low Power Design Giuseppe Scata –Texas Instruments ([email protected]) Ashwini Padoor

Formal Verification of SoC Register Maps · Formal Verification of SoC Register Maps Steve Holloway Principal Verification Engineer Dialog Semiconductor . ... Formal Verification

Addressing SOC/IP Verification Framework Creation with UVM ... · PDF fileAddressing SOC/IP Verification Framework Creation with UVM ... • IP verification using Re-use of IP level

Home - Silicon Service | Custom Software Solutions · VERIFICATION EXPERTISE SOC Verification GPI-I Verification Performance Verification Security Verification METHODOLOGY SV/UVM

SOC verification using SV

ARM Based SOC Verification - Test and Verification … Bartley (TVS... · 7 July 2008 1 Test and Verification Solutions ARM Based SOC Verification Mike Bartley, Avanish Sachan, Abhineet

SoC Verification Methodology - VLSI Laboratory

Rethinking SoC Verification - Synopsys Paper March 2014 Rethinking SoC Verification Enabling Next-Generation Productivity & Performance Rebecca Lipon Senior Product Marketing Manager,

ARM Based SOC Verification - T&VS · ARM Based SOC Verification Mike Bartley, Avanish Sachan, Abhineet Sanghvi, Christdas Test and Verification Solutions . 7 July 200814 March 2013

Mixed Signal Verification Transistor to SoC · Mixed Signal Verification Transistor to SoC. ... — Do not question requirements and specifications, they implement ... include checking

Formal Verification Based Automated Approaches To SOC DFT Logic Verification · 1 Formal Verification Based Automated Approaches To SOC DFT Logic Verification Subir K. Roy Rubin A

Mixed Signal SOC Circuit Design

SoC Verification

Interconnect Verification for SOC

Experimental Verification of Three - Dimensional Mixed