a variation tolerant current-mode signalling scheme for on-chip interconnects

342 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 2, FEBRUARY 2013

A Variation Tolerant Current-Mode Signaling Schemefor On-Chip Interconnects

Marshnil Dave, Student Member, IEEE, Mahavir Jain, Maryam Shojaei Baghini, Senior Member, IEEE, andDinesh Sharma, Senior Member, IEEE

Abstract—Current-mode signaling (CMS) with dynamic over-driving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However,they are sensitive to parameter variations due to reduced voltageswings on the line. In this paper, we propose a variation tolerantdynamic overdriving CMS scheme. The proposed CMS schemeand a competing CMS scheme (CMS-Fb) are fabricated in 180-nmCMOS technology. Measurement results show that the proposedscheme offers 34% reduction in energy/bit and 42% reduction inenergy-delay-product over CMS-Fb scheme for a 10 mm line oper-ating at 0.64 Gbps of data rate. Simulations indicate that the pro-posed CMS scheme consumes 0.297 pJ/bit for data transfer overthe 10 mm line at 2.63 Gb/s. Measurements indicate that the delayof CMS-Fb becomes 2.5 times its nominal value in the presenceof intra-die variations whereas the delay of the proposed schemechanges by only 5% for the same amount of intra-die variations.Measurement and simulation results show that both the schemesare robust against inter-die variations. Experiments and simula-tions also indicate that the proposed CMS scheme is more robustagainst practical variations in supply and temperature as com-pared to CMS-Fb scheme.

Index Terms—Current-mode circuit, dynamic overdriving,on-chip global interconnects, process variation.

I. INTRODUCTION

S PEED and power consumption of on-chip interconnect net-work have become important in advanced CMOS tech-

nologies. It is difficult to meet desired power and performancespecifications of modern system-on-chips (SoCs) and multicoreprocessors with buffer inserted long interconnects [1]. Many al-ternate repeater circuits and signaling schemes have been sug-gested in recent past to achieve high-speed low-power commu-nication over long on-chip interconnects [2]–[18]. In modernCMOS technologies, process variations cause significant varia-tions in device parameters which can lead to performance degra-dation of these signaling techniques. Hence, a signaling schemefor on-chip interconnects is also required to be robust againstparameter variations.We first review the most promising signaling schemes for

energy-efficient communication over long wires. Current-mode

Manuscript received December 07, 2010; revised August 06, 2011 andNovember 18, 2011; accepted January 04, 2012. Date of publication March 07,2012; date of current version January 17, 2013.The authors are with the Department of Electrical Engineering, Indian

Institute of Technology (IIT) Bombay, Maharashtra 400076, India (e-mail:[email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TVLSI.2012.2185835

signaling (CMS) scheme has the potential to improve bothspeed and dynamic power consumption. It consumes muchless power compared to the improved repeater circuits (suchas self-timed repeaters [6] and boosters [3]) and signalingschemes such as near-speed of light communication [7] andtransition-aware signaling [5] as shown in [10]. However,the basic current-mode signaling scheme consumes staticpower and exhibits a direct tradeoff between speed and staticpower. Capacitively coupled driver based low-swing signalingschemes are proposed in [16] and [17]. The capacitivelycoupled driver-based signaling scheme consumes much lessenergy than the basic CMS scheme. Further, the scheme in [17]employs channel equalization technique at the receiver end toimprove eye-opening. This scheme achieves 85% improvementin energy consumption over the buffer insertion scheme for a10 mm line in 90-nm process. We have earlier proposed a CMSscheme with equalization at transmitter end (with dynamicoverdriving) in [18]. This scheme achieves 87% improvementin energy/bit over the conventional buffer insertion schemefor a 6 mm long line in 180-nm process. The scheme is moreefficient for long wires carrying high activity signals thanshort wires carrying low activity signals. Hence the schemeis expected to give more than 87% improvement for a 10 mmline. The dynamic overdriving CMS schemes proposed in[11]–[14] also offer more than 60% improvement in energy/bit.Hence, we have adopted dynamic overdriving CMS scheme forvariation analysis.The huge reduction in energy consumption offered by the

low-swing signaling schemes and the CMS schemes is mainlydue to the reduced voltage-swing on the line. However, lowvoltage swing on the line reduces the noise margin of the datacommunication system. Hence, CMS schemes are more sus-ceptible to parameter variations than the voltage-mode repeaterinsertion scheme. In highly scaled technologies, process vari-ations cause significant variations in device parameters. Thevariations in the transistor parameters can be categorized as ei-ther inter-die variations or intra-die parameters. In the case ofinter-die variations similar devices on a chip have identical elec-trical parameters but the device parameters vary from die to die,wafer to wafer and batch to batch. In modern technologies, vari-ations in the parameters of devices on the same chip are alsosignificant. This class of variations are referred to as intra-dievariations. The variations can cause the voltage swing on theline to change which can lead to significant changes in the per-formance of a scheme.The schemes in [11]–[18] do not discuss the impact of

intra-die and inter-die variations on performance of their

1063-8210/$31.00 © 2012 IEEE

DAVE et al.: VARIATION TOLERANT CURRENT-MODE SIGNALING SCHEME FOR ON-CHIP INTERCONNECTS 343

Fig. 1. CMS scheme with driver pre-emphasis (a) signal waveforms of CMS schemes with driver pre-emphasis (b) CMS scheme proposed in [11] (CMS-Fb) (c)effect of mismatch between of inverters in transmitter and receiver in CMS-Fb scheme.

schemes. Further, the schemes proposed in [12]–[17] do notconsider parametric variations in the designs of the transmitterand the receiver circuits. The transmitter and the receivercircuit of the CMS scheme proposed in [11] employ feedbackwhich makes the scheme less sensitive to inter-die variations.However, this scheme is robust only as long as the transistor-pa-rameters of the transmitter and the receiver are identical. In anSoC, the driver circuit and the receiver circuit of a repeaterlessCMS scheme are quite likely to be in different parts of the chip.In this case, the performance of the scheme proposed in [11]can degrade significantly due to mismatch between transistorparameters in the transmitter and the receiver.In this paper, we propose a dynamic overdriving CMS

scheme that is robust against intra-die and inter-die variations.It also offers significant improvement in delay, energy andEDP over voltage-mode schemes for a wide range of linelengths, data rates and data activity factors. The proposedscheme employs a smart bias circuit in the transmitter whichmakes it robust against inter-die variations. The operation ofthe circuit does not rely on matching of the transistor param-eters of the transmitter and the receiver. In [19] and [18], wehave introduced our basic CMS scheme and showcased itsenergy-efficiency and robustness in 180-nm technology. TheCMS scheme proposed in this paper employs an improvedversion of the bias circuit. With the new bias circuit the pro-posed CMS scheme is more robust against inter-die variations.In this paper, energy efficiency and variation tolerance of ourCMS scheme are demonstrated using measured results from atest chip fabricated in 180-nm technology. Robustness of theproposed scheme over temperature and supply variations isalso discussed in this paper.The remainder of this paper is organized as follows. Section II

describes the principle of operation of a dynamic overdrivingCMS scheme. The scheme proposed in [11] is close to ourcircuit architecturally. Hence, we have analyzed this schemein detail in Section II. We shall refer it as CMS-Fb schemethroughout this work. The transmitter and receiver circuits of

the proposed CMS scheme are described in Section III. Designand implementation details of the test chip are discussed inSection IV. Section V shows performance of the proposed CMSscheme in comparison with CMS-Fb scheme using both simu-lation and measurement results. The schemes are compared forspeed-power-area and robustness against inter-die and intra-dievariations. Section VI presents major conclusions of the work.

II. INTRODUCTION TO CMS SCHEME WITHDRIVER PRE-EMPHASIS

Driver pre-emphasis is the technique of supplying largecurrent/voltage to the line during transitions of input and verysmall current/voltage in the steady state. In the frequencydomain, it means amplifying high frequency components ofthe input signal. Fig. 1(a) shows typical waveforms of voltageand current of a CMS system with driver pre-emphasis. Theline voltage swings around the voltage defined by the receiver.Fig. 1(b) shows the transmitter and the receiver circuits used inCMS-Fb scheme. The transmitter reported in [11] has a strongdriver and a weak driver. The strong driver supplies a large cur-rent to the line during transition and the weak driver providesa small steady-state current to the line. NAND and NOR gatesturn on the strong driver for a short duration. This duration iscontrolled by a feedback inverter [see Fig. 1(b)]. The strongdriver is turned off after the line voltage (at the transmitterend) crosses the switching threshold of the feedback inverter

. At the receiving end, the line voltage is held near[see Fig. 1(a)]. The receiver employs a feedback which

makes the line voltage (at the receiving end) swing around, which is the switching threshold of inverter-amplifier.

The steady-state voltage swing on the line is given by theproduct of the static current supplied by the weak driver andthe small signal input impedance of the receiver. The inverterfollowing the inverter-amplifier takes the output to CMOSlogic levels.This scheme is robust against inter-die variations due to the

feedback in the transmitter and receiver circuits as long as


Fig. 2. Macro model of a dynamic overdriving CMS scheme.

and are the same. However, and are likelyto be different as transmitter and receiver are placed far apart(more than 1.5 mm). Consider a case where is less than

and steady-state voltage swing on the line is less than[see Fig. 1(c)]. In this case, when input is con-

stant “0”, the receiver tries to hold the line voltage atwhich is more than . As a result, the strong driver is turnedon to pull the line voltage below . Once the line voltageis pulled below the strong driver is turned off. However,now as the receiver is suppose to hold the line voltage at ,the line voltage rises to which in turn activates strongdriver. This way voltage on the line swings between and

even if input is constant logic “0” as shown in Fig. 1(c).During “0” to “1” transition in the input, the strong driver isturned off well before voltage at the receiver end has crossed

. During “1” to “0”, the strong driver is active even afterline voltage at the transmitter end has crossed . As a result,delay of the scheme for “0” to “1” transition is more than for “1”to “0” transition. Similarly, if , the line voltagekeeps fluctuating even when input is constant at logic “1” and“1” to “0” transition is slower than “0” to “1” transition. If thesteady-state voltage-swing on the line is more than the differ-ence between and , the line voltage does not swingwhile the input is constant. However, the delay of the schemeduring “0” to “1” and “1” to “0” transitions differ by a largeamount which causes significant reduction in the throughput ofthe scheme.

III. PROPOSED CMS SCHEME

A macro model of a dynamic overdriving CMS scheme wasdeveloped in order to understand the effect of different designparameters on the performance signaling schemes (see Fig. 2).This aids us in designing the transmitter and receiver circuitsuch that the interconnect scheme is robust against process vari-ations. The driver circuit is modeled as a current source that sup-plies current of the shape as shown in Fig. 1(a) to the line. Thereceiver circuit is modeled by a terminator circuit followed byan amplifier. The terminator is represented by a resistancein series with a DC voltage source .Our analysis shows that delay of the line is a strong function

of the large current supplied to the line during transition ,the duration for which this large current is given and thevoltage swing on the line . Hence, for a robustdynamic overdriving CMS scheme, , , and shouldremain the same in all process corners.For high throughput (the maximum rate at which data can

be transmitted reliably) rise and fall delay of the link should be

Fig. 3. Proposed current-mode signaling scheme (CMS-Bias).

Fig. 4. Derivation of the proposed corner-aware bias circuit. a) Resistancebased; b) diode-connected transistor based; c) two step (fine-coarse) compen-sation; d) diode-connected devices with extra sensor.

equal. Therefore the peak current supplied by the driver duringlow-to-high and high-to-low transitions must be equal andon the line must be symmetric around . Further ,must be nearly in the center of amplifier’s input common-moderange. A robust CMS scheme meets all these requirements in allprocess corners.

A. Proposed Transmitter and Receiver Circuits

Fig. 3 shows the transmitter and the receiver of the proposedCMS scheme (CMS-Bias). The proposed transmitter employstwo drivers (a strong driver and a weak driver) with NAND andNOR gates like the transmitter of CMS-Fb scheme. In the pro-posed transmitter, duration for which the strong driver is turnedon is controlled by a delay element and not by the feedback.The strong and weak drivers employ single transistor currentsources. The bias voltages ( and ) of these current sourcesare generated from a specially designed bias circuit such thatcurrent through strong and weak driver remain constant acrossall process corners. Operation of the bias circuit is discussed inthe next section.The proposed receiver uses a diode connected pMOS and

nMOS (terminating inverter) followed by an inverter chain.The terminator inverter holds the line voltage near its switching


Fig. 5. a) Proposed corner-aware bias circuit b) probability density function of output current (results of 4000 Monte Carlo simulations).

threshold. Inverter amplifier (IA) and subsequent invertersamplify the small line voltage swing to digital logic levels.

B. Bias Generation Circuit

The proposed bias circuit is derived from the conventionalresistor based bias circuit. Fig. 4(a) shows the resistor basedbias circuit. In the ideal resistance based circuit, the pMOS biasvoltage increases/decreases from its value defined in thenominal process corner when the pMOS (MP0) becomes fast/slow due to process variations. As a result, does notchange much with process variations. Similarly, changessuch that the variations in are less. However, the on-chipresistors can vary by 15% [20]. Hence, in practice, the biasvoltages and change not only due to variations in thepMOS and nMOS transistors but also due to variations in theresistance. Moreover, in this circuit there exists a direct tradeoffbetween area of a resistor and power consumption. Essentially,in the bias circuit the variations in the load device [the resistorin Fig. 4(a)] must be much less compared to the variations inthe sensor device [pMOS and nMOS in Fig. 4(a)]. One possiblealternative is to employ a long channel transistor as load anda short channel transistor as the sensor device. Long channeltransistors are less susceptible to process variations. One suchcircuit was proposed in [19] [see Fig. 4(b)]. The major limita-tions of this bias circuit are as follows.1) The bias voltages do not change sufficiently in the extremeprocess corners (SS and FF). For a independent currentsource, of aMOSFET should remain nearly thesame across all corner. In other words, ,for a independent current source. In this bias circuit,bias voltages are given by

This circuit when designed for requireslarge area and power.

2) The bias voltages do not compensate for variations in mo-bility as variations in mobility of the transistors have verylittle dependence on channel length of the transistors.

One solution is to perform process compensation in twostages: coarse compensation and fine compensation [see

Fig. 4(c)]. In this circuit, the load transistor in the final stageis a current source compensated by the coarse bias circuit. Theother solution is to employ two sensor transistors (short transis-tors) and a long channel transistor as shown in Fig. 4(d). Dueto the presence of two short-channel transistors in the stack, thebias voltage is a stronger function of and of the shortchannel device than that of a long channel device. Here, wehave employed the bias circuit which is a combination of boththe circuits shown in Fig. 4(c) and (d). Fig. 5(a) shows the finalbias circuit employed in the proposed CMS scheme. Fig. 5(b)shows the probability distribution function of drain current ofa transistor biased by this bias circuit in 180-nm technology.The of the output current is 1.69% which is 7 lessthan of an uncompensated MOSFET in this process.With this bias circuit, the proposed CMS scheme is more robustagainst process variations. A qualitative analysis of robustnessof the proposed CMS scheme against inter-die and intra-dievariations is discussed in the next section.

C. Robustness of the Proposed CMS Scheme

The effect of inter-die variations on the performance of theCMS schemes is analyzed in four process corners: SS (nMOSand pMOS both are slow), FF (nMOS and pMOS both are Fast),SNFP (nMOS is Slow and pMOS is Fast), and FNSP (nMOS isfast and pMOS is slow). In the skewed process corners (SNFPand FNSP), current through the strong and weak drivers do notdiffer much from their values in the nominal case. In the skewedcorners, rise and fall delay of the inverters in the delay elementchange in the opposite direction and hence does not deviatemuch from the nominal process corner. The input impedance ofthe proposed receiver circuit is . Sinceand change in opposite directions in the skewed corner,

of the receiver remains the same as in the nominal case.Thus, in the skewed corners, , , and re-main nearly unchanged and so does the delay of the line. In theSS and FF corners, change in the strength of the current-sourcetransistors is compensated partly by the change in bias-voltageand partly by . In the SS corner, increases whereas in FFcorner decreases. In these corners, decrease/increase in thestatic current is partly compensated by increase/decrease in the

which keeps nearly the same as given in the nominalcorner. This way, the proposed scheme is conceptually robustagainst inter-die process variations.


The proposed transmitter and receiver circuits do not haveany local feedback connections. As a result performance ofthe proposed circuit does not rely on matching of the tran-sistor parameters between transmitter and receiver circuit.In the proposed receiver, the terminating inverter and IA aredesigned using fingers and placed close to each other so thattheir switching thresholds are nearly the same under all processconditions. Hence, it is less sensitive to intra-die variations.

D. Scalability of the Proposed CMS Scheme

Design and performance of the proposed circuit in scaleddown technologies are analyzed in this subsection. Majorconcerns in design of mixed signal circuits in sub-90-nm tech-nology nodes are reduced voltage headroom and variations.Both of these issues do not pose major limitations on scalabilityof the proposed circuit.Transmitter circuit employs digital circuits such as NAND,

NOR, and inverters (in the delay element) which scale well withscaling of transistor features. It also employs switched currentsources in the strong driver and weak driver. Even with reducedvoltage headroom and leaky switches in scaled down technolo-gies, the strong and weak drivers can be designed such that largecurrent is supplied during input transition and very small duringsteady-state. As long as dynamic overdriving property of thetransmitter is maintained, the signaling scheme allows very highdata-rates while consuming very little energy. The proposedbias generation circuit is based on the statistics that variation inshort-channel MOSFETs is more as compared to long-channelMOSFETs. These statistics are valid even in the shorter tech-nology nodes. Hence, the bias circuit can be redesigned in anew technology node to track process variations. Receiver cir-cuit employs inverters which scale well with technology nodes.In the proposed scheme designed in 180-nm process, voltageswings on the line are 30 mV. In the shorter technology nodesline voltage swings can be further reduced but shall remain tobe the same percentage of supply voltage. It should be notedthat major sources of noise such as supply noise and crosstalkalso scale with supply levels. Hence, good signal to noise ratiocan be maintained even in sub-90-nm technology nodes. Ro-bustness against inter-die and intra-die variations is achievedprimarily due to topology of the transmitter and receiver cir-cuits and process tracking ability of the proposed bias genera-tion circuit as explained in Section III-C. Thus qualitatively, theproposed circuit is expected to remain energy efficient and ro-bust against inter-die and intra-die variations even in the shortertechnology nodes.Only concerns in the shorter technology nodes would be

increased local mismatch in transistors which can cause sig-nificant mismatch between switching threshold of theterminating inverter which sets and switching thresholdof the inverter amplifier in the receiver. The signaling schemehas to be designed such that voltage swings on the line ismore than the mismatch between the s of the two inverters.Mismatch between the of the two inverters can be re-duced by using long channel MOSFETS in the inverters andcommon-centroid kind of layout of the two. We have designedthe proposed CMS scheme, CMS-Bias, in 65-nm CMOS and90-nm CMOS process. Simulations show that the proposed

Fig. 6. Part of die photograph highlighting CMS schemes.

CMS scheme is energy-efficient and robust against inter-dieand intra-die variations as well as local mismatch in transistorparameters even in these technology nodes.

IV. DESIGN AND IMPLEMENTATION OF CMS SCHEMES

Two CMS schemes, CMS-Fb and the proposed scheme(CMS-Bias), were designed in 180-nm CMOS process usingnominal devices for 1.8 V. Both the schemes weredesigned such that the input capacitance of their transmittersis equivalent to that of one minimum sized inverter while thereceivers drive FO4 load. The CMS schemes were designedto drive a 10 mm long 0.63 m wide shielded M3 line with0.63 m spacing between the shield and the wire. Resistanceand capacitance of the shielded line extracted by Assura RCextractor are 95 mm and 0.150 pF/mm, respectively. Undernominal process, voltage, and temperature (PVT) conditions,the maximum frequency of the digital core is marginally lessthan 2.6 GHz. Here, the frequency of three-stage NAND gatesdriven by a flip-flop and loaded by a flip-flop is considered tobe a representative of the frequency of digital core. Hence, theCMS schemes were designed for a throughput of 2.63 Gbpsfor the minimum possible power consumption in the nominalcase. The CMS schemes are designed for a steady-state voltageswing of 30 mV on the line at the receiver end [11]. A test chipwas fabricated to demonstrate the performance of the designedCMS schemes on silicon (see Fig. 6).

A. Delay Measurement Scheme

Delays of the CMS schemes are of the order of hundreds ofpico-seconds. It is nearly impossible to take input and outputsignals outside the packaged chip and measure the delays of thisorder. Special test circuits which convert small time differencesinto quantities which can be easily measured off-chip are re-quired. One such scheme that converts time difference into fre-quency difference was implemented in the test chip (see Fig. 7).The CMS scheme is placed within a ring oscillator (RO) loop viaa multiplexer and a demultiplexer. Frequency of the ringoscillators with the interconnect scheme in the loop is measured

. Frequency of the ring oscillator with isalso measured. Delay of the interconnect scheme is then calcu-lated by

(1)

In the layout, lengths of wires connecting the multiplexer anddemultiplexer to the interconnect scheme and thewires forming RO (L3), were carefully matched. Switches in


Fig. 7. Delay measurement scheme. (a) Delay measurement circuit: principle;(b) delay measurement with CMS link: floor plan.

the multiplexer and the demultiplexer are implemented usingtransmission gates. The multiplexer (demultiplexer) exhibits thesame delay for all inputs (outputs). This ensures that in the dif-ferential measurement given by (1), delays corresponding tothe multiplexer, demultiplexer and inverters are canceled. Fre-quency of ring oscillator was pre-scaled using on-chip di-viders to permit convenient measurement using standard fre-quency counters.

B. Measurement Setup for Parameter Variations

Parametric variations are statistical in nature. Hence, the ef-fect of process variations on the performance of a system cannot be shown from a few chips fabricated in one run. Hence, thetest circuits on the chip should be such that at least a few deviceparameters can be controlled externally after the fabrication.Weuse pMOS substrate bias (NWell Bias) to emulate variations inMOSFET parameters. Using NWell bias, we can change theof PMOS and hence, the switching threshold of inverters. TheNWells in the transmitter and the receiver circuits are assignedseparate pins. In order to analyze inter-die variations, they aregiven the same voltages which is adjusted to emulate practicalvariations in . To assess the effect of intra-die variations, theyare driven to different values.

C. On-Chip Test Circuits

Fig. 8 shows the schematic of the test circuits placed on thechip. Two delay measurement schemes were implemented onthe chip: one with a 2 1 multiplexer-demultiplexer (2 1Mux-Demux) and the other with a 4 1 multiplexer-demulti-plexer (4 1 Mux-Demux). A 2 1 Mux-Demux scheme in-cludes CMS-Fb scheme and CMS-Bias scheme. Hence, it givesonly the difference in delay of the two CMS schemes. A 41 Mux-Demux scheme includes the two CMS schemes as wellas an RO with direct connection. Hence, 4 1 Mux-Demuxscheme also gives the absolute delay of the CMS schemes. Sepa-rate pins are assigned to of the digital circuits, output buffers

Fig. 8. Circuits on the test chip. (a) 4 1 Mux-demux-based scheme; (b) 21 Mux-demux based scheme; (c) driver with programmable istatic.

Fig. 9. PC board used for testing.

and CMS schemes. This is to limit the supply noise seen by theCMS schemes and to measure their power consumption individ-ually. The currents through weak drivers in both the signalingschemes are made externally programmable by using additionalcurrent mirrors on the chip as shown in Fig. 8(c).The frequency of the ring oscillator was divided by 16 using

a 4-bit on-chip counter before taking it to I/O pads. The counteroutputs are buffered by on-board buffers and the frequencyis measured using a 6-digit frequency counter. The chip wasplaced in a socket mounted on a PC board for testing (seeFig. 9). The PC board also includes electronics for generationof variable supply and substrate bias.

V. PERFORMANCE OF THE PROPOSED CMS SCHEME:SIMULATION AND MEASUREMENT RESULTS

A. Performance in Nominal Conditions

Table I summarizes measured results of the CMS schemesunder nominal operating condition (no additional currents and

1.8 V). Frequency measurements of 2 1 Mux-Demux-based scheme show that delay of CMS-bias scheme is less thanthat of CMS-Fb scheme by 143 ps. Measurement results from4 1 Mux-Demux-based scheme show that CMS-bias schemeoffers 9% improvement in delay over CMS-Fb. This difference


Fig. 10. Waveform of forth bit of the on-chip counter used for 4 1Mux-demux scheme observed on DSO. (a) : CMS-Fb in the loop; (b) :CMS-bias in the loop; (c) : plain RO.

TABLE IPERFORMANCE OF CMS SCHEMES DRIVING 10 mm LINE

is primarily because the inverter amplifier in the receiver ofCMS-Fb scheme has to drive transistors and un-like CMS-Bias scheme (see Fig. 1). The additional capacitiveload offered by and is significant as their channellengths are chosen to be more than 180 nm in order to reducestatic power consumed in the receiver. Fig. 10 shows the ringoscillator signal divided down by 16 as observed on a digitalstorage oscilloscope (DSO). Since CMS-Fb scheme has moredelay than CMS-Bias scheme, the ring oscillator oscillates atlower frequency when CMS-Fb is selected. For fair compar-ison of energy/bit, of digital circuits (multiplexers, demul-tiplexers and inverters) was adjusted so that the ring oscillatesat the same frequency in both the cases. Hence, for the dig-ital circuit was kept 2.5 V when CMS-Fb was selected and 2.0V when CMS-Bias was selected for energy measurements. Theproposed CMS scheme offers 34% gain in energy/bit and 42%improvement in EDP at data rates of 0.64 Gbps over CMS-Fbscheme. Measurements on 2 1 Mux-Demux-based schemeshow that the proposed scheme consumes 0.622 pJ/bit at datarate of 0.78 Gbps.The ring oscillator-based test structures force the input

signal to the CMS schemes to have activity factor of 1. Forthroughput estimation with realistic data patterns, simulationswere performed with random input bit sequence of differentactivity factors. Throughput is defined as the maximum datarate at which the worst-case eye-opening at the output is 40% of. Throughput of both the schemes is 2.63 Gbps. Energy/bit

consumption for random bit sequence with activity factor of0.5 is reported in Table I. Simulation results in nominal processcorner show that proposed scheme shows 28% and 34% im-provement in energy/bit and EDP over CMS-Fb scheme. Inboth the CMS schemes dynamic power consumption is muchless than static power consumption. This is primarily becausevoltage swing on the line is very small and a large currentsupplied by the strong driver is hardly for 200–300 ps. In

Fig. 11. Measurement results of (a) effect of pMOS substrate bias on switchingthreshold of inverter (b) effect of intra-die variations on average delay ofthe CMS schemes.

CMS-Bias scheme inverter amplifier in the receiver and biascircuit in the transmitter consume static power. The transmitterof CMS-Fb scheme does not have a bias circuit but it has a feed-back inverter which consumes more power than biasing circuit(see Fig. 1). Further, the bias circuit can be shared by multiplelines of a bus. Assuming a 16-bit bus, power consumption inthe bias circuit is divided by sixteen for calculating power ofa single bit line of CMS-Bias. Hence, energy/bit consumedby CMS-Bias scheme is much less as compared to CMS-Fbscheme. CMS-Bias scheme takes up slightly more active areathan CMS-Fb scheme.

B. Effect of Intra-Die Variations

In order to study the effect of intra-die and inter-die varia-tions, we need to know the range over which the NWell biasshould be varied to produce expected variations in . A setof simulations and experiments were performed for the same.We defined separate sets of model parameters for the transistorsplace 1.5 mm apart based on the statistical mismatch report fromfoundry, called and . In model, ofthe nMOS transistors is less while of pMOS transistorsis more than given in nominal process corner ( corner) and allthe rest of the parameters are the same as given in corner.The maximum difference in the switching threshold ofinverters using and model parameters is 60 mV.Fig. 11(a) shows the of inverter as a function of pMOS sub-strate bias measured on bare dies fabricated in this run. In thisrun 500 mV of change in maps to 60 mV of change inof the inverter. Therefore, the difference in source-bulk voltage

of pMOS transistors in the transmitter and in the receiversis varied from 0 to 500 mV during the intra-die variations ex-periments. In the scaled down technologies source-bulk voltage


TABLE IIEFFECT OF INTRA-DIE VARIATIONS: SIMULATION RESULTS

Fig. 12. Measurement results of (a) effect of voltage swing (external current)on delay in the presence of intra-die variations (b) effect of voltage-swing (ex-ternal current) on energy/bit of CMS-Fb scheme.

can not be forward biased by more than about 30–50 mV dueto the parasitic BJT effect. Hence, the pMOS substrate bias wasvaried from 1.8 to 2.3 V for 1.8 V while evaluating theeffects of intra-die variations.The intra-die variation experiments were performed at a data-

rate of 0.45 Gbps which was reached by setting the ofdigital circuits to 1.5 V. Fig. 11(b) shows the measured delayof CMS-Fb and CMS-Bias as a function of the difference inPMOS substrate bias in the transmitter and the receiver. Delayof CMS-Fb scheme becomes 2.5 the nominal delay in the ex-treme case of mismatch in of inverters. In CMS-Fb schemestrong driver is turned off after the line voltage has crossedof the inverter in the transmitter and line voltage is clampedclose to of the inverter in receiver. The mismatch in sbeing more than steady-state voltage swing causes low-to-highdelay and high-to-low delay in CMS-Fb scheme to be very dif-ferent as explained in Section II. We can conclude that in theextreme case of intra-die variations shown in Fig. 11(b), mis-match in s is more than the steady state voltage swing onthe line. Delay of the proposed scheme remains nearly the samefor the entire range of pMOS substrate bias as its operation doesnot rely on matching of transistors in the transmitter and transis-tors in the receiver as explained in Section III-C. CMS schemeswere designed for 30 mV of steady-state voltage swing on theline at the receiver end as in [11]. Robustness of CMS-Fb tointra-die variations can be improved by increasing the voltageswing on the line. In this test chip, voltage swing on the linecan be changed by applying currents through the pins and

externally [see Fig. 8(c)]. Fig. 12(a) shows the delay of theschemes as a function of the difference in pMOS substrate biasin the transmitter and the receiver for different voltage swingson the line. It shows that even with higher voltage swing, delayof CMS-Fb scheme degrades significantly when the transistorparameters of transmitter and receiver are not identical. 10 Aof external current, corresponds to around 50 mV of additional

TABLE IIIEFFECT OF INTER-DIE VARIATIONS ON DELAY: MEASUREMENT RESULTS

voltage swing on the line. Fig. 12(b) shows the energy over-head incurred due to the increase in voltage swing on the line. Inthese experiments, it could be argued that the increase in delayof CMS-Fb is due to the weakening of pMOS devices on ap-plication of NWell bias. To rule out this possibility, we appliedidentical high reverse-bias to the transmitter and the receiverand this did not result in significant increase in the delay. Hence,we can conclude that the observed increase in delay is due tomismatch. The detailed results of these experiments are shownin the next section.The measurement results give only the average delay of the

CMS schemes. In reality the difference in rise delay and the falldelay becomes high due to intra-die variations. Table II showssimulation results of rise delay, fall delay and throughput ofthe two CMS schemes in the presence of intra-die variations.It shows that the rise and fall delays of CMS-Fb scheme dif-fers by a large amount in the presence of intra-die variations,which degrades its throughput. The throughput of the schemefalls to 166 Mbps in the extreme case of difference in inverters. Throughput of the proposed scheme remains around 2.22

Gbps even in the extreme case of intra-die variations. In case ofmoderate intra-die variations where either the transmitter or thereceiver transistors follow model parameters given in the nom-inal case, throughput of the CMS-Fb scheme reduces to 0.833Gbps. In these cases throughput of CMS-Bias scheme remainsaround 2.5 Gbps.Apart from separation-dependent mismatch, random mis-

match between the parameters of the adjacent transistors isalso possible due to process variation. We have performedsimulations for local mismatch in transistor parameters withinreceiver and transmitter. Its effect on throughput of both theCMS schemes is negligible. Local mismatch in transistor pa-rameters can be reduced by deploying good design techniques(using fingers and common-centroid layout. The transmittersof CMS-Fb and CMS-Bias schemes have digital circuits (in-verters, NAND and NOR gates). Performance of digital circuits


TABLE IVFOUR CORNER ANALYSIS: SIMULATION RESULTS (ENERGY/BIT CALCULATED AT 2 Gbps)

is not affected by local mismatch transistor parameters. Trans-mitter of CMS-Bias scheme employs current sources. Matchingof current through strong and weak drivers during “0” to “1”transition and “1” to “0” transition of inputs is essential. Thisis taken care by bias generation circuit. As is derived from, good matching between the currents sourced and sank by

the strong and weak driver is realized.In the proposed receiver, s of the terminator and inverter

amplifier in the receiver of CMS-Bias scheme can differ at themost by 11 mV. The CMS schemes are designed for voltageswings enough higher than the maximum mismatch. Once thesignal is amplified by the inverter amplifier, mismatch in param-eters of the rest of the inverters in the receiver do not affect theoutput. In the receiver of CMS-Fb scheme more transistors needto be matched as compared to the proposed CMS-Bias scheme.However, it employs feedback so that resting voltage of the linetracks inverter amplifier’s switching threshold. Hence, for boththe receivers local matching of the transistors is not very crit-ical. Hence, even in the presence of local mismatch in deviceparameters, throughput of both the CMS schemes is around 2.5Gbps.

C. Effect of Inter-Die Variations

To assess the effects of inter-die variations, we vary NWellbias in the transmitter and the receiver from 1.8 to 2.3 V iden-tically. Table III shows the delay and energy/bit of both theschemes for different NWell bias voltages. The last two columnsin the table shows the data rate at which the energy/bit was mea-sured. It is apparent from the table that delay of both the sig-naling schemes do not change much with inter-die variations.Also, they do not consume much additional energy to keep thedelay constant with inter-die variations.These experiments do not capture the effect of variations in

parameters of nMOS transistors. Table IV shows the simulationresults of delay, energy/bit and throughput of the two schemesin all process corners. It shows that delay and throughput ofboth the schemes remain practically the same in the four digitalprocess corners and the nominal case without consuming muchadditional energy. The local feedback in the transmitter and re-ceiver of CMS-Fb scheme that makes it susceptible to intra-dievariations makes it robust against inter-die variations. As longas these of the inverters in the transmitter and in the receiverare matched, CMS-Fb scheme is robust against inter-die vari-ation. Robustness of CMS-Bias scheme against inter-die vari-ation is primarily due to circuit topology and process compen-sated current sources in the strong and weak drivers in the trans-mitter as explained in Section III-C. In the slow process corner(SS), throughput of the proposed scheme degrades by 24%. The

Fig. 13. Output of noisy supply (NS) in AC coupling mode.

TABLE VEFFECT OF SUPPLY VARIATIONS ON DELAY: MEASUREMENT RESULTS

last column in Table IV shows the clock frequency of logic cir-cuits in the four process corners. It shows that in the nominalcase, the clock frequency of the logic core would be around 2.2GHz. As seen from Table IV that the frequency of the logic corereduces to 1.81 GHz in the SS corner. Thus, the throughputs ofboth the CMS schemes remain above the clock frequency oflogic in all process corners including SS.

D. Effect of Supply Variations

The reduced voltage swings in the CMS schemes make themsusceptible to variations in supply. The delays of the signalingschemes were measured in the presence of supply noise andsupply drift. In the experiments, the signaling schemes weregiven from a noisy supply and clean (regulated) supply tosee the effect of supply noise. Fig. 13 shows the voltage at thesupply pin of the signaling scheme on the chip observed on aDSO in AC coupling mode when given from noisy supply. Theoutput of noisy supply has low frequency noise of around 100mV of peak-to-peak amplitude. Table V shows the measureddelay of the two signaling schemes for different given froma noisy and a clean supply. From Table V, it is clear that, thedelay of the CMS schemes, CMS-Fb and CMS-Bias, changeby at the most 7% due to low frequency supply noise. A driftin from 1.7 to 1.9 V also causes around 7% change in the


TABLE VIEFFECT OF SUPPLY DRIFT ON SPEED AND POWER: SIMULATION RESULTS

(ENERGY/BIT CALCULATED AT 2 Gbps)

TABLE VIIEFFECT OF PRACTICAL SUPPLY NOISE ON SPEED: SIMULATION RESULTS

delay of the two CMS schemes. This is because operation andperformance of transmitter and receiver circuits of CMS-Biasscheme do not change much with 10% drift in supply voltageas they comprise of digital logic gates, switched current sourcesand bias circuit. From Table V, power consumption of both thescheme is a strong function of and static power consump-tion is a significant component of the total power consumptionin both the CMS schemes. Simulations were performed toobserve the effect of supply drift on the throughput and en-ergy/bit at high frequencies. Table VI shows simulation resultsfor delay, throughput and energy/bit. The simulation resultsshow that throughput and delay of the CMS scheme do notchange much with supply drift. We can also conclude thatthe current-mode schemes are more energy-efficient at lowersupply voltages without degradation in throughput.The transmitter and the receiver circuits of the signaling

schemes on the test chip observe identical fluctuations on theirsupply lines since they are placed very close. However, supplylines of the transmitters and the receivers are likely to have un-correlated fluctuations in practice. The signal-unrelated powersupply noise can be around 5% of the magnitude of powersupply for a well-designed power distribution network [2].Simulations were performed to observe the effect of practicalhigh frequency supply noise on the speed of the CMS schemes.In the simulations the transmitter and the receiver circuitswere given supply from separate random signal generatorwith different seed values via a source resistance and a bypasscapacitor. Fig. 14 shows the simulation setup used to considersupply noise and the resultant waveform of supply of the trans-mitter and the receiver circuits. Table VII shows the throughputof the schemes for different peak-to-peak amplitudes of supplynoise. From Table VII, throughput of the scheme CMS-Fbdegrades significantly in the presence of even very little supplynoise. Throughput of the proposed scheme degrades less underthe same condition. However, the proposed scheme becomesslower than the logic circuit in the presence of supply noisewith a peak-to-peak amplitude of 70 mV which is much morethan voltage swing on the line. It is important to understandthat these numbers are for 10 mm long lines designed for a verysmall voltage swing. The noise margin of the CMS schemecan be increased by designing it for higher voltage-swing. Theproposed scheme can sustain supply noise of around 100 mV

Fig. 14. Simulation setup for supply noise and waveform of a noisy supply.

when designed for 60 mV of line voltage-swing. This costsonly 10% additional energy.

E. Effect of Temperature

The effects of temperature rise on the performance of theCMS schemes were analyzed through simulations. The simula-tions were performed for two cases: 1) temperature of the entirechip is higher than nominal level and 2) the transmitter and thereceiver are at higher but different temperature compared to thenominal values. On-chip spatial difference of temperature canbe as high as 40 C [21]. Here we have considered that the trans-mitter and the receiver are operating at 90 and 50 , respectivelyas transmitter operating at a higher temperature is worse than thereceiver operating at higher temperature. Table VIII shows ef-fect of temperature change on delay, energy/bit and throughputof the CMS schemes. The difference in temperature of the trans-mitter and receiver causes difference in device parameters ofthe transistors in the transmitter and transistors in the receiver.As a result of the inverter in the transmitter and of the in-verter in receiver are different. Hence, throughput of CMS-Fbscheme degrades significanly in the presence of on-chip tem-perature gradient (see Table VIII). The results of Table VIII in-dicate that the proposed scheme remains faster than the logiccircuit even in the extreme case of on-chip temperature rise andtemperature gradient.

VI. PERFORMANCE OF THE PROPOSED CMS SCHEME INCOMPARISON WITH OTHER SIGNALING SCHEMES

Table IX shows performance of recent energy-efficientsignaling schemes for on-chip long wires. Energy consumptionof the proposed signaling scheme (CMS-Bias) is the lowestof all. Energy consumption of the capacitively coupled trans-mitter based scheme presented in [17] is comparable to that ofCMS-Bias but it has been implemented in 90-nm technologynode. In [15], a similar scheme with capacitively coupled trans-mitter is presented with implementation in 180-nm process. Itconsumes 1.05 pJ/bit which is 74% more than the proposedscheme, CMS-Bias. However, the scheme given in [15] isdifferential nature whereas we have presented a single-endedscheme. Assuming differential design of CMS-Bias consumestwice the power consumed by single-ended design (being pes-simistic for CMS-Bias), energy consumption of the proposedscheme is 49% less than the scheme proposed in [15]. In [12],[15], and [17] effects of PVT variations (specifically intra-dievariations) on throughput of the signaling schemes are not


TABLE VIIIEFFECT OF TEMPERATURE VARIATIONS ON CMS SCHEMES (TT CORNER, 1.8 V, ENERGY CALCULATED AT 1.5 Gbps)

TABLE IXPERFORMANCE OF VARIOUS SIGNALING SCHEMES

discussed in detail in spite of having reduced voltage swings onthe line. The dynamic overdriving CMS scheme proposed in[11] (CMS-Fb) is single-ended and is architecturally similar toour scheme. Our analysis shows that CMS-Fb is robust againstinter-die variations but not intra-die.

VII. CONCLUSION

In this paper, we have shown that the repeaterless signalingschemes for on-chip long interconnects should be designedconsidering both intra-die and inter-die variations in process,voltage and temperature. A dynamic overdriving CMS schemethat is robust against inter-die and intra-die variations is pro-posed in this paper. The proposed scheme uses a novel biascircuit for the transmitter, based on a judicious combinationof long and short channel MOSFETs. Energy efficiency androbustness of the proposed CMS scheme are demonstratedusing measurement results on a test chip in 180-nm CMOSprocess. The proposed signaling scheme consumes 0.622and 0.297 pJ/bit of energy for communication over 10 mmlong line at 0.78 and 2.63 Gbps of data-rates, respectively.It also offers more than 30% improvement in energy/bit andEDP, respectively, over a competing CMS scheme, CMS-Fb.Measurements indicate that the delay of the proposed schemechanges by only 5% in the presence of intra-die variationswhereas delay of CMS-Fb [11] becomes 2.5 times of its nom-inal value for the same amount of variations. Throughput ofthe proposed scheme reduces to 2.17 Gbps in the extreme caseof intra-die variations whereas throughput of CMS-Fb schemedrops to 166 Mbps in this case. Measurements and simulationsindicate that CMS-Fb and proposed schemes both are robustagainst inter-die variations. Simulations indicate that the CMSschemes are more sensitive to high frequency supply noisethan DC drift in the supply. Magnitude of supply noise playsa major role in determining minimum required voltage swingson the line. CMS-Fb scheme is more sensitive to supply noise,temperature rise, and on-chip temperature gradient than thepresented novel scheme in this paper. In all cases, the proposedCMS scheme remains faster than logic circuit even in theextreme case of PVT variations with negligible compromise onthe energy consumption.

ACKNOWLEDGMENT

The authors would like to thank Tata Consultancy Services(TCS) and Government of India (SMDP) for funding chip fab-rication. They are also thankful to Europractice and Faraday forproviding fabrication service and ESD protection circuits, re-spectively. They would also like to thank VLSI Design Group,IIT-Bombay for insightful discussions.

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and L.-S. Peh, “Research challenges for on-chip interconnectionnetworks,” IEEE Micro, vol. 27, no. 5, pp. 96–108, Sep./Oct. 2007.

[2] H. Zhang, V. George, and J. M. Rabaey, “Low-swing on-chip signalingtechniques: Effectiveness and robustness,” IEEE Trans. Very LargeScale Integr. (VLSI) Syst., vol. 8, no. 6, pp. 264–272, Jun. 2000.

[3] A. Nalamalpu, S. Srinivasan, and W. Burleson, “Boosters for drivinglong on-chip interconnects: Design issues, interconnect synthesis andcomparison with re-peaters,” IEEE Trans. Comput.-Aided Design In-tegr. Circuits Syst., vol. 50, no. 4, pp. 50–62, Jan. 2002.

[4] R. Ho, K. Mai, and M. Horowitz, “Efficient on-chip global intercon-nects,” in VLSI Symp., Dig. Tech. Lett., 2003, pp. 271–273.

[5] H. Kaul and D. Sylvester, “Low-power on-chip communication basedon: Transition-aware global signaling (TAGS),” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 464–476, May2004.

[6] J. sun. Seo, P. Singh, D. Sylvester, and D. Blaauw, “Self-timed regener-ators for high-speed and low-power interconnect,” in Proc. ACM/IEEEInt. Symp. Quality Electron. Design (ISQED), 2007, pp. 621–626.

[7] R. T. Chang, N. Talwalkar, C. P. Yue, and S. S. Wong, “Near speed-of-light signaling over on-chip electrical interconnects,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 834–838, Apr. 2003.

[8] N. Tzartzanis and W. W. Walker, “Differential current-mode sensingfor efficient on-chip global signaling,” IEEE J. Solid-State Circuits,vol. 40, no. 11, pp. 2141–2147, Nov. 2005.

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[17] E. Mensink, D. Shinkel, E. A. M. Klumperink, E. van Tuijl, and B.Nauta, “Power efficient gigabit communication capacitively drivenRC-limited on-chip interconnects,” IEEE J. Solid-State Circuits, vol.45, no. 2, pp. 447–457, Feb. 2010.

[18] M. Dave, M. Shojaei, and D. Sharma, “Energy-efficient current-modesignaling scheme for on-chip interconnects,” presented at the AsianSolid-State Conf., Beijing, China, 2010.

[19] M. Dave, M. Shojaei, and D. Sharma, “A process variation tolerant,high-speed and low-power current mode signaling scheme for on-chipinterconnects,” in Proc. GLSVLSI, 2009, pp. 389–392.

[20] Europractice, Belgium, “Foundry reistancemodel file,” 2007. [Online].Available: http://www.europractice-ic.com/index.php

[21] T. S. Rosti, K. Mihik, and G. D. Micheli, “Power and reliability man-agement of SoCs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 15, no. 4, pp. 391–403, Apr. 2007.

Marshnil Dave (S’11) is pursuing the Ph.D. de-gree from the Electrical Engineering Department,IIT-Bombay, Bombay, India. Her Ph.D. dissertationis on “High speed energy-efficient on-chip links”.She has taped out and successfully tested three test

chips demonstrating the novel circuits for on-chipglobal communication. Her research results havebeen published in various reputed journals andconferences (including ISSCC-SRP and A-SSCC).In addition to high speed low power links, herresearch interests include PVT variation tolerant

circuit design, Circuit design using new devices, signal conditioning circuitsfor biomedical applications, and on-chip test circuits for analog mixed-signalcircuits. In parallel to her Ph.D. work, she has also co-guided many graduatestudents for thesis on various related topics.Ms. Dave was a recipient of a Best Student Paper Award at IEEE ISVLSI

2011. Recently, she has also served as a reviewer for reputed conferences andjournals such as VLSI Design, ASQED, and Microelectronics Journal.

Mahavir Jain received the Bachelor’s degree inelectronics and communications engineering fromNorth Maharashtra University, Jalgaon, in 2006 andthe Master’s degree in information and communica-tion technology from DA-IICT, Gandhinagr, India,in 2009.From 2009 to 2010, he worked as a Research En-

gineer with IIT- Bombay, where he worked on deviceand packaged IC level testing and characterization.Since November 2011, he is working with FairchildSemiconductor, India, as a Device Test Engineer.

His areas of interest include on-chip test architectures for analog and mixedsignal systems and power MOSFET-based systems design, macro-modelling,and testing.

Maryam Shojaei Baghini (M’00–SM’09) receivedthe M.S. and Ph.D. degrees in electrical engineeringfrom Sharif University of Technology, Tehran, Iran,in 1991 and 1999, respectively.She worked for two years in industry on the de-

sign of analog ICs. In 2001, she joined IIT-Bombay,Mumbai, India, as a Postdoctoral Fellow, where sheis currently an Associate Professor. She is the au-thor/coauthor of 86 international journal and confer-ence papers, the inventor/coinventor of 13 patent ap-plications, and the coauthor of 2 books. Her current

research interests include device–circuit interaction in emerging technologies,high-performance low-power analog/mixed-signal/RF IC design and test forvarious applications and power management for systems on chip.Dr. Baghini serves in the Technical Program Committee of several confer-

ences, including the IEEE Asian Solid-State Circuits Conference, IEEE Inter-national Conference on VLSI Design, and Asia Symposium on Quality Elec-tronic Design. She was a corecipient of IIT Bombay Industry Impact Awardin 2008, the Best Research Award in Circuit Design at Intel Corporation AsiaAcademic Forum 2008, and the Third Award on R&D at the International Fes-tival of Kharazmi in 2002. Her team of students won first place in the DesignContests held by Cadence Design Systems, India, and Analog Devices, India,in 2006 and 2011, respectively.

Dinesh Sharma (M’98–SM’01) received the Ph.D.degree from the University of Bombay, Mumbai,India.He was with the Solid-State Electronics Group,

Tata Institute of Fundamental Research, from 1971to 1991, except between 1976 and 1978, when hewas a visiting Scientist with Laboratoire d’Électron-ique des Technologies de l’Information, Grenoble,France, and between 1985 and 1987, when he waswith the Microelectronics Center, Research TrianglePark, NC. Since 1991, he has been with the De-

partment of Electronic Engineering, Indian Institute of Technology, Bombay,where he is currently a Professor and the Head of the department. Over the last35 years, he has worked in the areas of metal–oxide–semiconductor (MOS)device modeling, very large scale integration (VLSI) technology development,VLSI digital system design, mixed-signal design, and radio frequency (RF)design. He has also contributed to research in process and device simulation,electrothermal modeling, and characterization of MOS devices. He maintainsclose contact with the microelectronics industry in India. He has designedseveral integrated circuits for the industry and has conducted training coursesfor them in the areas of VLSI technology and design. He has published over100 papers in reputed journals and conferences on these subjects. His currentinterests include mixed-signal VLSI, asynchronous design and the effect oftechnology and device scaling on design architectures and tools.Prof. Sharma is a Fellow of the Institution of Electronics and Telecommuni-

cation Engineers (IETE) and serves on the editorial board of Pramana, whichis the journal of physics of the Indian Academy of Science. Over the last fewyears, he has been also working on manpower training in the areas of microelec-tronics and VLSI design in India. He has served on several committees withinthe government which are trying to improve the general level of training in thisarea. He has also collaborated with the industry and coauthored a widely quotedreport with Dr. F.C. Kohli of Tata Consultancy Service on this subject. He wasa recipient of the Bapu Sitaram Award of the IETE for Excellence in Researchand Development in Electronics in 2001.

a variation tolerant current-mode signalling scheme for on-chip interconnects

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