A Wireless RF CMOS Interface for a Soil Moisture Sensor

Raul Morais1, A. Valente1, C. Couto2 and J. H. Correia2

1UTAD University, Dept. Engenharias, Quinta de Prados, 5000-911 Vila Real, Portugalemail: rmorais@utad.pt http://www.utad.pt/˜aci

2University of Minho, Campus de Azurem, 4800-058 Guimaraes, Portugal

Summary. This paper describes a wireless RF CMOS interface for a soil moisture sensor. The mixed-signal interface is based on a2ndorder switched capacitor, fully differential sigma-delta modulator withan effective resolution of 17-bit. The modulator bit stream output is applied to a counter as a first orderdecimation filter and encoded as a pulse width modulated signal. This signal is then transmitted bymeans of an amplitude shift keying modulation, through a power amplifier operating at433.92 MHz inclass-E mode. The soil moisture sensor is based on Dual-Probe Heat-Pulse method and is implementedusing an integrated temperature sensor and heater. After applying a heat-pulse, the temperature risethat is a function of soil moisture, generates a differential voltage that is amplified and applied to themixed-signal interface input. The described interface can also be used with other kinds of environmentalsensors in a wireless network for agricultural environments such as greenhouses. The CMOS mixed-signal interface has been implemented in a single-chip using a standard CMOS process (AMI0.7 µm,n-well, 2 metals and 1 poly).

Keywords: Wireless, Sigma-Delta, Soil-Moisture SensorsCategory: 9 (System architecture, electronic interfaces, wireless interfaces)

1 Introduction

The control of physical and chemical variables in agri-culture fields require the use of several sensors, as soiltemperature and relative humidity,CO2 concentration,solar radiation, soil moisture, among others.

An important goal in agricultural exploitations itis the need to minimize natural resources over-consumption, namely water supply in irrigation sys-tems. Irrigation management systems should have in-formation about soil moisture at the plant root level.With such information, only the necessary water couldbe provided in an efficient way.

Today a large number of sensors based on differ-ent methods are available for measuring soil moisture.However, they present a few drawbacks: as inaccuracy,high-cost and soil dependency.

Integrated microsensors, with on-chip interface cir-cuitry, are currently replacing discrete sensors due totheir inherent advantages, namely, low cost, high reli-ability and on-chip processing. To accomplish small,robust and inexpensive microsystems, it is desirableto integrate the soil moisture sensor with digital sig-nal processing and wireless front-end. Therefore, thismicrosystem can be installed near plants roots for mea-suring real plant water needs.

2 System overview

The complete system is divided in two blocks, as de-picted in Fig. 1: the sensing system and the mixed-signal interface.

Fig. 1: System Overview.

The sensing system is based on a dual probe wherein one rod is placed a heater and in the other rod a tem-perature sensor. A special package will allow its imple-mentation near plants roots.

The implemented CMOS mixed-signal interface,outlined in Fig. 2, includes a2ndorder switched-capacitor fully differential sigma-delta (Σ∆) modula-tor, a first-order decimation filter, a shift register andframe generator, a pulse width encoder, an amplitude-shift-keying (ASK) modulator and a RF switch. The433.92 MHz carrier is generated on-chip by means ofa phase-locked loop (PLL).

3 Mixed-signal interface

The water in the soils must be measured with a resolu-tion better than1%. The sensing system, developed ina previous work, [1], has a differential output of about6825µV/m3m−3 and signal bandwidth is typically a444

Fully Differential

SC Second-Order

Sigma-Delta

Modulator

Clo

ck P

hase

Gen

erato

r

Shift Register & Frame Generator

433.92 MHz

Frequency

SynthesizerCrystal

Oscillator

Clock

Generator PWM Encoder

ASK Modulator

RF Driver &

Switch

First-order Decimation Filter

13.56

MHz

433.92

MHz

PWM Serial Out

13.56 MHz

13.24 kHz423.75 kHz

423.75

kHzBitStream

(+)

(-)

16-bit

Class-E

Matching

Network

CMOS AMI 0.7m13.56

MHz

Inpu

t

Fig. 2: Mixed-signal interface architecture.

few Hz.

3.1 Analog section

Previous studies have showed that a second-orderΣ∆modulator is a suitable architecture for converting thiskind of signal to digital domain. The second-orderarchitecture is preferred to the simpler first-order onebecause it is less sensitive to the correlation betweenthe input and the quantization noise, which reduces thepresence of pattern noise [2].

The2ndorderΣ∆ modulator has been implementedusing switched capacitor techniques. In addition to ro-bustness of these techniques, the use of fully differen-tial topology minimizes common mode interferences,switches charge injection and clock feedthrough. Thetwo integrators are based on fully differential folded-cascode amplifiers biased by a constant-gm wide swingcircuit. Also, for reducing the influence of the first-amplifier offset and low-frequency noise, a chopperscheme has been implemented. The modulator refer-ence is external and set to±0.5V . The completeΣ∆modulator is shown in Fig. 3.

The dominant sources of error in theΣ∆ modulatorare quantization and thermal noise. A clock frequencyof 423.75kHz with an oversampling ratio (OSR) of256 was chosen to make the quantization noise in-significant. This results in an input signal bandwidthof about830Hz which is fairly above the requirement.Thermal noise is essentiality determined by the size ofsampling capacitors which are in our case6pF .

The amplifiers used in theΣ∆ modulator are basedin a fully-differential folded-cascode topology. ANMOS-input topology was preferred to a PMOS-inputone because PMOS transistors generate more thermalnoise (for the same dimensions and current). Thehigher flicker noise associated to the NMOS transis-tors will be reduced by the chopper action. Also, inputtransistors were chosen to be large enough to minimizesystematic offset by employing matching techniques.

Σ∆ modulators show low sensitivity to the errors in-duced during internal quantization. In our case, havinga single-bit (two-level) quantization, errors are limitedto offset and hysteresis. For a2ndmodulator the offsetis attenuated byA2

V , whereAV is the amplifier open-loop low-frequency gain. The hysteresis, as an inde-termination of the output state for small input values,is also attenuated by the high DC-gain of the integra-tors. This low-demanding performance requirementsleads to a simple solution based on a clocked compara-tor followed by a NOR SR flip-flop with minimum sizetransistors to reduce resolution time.

Special care has been taken in the layout of theΣ∆ modulator which was manually routed. Allmatched transistors and capacitors have been laid us-ing common-centroid techniques. The switches usedin the SC implementation are all transmission gates.

3.2 Digital section

The bitstream output is applied to a counter as a1storder decimation filter as seen in Fig. 4. The time-base circuit generates a signal to latch the counter dataand afterwards a reset signal to clear the counter.

423.75kHz TimeBaseClock

Lached Data

Latch

Reset

32

14-bit Counter

13.2kHz

. . .

Latch

Bitstream

D0 D13

Latch

Latch

Reset

To PWM

Encoder

Fig. 4: First-order decimation filter.

For each counting, a sample is generated, stored andtransmitted. Prior to transmission, data is encoded inpulse widths of25 % and75 % duty-cycle represent-ing the logic levels ’0’ and ’1’ respectively. For errordetection and receiver synchronization, data is assem-bled together with a11 − bit preamble and a4 − bitchecksum. The assembled frame has a29− bit lengthand takes about4.39ms to be transmitted. The PWMencoder as well as the frame generator block diagram isshown in Fig. 5. The resulting frame is then transmit-ted by means of a amplitude shift keying modulation.The modulated signal is then applied to a class-E poweramplifier that drives a small off-chip loop antenna totransmit the signal.

3.3 RF transmitter module

The RF transmitter module schematically representedin Fig. 6, includes a crystal-controlled frequency syn-thesizer, a PWM encoding circuit, an ASK modulator, aRF driver and a RF switch. With the convenient match-ing network, the transmitter operates in Class-E mode.

By using a simple modulation scheme such as ASK,where the carrier is switched on and off, carrier fre-quency generation circuit can be relaxed. In this way,445

2

1

2

1

VCM

12

21

1d

FDFC OTA

CB3

2d

2d

1d

1d

2d

1d CB32d

CB1

CB1

Dd

Cd

Chopper

CB2

CB2

FDFC OTA

CA2

CA2

D

C

Chopper

2

2

1

VCM

1

2d

2d

1d

1d

CA1

CA1

Input

Ref

Ref

Ref

Ref

1

Bitstream

Fig. 3: Complete2ndorder SCΣ∆ modulator.

CLR

QD

CLR

QD

QD

Q

VDD

Latch

13.2kHz

PWM Out

FRAME

Shift Register

Serial Out

Load

Clock Serial Out

Parallel Data(from Latches)

CheckDataPreamble Wait

Fig. 5: Shit register and PWM encoder block diagram.

RF Driver

&

RF Switch

Vdd

RFC

L1 C2

C1 C3

L3

RLOAD

Crystal

Oscillator

13.56

MHz

Serial DATA

Class-E Matching Network

CMOS AMI 0.7m

13.56

MHz

Phase

Locked

Loop

PWM

Encoder

ASK

Modulator

433.92 MHz

Fig. 6: Transmitter module diagram.

and to ensure carrier stability, the frequency synthe-sizer was implemented as a classical phase-locked loop(PLL) using a13.56 MHz crystal reference oscillator.

The PLL consists of a phase-frequency detector(PFD), charge pump (CP),3rd order passive loop filter,current-starved voltage-controlled oscillator (VCO),and a fixed divider, as shown in Fig. 7. The phase-frequency detector identifies phase and frequency dif-ferences between the reference and the divider signals.With the charge pump and loop filter these differencesare converted into a control voltage to adjust the outputfrequency.

The phase-frequency detector generates two signals,Up andDown, that controls the charge pump to chargeand discharge the loop filter equivalent capacitorCLF .Special care has been taken to avoid overlapping be-tween these signals that leads to a short circuit in thecharge pump. Also, a delay was inserted in the path

Crystal

Oscillator13.56

MHz

CMOS AMI 0.7m

13.56 MHz

PFD433.92

MHz

Charge

PumpVCO

K =91MHz/VVCO

32 32

423.75 kHz

13.56 MHz

Clock

Up

Down

Comp

Ref

ASK

Modulator

PWM

Encoder

Serial Data

Spur Attn = 26dB

K =300 A/2pf m

Current-StarvedLF

CF1

RF1

CF2

RF2 CF3

Fig. 7: Phase Locked Loop Block Diagram.

of reset signal to eliminate the dead-zone problem thusreducing the phase noise of the PLL.

In a conventional CMOS charge pump, the switchescontrolled by theUp and Down signals are directlyconnected to the output node. When one of theswitches are turned on, the charge on the LF equivalentcapacitor,CLF , will be shared with the switch parasiticcapacitance. This induces glitches in the charge pumpcurrent which increases spurs in the PLL output signal,[3]. In the implemented charge pump,Up andDownsignals are used to switch on and off a current mirrorwith current matching, thus avoiding charge sharing inthe CP output node. The charge pump current was de-signed to be300µA.

The 3rd order passive loop filter comprises an off-chip2nd order filter section(RF1, CF1 andCF2), con-nected to the LF pin and an internal RC section (RF2

andCF3) providing an extra pole to assist the attenu-ation of the sidebands at multiples of the comparisonfrequency (spurs) that may appear. The resulting PLLis then a type-2 fourth-order loop which provides greatnoise supression in the PLL output spurious level.

The VCO is based in the current-starved configu-ration with five delay stages. To avoid the problemof locking on harmonics of the desired output fre-quency, the maximum output frequency has been lim-ited. Output frequency range is between330MHz and500MHz. The433.92MHz carrier frequency is ap-proximately the VCO center frequency and is obtainedfor an input voltage of about2.3 V .446

4 Results

Simulations from the extracted layout have shown thatit can be expected an effective resolution of about17bit(DR = 103.36db) for theΣ∆ modulator. The quanti-zation noise power,PQ, is−112.28db. Thermal noisecontribution,PTH , mainly due to the6pF sampling ca-pacitors, is−115.57db. Incomplete settling error in thefirst integrator isPST = −108.87db.

As a prototype, and for testing purposes, the outputof the modulator (bitstream) is available outside for off-chip digital filtering and decimation. For this prototypeit was chosen to process internally 14-bit samples fortesting the digital section and the RF transmitter. In thiscase, conversion time is38.8ms for a clock frequencyof 423.75 kHz.

The PLL has a simulated lock time of about6µs asshown in Fig. 8. Loop filter values wereRF1 = 3.9k,CF1 = 220pF , CF2 = 12.2pF , RF2 = 33k andCF3 = 1.5pF .

0 1 2 3 4 5 6 7 8

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Time ( S)m

VC

O Inp

ut (V

)

K = 90.5MHz/VVCO

Pump Current =300 Am

Phase Margin = 51.5o

Lock time = 6 sm

Damping ( )=0.82x

Loop Bandwidth =500kHz

Fig. 8: PLL Simulated lock time.

Fig. 8 shows the simulated transfer function ofthe voltage-controlled oscillator. The VCO constant,KV CO, is approximately90.5MHz/V .

300

350

400

450

500

550

0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5

VCO Input Voltage (V)

VC

OO

utp

ut

Fre

qu

en

cy(M

Hz)

K = 90.5MHz/VVCO

Fig. 9: VCO transfer function.

Fig. 10 shows a binary pattern ’011’ PWM encodedsignal (A) and transmitted signal (B) in a50Ω load.

In this first prototype, the typical class-E matchingnetwork is off-chip. Since component values are suitedfor integration, they will be on-chip in the next pro-totype. Fig. 11 shows the layout of the implementedmixed-signal interface. Die area is3.79mm2.

(433.92 Mhz, 50 Load)W

Time ( s)m

PW

M s

ignal, R

F O

utp

ut (V

)

(A)

(B)

Fig. 10: PWM signal and RF output signal.

Fig. 11: Layout of the described mixed-signal interface.

5 Conclusions

In this paper a Wireless CMOS mixed-signal interfacefor a soil moisture sensor has been proposed. Chiplayout has been submitted to fabrication through Eu-ropractice IC service. A set of experiments has to bedone for testing the reliability and precision of results.

Some enhancements are now being carried out, suchas a receiver, among others. With bidirectional commu-nications capabilities, it will be possible to implementa wireless network of soil moisture sensors in a smartirrigation control system.

References

[1] A. Valente, Raul Morais, C. Couto and J. H. Cor-reia, A MCM-based micro-system for soil moisturemeasurementsEurosensors XVI, Prague - CzechRepublic, 15-18 September, 2002, 447–448.

[2] J. C. Candy. A Use of Double Integration in Sigma-Delta Modulation.IEEE Transactions on Commu-nications, 33 (1985) 249–258.

[3] Chih-Ming Hung and Kenneth K. O. A fully Inte-grated 1.5V 5.5-GHz CMOS Phase-Locked Loop.IEEE Journal of Solid-State Circuits, 37, April,(2002) 521–525.

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