Abderrezak Mekkaouiamekkaoui@lbl.gov

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General Outline

IntroductionA glance at the current ITRS roadmap for analogSome 65nm device test resultsSome examples of current projects FEI4 (ATLAS) ATPIX65 (LBNL) APSEL(INFN) MAPS (LBNL) HIPPO (LBNL)

Vertical integration: 3DConclusionsBackup slides and extras

NOTE: throughout this presentation, HEP denotes High Energy Physics and similar fields

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IntroductionPerformance and functionality of integrated circuits continued to increase for the past few decades. Technology scaling (down) has fueled what is known as Moore’s law (or is it vice versa?): the number of components per chip roughly doubles every 24 months.Transistor dimensions (width, length and gate thickness) are continuously decreased and so are the metal pitch while the number of metal levels has been increased. Process optimization for some niche market (like RF) has also led to multi-threshold and multi-supply transistors along with high quality passives.While scaling down is still going on, industry experts are already introducing the concept of “more than Moore” to prevent the increase of performance of ICs from slowing down (physical scaling down will ultimately be unpractical).Without the advances in IC technology, some important HEP projects (at some crucial time) would have been not feasible or would have required specialized low yield low performance high cost processes.The future will be no different. Complex and challenging instrumentation projects (Upgrades, SLHS, new Detector concepts) will require the adoption of the ever more empowering (and more complex) IC technologies. This is exemplified by recent design activities using the 65nm CMOS node, which is the state of the art for this community. This talk will briefly describe some of the prototyping work in 65nm CMOS (mainly).

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Industry and HEP IC “nodes”

A. Baschirotto, University of Milano-Bicocca“LV Analog Design in scaled CMOS technology”

(image without the HEP figures)

250nm, 70Mrad special layout

130nm, 250Mrad

65nm, >200Mrad

HEP projects, even though lagging mainstream technology, are benefitting fromTechnology scaling. There should be a “topical” Moore’s law.ICs are only one part of an instrumentation system! Is detector technology not keeping pace?

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ITRS performance RF/Analog roadmap

Year of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021

Supply voltage (V) 1.1 1.05 1.05 1.05 1 0.95 0.95 0.95 0.85 0.85 0.85 0.85 0.75

Tox (nm) 1.2 1.2 1.2 1.2 1.10 1.10 1.10 1.10 1.10 1.00 1.00 0.90 0.90

Gate Length (nm) 38 38 32 29 27 22 18 17 15 14 13 12 11

gm/gds at 5·Lmin-digital 30 30 30 30 30 30 30 30 30 30 30 30 30

1/f-noise (µV²·µm²/Hz) 100 90 80 70 70 60 50 50 40 40 40 30 30

s Vth matching (mV·µm) 5 5 5 5 5 5 5 5 5 5 5 4 4

Ids (µA/µm) 9 9 8 7 7 6 5 4 4 3 3 3 2

Peak Ft (GHz) 240 240 280 310 340 400 480 520 570 630 680 750 820

Peak Fmax (GHz) 290 290 340 380 420 510 610 670 740 820 900 990 1090

NFmin (dB) 0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2

Notice difference between Performance versus precision (next slide)ITRS key: Yellow=solution known but not optimized. Red= solution not known. http://www.itrs.net/

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ITRS Precision Analog/RF roadmapYear of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021

Supply voltage (V) 2.5 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.5 1.5 1.5

Tox (nm) 5 3 3 3 3 3 3 3 3 3 2.6 2.6 2.6

Gate Length (nm) 250 180 180 180 180 180 180 180 180 180 130 130 130

gm/gds at 10·Lmin-digital 220 160 160 160 160 160 160 160 160 160 110 110 110

1/f Noise (µV²·µm²/Hz) 1000 360 360 360 360 360 360 360 360 360 270 270 270

s Vth matching (mV·µm) 9 6 6 6 6 6 6 6 6 6 5 5 5

Peak Ft (GHz) 40 50 50 50 50 50 50 50 50 50 70 70 70

Peak Fmax (GHz) 70 90 90 90 90 90 90 90 90 90 120 120 120

Tox decreasing: better ionizing radiation resistance. Gate rupture? Other problems?Gm/gds decreasing: Lower gain1/f noise decreasing.Matching improving (barely and only for analog devices)Speed increasingSupply voltage decreasing: reduced Dynamic range.Other: gate leakage, off current, variability of non analog transistors …

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The main design challenges (my experience)Gate leakage Big problem biasing/controlling large

number of transistors in parallel (pixels).Current is proportional to gate area: can be problematic for low noise large cap FENDs (wide input transistor)

Be Aware the problem. Can be serious. Realistic simulations is a must. Design Bias DACs to handle the excess current.Use higher voltage devices, if possible (be aware of radiation issues).

Off leakage current

Problem for low current circuits. May lead to higher power (increase operating currents to dwarf leakage)

Use low leakage transistor variants (order of magnitude lower).Creatively live with it.

Low Supply voltage

Reduced Dynamic range. May lead to higher analog power. Problem for high precision/accuracy systems

Use rail to rail circuits. LV circuits techniques…

Highly layout dependent device parameters

Makes design more complex. Requires a high quality design kit

Read the manuals (obvious but …). Check the effects are back annotated for simulations.

It is only a problem of degree. Analog design has always been about designing workingcircuits using imperfect devices. Good circuits were designed in NMOS only single metalSingle poly processes! Read IEEE JSSC!

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ITRS bipolar RoadmapYear of Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 20211/f-noise (µV²·µm²/Hz) 2 1.5 1.5 1.5 1 1 1 1 1 1 1 1 1s current matching (%·µm) 2 2 2 2 2 2 2 2 2 2 2 2 2High Speed NPN (HS NPN) - Common to mmWave TableEmitter width (nm) 130 120 110 105 95 90 85 80 75 70 65 65 60Peak fT (GHz) 265 285 305 325 345 365 385 405 425 445 465 485 505Peak fMAX (GHz) 310 350 390 430 470 510 550 590 630 670 710 750 790Maximum Available Gain (dB) @ 60 GHz 12.0 12.9 13.6 14.3 15.0 15.6 16.1 16.6 17.1 17.5 18.0 18.4 18.7

Maximum Available Gain (dB) @ 94 GHz 8.0 8.9 9.6 10.3 11.0 11.6 12.1 12.6 13.1 13.5 14.0 14.4 14.7

NFMIN (dB) @ 60 GHz 2.5 2.0 1.6 1.3 1.1 0.9 0.8 0.7 0.6 0.5 0.5 0.4 0.4BVCEO (V) 1.7 1.7 1.6 1.6 1.5 1.5 1.4 1.4 1.4 1.3 1.3 1.3 1.2JC at Peak fT (mA/µm2) 14 15 16 18 19 20 22 23 24 26 27 28 30

High Speed PNP (HS PNP)

Emitter width (nm) 500 500 300 300 200 200 200 200 200 150 150 150 150Peak fT (GHz) 25 40 60 80 85 95 105 115 125 135 145 155 165Peak fMAX (GHz) 40 50 80 90 95 105 115 130 140 150 160 170 180BVCEO (V) 5.5 4.0 3.0 2.5 2.2 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.4

For specialized projects.Main challenge: breakdown voltage getting lower.

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Advanced IC processes are available thru brokers32 nm 0.9 /1.5 7th generation IBM SOI technology improves energy savings for high-

performance servers, printers, storage devices; networking, mobile, consumer, and game applications. Trusted foundry access only.1

45 nm 1.0 /0.9 This energy-saving SOI process is suitable for a broader range of consumer electronics, including digital TVs and high-end mobile applications. Trusted foundry access only.1

65 nm 1.0 /1.8, 2.5 Excellent for consumer electronics, wireless communications, and other applications requiring high performance or system-on-a-chip. Trusted foundry access only.1

1.2 /2.5 Tailored for power-sensitive applications in wireless communications and consumer electronics. Trusted foundry access only.1

90 nm 1.0 /2.5 Ideal for leading-edge microprocessors, communications, and computer data processing applications. Trusted foundry access only.1

1.2 /2.5 Use for low-cost, high performance wireless applications, as Bluetooth, WLAN, cellular handsets, mobile TV, WiMax, UWB and GPS. Trusted foundry access only.1

130 nm

1.2 /2.5 Use for low-cost, high performance wireless applications as Bluetooth, WLAN, cellular handsets and GPS.

1.2 /2.5 Similar to 8RF-DM, but uses LM top metal.

40 nm

Low-power logic

65 nm

Standard logic, RPO Mixed-mode/RF, RPO, MiM

90 nm

Standard logic, RPO Mixed-mode/RF, RPO, MiM

0.13 µm

Standard logic, RPO Mixed-mode, RPO, MiM Low-power logic, RPO Low-voltage logic, RPO TSMC CMOS (mosis)

IBM CMOS (mosis)

VDD

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Advanced IC processes available thru brokersIBM SiGe BiCMOS Processes

Feature Size

CMOS Vdd [V]

SiGe Ft [GHz] | BVceo(1) [V]

Description

HP Ft/BVceo

HB Ft/BVceo

0.13 µm 1.2, 2.5, 3.3

200 | 1.77

57 | 3.55

5th generation SiGe technology for advanced RADAR and mmWave applications.

1.2, 2.5, 3.3

103 | 2.4 54 | 4.7 Reduced performance, cost effective technology for wireless applications.

0.18 µm 1.8, 2.5, 3.3

120 | 2.0 20 | 4.75

4th generation SiGe technology best suited for wireless and high-speed switches.

1.8, 2.5, 3.3

60 | 3.3 29 | 6.0 Reduced performance, yet most cost effective SiGe technology offered.

0.25 µm 2.5, 3.3 47 | 3.3 27 | 5.7 3rd generation SiGe technology.

2.5, 3.3 60 | 3.2 29 | 6.0 A descendant of 7WL, it integrates 0.25 µm CMOS with the 7WL SiGe NPN.

IBM BiCMOS SiGe (mosis)

28 nm CMOS28LP CMOS 7LM

40 nm CMOS040 CMOS 7LM

65 nm CMOS065 CMOS 7LM

65 nm CMOS065-SOI SOI 6LM

St Micro CMOS (cmp)

Other less advanced and specialized processesare available thru mosis, cmp, europracticeAnd others!http://www.mosis.comhttp://cmp.imag.fr/http://www.europractice-ic.com/

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Area reduction Highest for mostly digital systemsFor analog design, most of the challenges can be addressed by proper device selection and design. But at the expense of increased area: Reduce analog functionality to the minimum to benefit from the ever increasing integration density in advanced process. Analog “deficiencies” can be mitigated by special digital techniques.

Die area reduction based on analog/digital mix (A. Baschirotto )

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Harnessing digital processing power (a physicist perspective)

Complex pattern recognition on chip Cluster formation, including NN-style. Rejection of background clusters- eg. from beam halo particles Generic user-programmable DSP

Pulse shape analysis. Digital corrections for anything and everything (eg. Time-walk).

Self-repairing or self-testing designs. Either 100% yield or chips that automatically report their quality upon power-up (second probably easier)

Self calibrating, self timing-in, etc. No need to save and download threshold tunes, for example, because threshold is

automatically tuned on-chip in real time. Automating monitoring, interlocking, etc. Configurable geometry. Not all pixels have to be used. User selects desired density

lower density = lower power and greater bump bonding pitch Prompt hit processing (complex and fast processing of hits from pixel columns)

M. Garcia-Sciveres, Atlas Upgrade Week 11/16/11

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Illustration of the Power of integration

>One 32bit ARM11 processor core Per 4 columns (65LP)!Fits in the dead area!

FEI4: 0.13m ATLAS Pixel ROC~ 20mm X 20mmSize would probably remain the same if implemented in65 nm

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65nm: Some transistor test result

M. Manghisoni et al. TWEPP 2011

Same gate capacitance No noise degradation at lower nodesNo thermal noise increase with radiation No or little 1/f noise increase with radiation

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65nm: Some radiation tolerance resultsThreshold voltage Leakage current

S. Bonacini et al. TWEPP 2011

65 nm devices seem to outperform their 130nm counterparts in theirtolerance to ionizing radiation !

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Example 1: FEI4A (ATLAS PIXELS FOR IBL)FEI4A FEI3

Year 2010 2003

Technology 130nm 250nm

Chip size 20x19mm2 7.6x10.8mm2

Active area 89% 74%

Array 80x336 (26880)

18x160 (2880)

Pixel size 50x250μm2 50x400μm2

Number of transistors

87M 3.5M

Data rate 320 Mb/s 40Mb/s

Wafer yield 65% * 80%

FEI4A 0.13u processPerforms also most of a moduleController chip duties

FEI3 0.25u process Copes with higher hit rate: regional architecture and smaller pixel size

Improved cost effectiveness: Large chip with large active area Lower power: Improved design and architecture Increased radiation tolerance (~250Mrad)

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FEI4 (cont’d)• Column drain architecture (a la FEI3) saturates at high rate

– All pixel hits are sent to periphery – Column based readout induces dead-time (during data transfer to

periphery and column readout) • ATLAS solutions for higher rate

→ Development of regional architecture in FEI4 enabled by migration to a finer process

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FEI4 PIXEL REGION• FEI4 is organized in digital regions serving 4 analog pixels• Hits are stored locally during L1 latency

– 5 ToT memories per pixel, 5 latency counters per region• Hits are not moved unless triggered

– only 0.25% of hits are sent to periphery• Lower digital power consumption (6μW/pixel at IBL occupancy)

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FEI4: Pixel front end

Cc

Cf2Cf1

Preamp Amp2

feedbox feedbox

Inj0

Inj1

injectIn

Cinj1

Cinj2

+local

feedback tune

FDAC4 Bit

Vfb

+local

thresholdtune

TDAC5 Bit

Vfb2

+

-

HitOutNotKill

Vth

• Similar design of analog pixel in FEI3/FEI4• Two-stage amplification• Clock is distributed to all digital pixel region• ToT counters within pixel digital region• ToT together with pixel address sent to periphery

FEI3 FEI4

ToT 8 bit 4 bit

TDAC 7 bit 5 bit

FDAC 3 bit 4 bit

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FEI4A: A result

1500 2000 2500 3000 3500 4000 5000

103

102

10

110-1

Constant 849Mean 3178Sigma 403

2700 2900 3100 3300 3500

103

102

10

110-1

Constant 2865Mean 3100Sigma 26

• FEI4 bump-bonded to planar and 3D sensors have been successfully operated in lab test, test beams and cosmic data taking

• Tuned threshold dispersion ~30e • FEI4 low threshold operation (~700e) shows promising results with

reasonable dispersion• Irradiation tests with bare chips show no effect on threshold

dispersion and 20% increase in noise

Threshold tuning at 1400e

Threshold [e]

Threshold [e]

before tuning

after tuning

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Example 2: ATPIX65, next generation Atlas pixel readout prototype

To explore the capabilities of advanced CMOS processes to address future HEP needs (upgrades, SLHC, )To have a feel of what is the best way these processes should be used to maximize ROI.To evaluate radiation hardness (mainly SEU and new damage mechanisms, if any!)To keep abreast of the state of the art (if one can).

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Pixel region (2X2) a la FEI4 if implemented in 65nm

Region logic synthesized from FEI4 verilog.Neither 100% complete nor verified.Just to have an idea on what is possible Pixel size=50X100 (?)

~FEI4 AFE equivalent

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“FEI5” 2X2 REGION (100X200)

=> Substantial area reduction=> Ultimately the width of a pixel will limited by practical considerations (power distribution) and not the number of transistors!=> Room to add functionality

FIE4 pixel region Vs Pix65nm region (assuming y=50u)

FEI4 2X2 REGION (100X500)

If area to be kept the same as FEI4, about 4X more logic can be added

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Snapshot of submitted pixel array

25 mm y cell pitch but 50mm bump y picth. Power distribution will be major factor in the ultimate minimum dimensionsBump mask not part of the submitted layout (same size as FEI4)

Analog FE Config. Logic FutureDigitalRegion

nXm pixels

Analog FEConfig. Logic

Bump opening

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ATPIX65A FEND BLOC DIAGRAM

Inject Bloc Preamp.17fF Feeback cap.Variable “Rff”

Single to differential+Comparator “preamp”

Comparator

TDAC (+/- 4b tuning)

Passive RC: gate leakage limited

Uses only 65nm Transistors2mA to 25mA @ 1.2V

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ATPIX65A: Atlas Pixel prototype array

Pixels withAddedsensors(row 11:31)

Pixels withAddedmimcaps(31,27,22,18)

16 X 32 array25m X 125m pixels

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Preliminary test results

Preamp out

Single to Diff. out

Chan 15/32 Qin: 2ke

Chip found to work as expected!VDD=1.2VI= 5mA per pixel (can be as low as 2mA)

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Qin=10ke-; 5IFF settings

Chan 15/32 Qin: 2ke to 10ke-

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ATPIX65A: Noise and Threshold distribution

Channels with caps or diodes

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ATPIX65A: ENC for some columns

. . . .Channels withmimcaps

Channels withDiodes (3 types)

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Fe55 spectrum as detected by one of the integrated sensors

Chip2 high gain mode. Sensor@-8VVery preliminary! Work in progress!

1040e- pulser injection~3.7keV. Assuming Cinjto be nominal.

2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?)

5154 KeV (theory; 5.9KeV?)

For the experiment to agree with theory (for the 5.9KeV), injection cap has to be corrected by 15% . Still being reviewed!

Noi

se a

rtific

ially

Lim

ited

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Example 3: Apsel65 65nm pixel front end with MAPS

L. Gaioni et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 163–168

DNW-MAPS FFE Power consumption(mW) 20 6 ENC (e-) 38 200 Charge sensitivity(mV/fC) 725 40 Peaking time(ns) 300 25

Fast Front End forHigh resistivity pixels

Integrated sensor

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Example 4: Fast, rad-hard CMOS direct detectors for TEM

0.35 um CMOSTEAM2k(2009)

9.5m pixels4Mpix, 400 f/s

0.18 um CMOS K2 sensor (2010)

5m pixels16Mpix, 400 f/s

Improved radiation tolerance

Commercial product

0.35 um CMOS(2009)

TEAM1k1 Mpix

HIPPIX (2011)65nm proto

Fabricationprocess

Pixel pitch [µm]

ConversionGain

[µV/e-]

Noise[e-]

Leakagecurrent

[fA]

Welldepth

[e-]

0.35 µm 9.5 9.4 30 10 90000

0.18 µm 5.0 15.5 35-40 4 23000

65 nm 2.5 21 50 8 18000

B.Krieger, TNS 2011

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Example 4: HIPPO, a column-Parallel CCD readout (for X-ray imaging and muon collider applications)

Megapixel square sensor has ~1000 columns @ 50 μm pitch need custom IC readoutNo room for output amplifier need charge-sensitive readoutUltimate applications require intensive DSP advanced CMOS process65nm CMOS found to be the most adequate

35 e- @ 10 Mpix/s

Custom 65nm CMOScolumn-Parallel LBNL CCD

C. Grace, TNS 2011

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HIPPO prototype chip

4 ADCs16 SHAs16 AnalogFront ends

4200 μm

SERD

ES

(480

Mb/

s)

12b (80 Msps)

HV input transistor to achieve the required noise level. Nominal transistor is too leaky!

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HIPPO results (mixed simulation and measurements)

Resolution 12 b @80MHz

Noise 0.77 b

Linearity 10 b

Serial output 480 Mb/s

ADC Pitch 200 μm

ADC Area 0.35 mm2

Power per ADC 30 mW

Full Scale 50k / 1M e-

CCD charge 200ke-

Input noise 35 /24e-

Settling time < 15ns

Charge loss < 1%

Linearity 10 b

Power 5 mW

ADC

Preamp

J.P. Walder, TNS 2011

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ATLAS 3D EFFORT50

μm

400 μm

50 μ

m50

μm

< 50

μm

250 μm

FE-I4 CMOS 130 nm

125 μm

< 100 μm

FE-TC4 CMOS 130 nm 2 layers

FE-X5-3D CMOS xx nm 3 layers

A.Rozanov Atlas Upgrade Week 11/16/11

FE-I3 CMOS 250 nm

M5M4M3M2M1

M6

Super Contact

M1M2M3M4M5

M6

Super Contact

Bond Interface

Tier

2Ti

er 1

(thi

nned

waf

er)

Back Side Metal

sensor

Achieves integration verticallyOptimized “tiers”One of the “more than Moore” waysMany challenges!

Tezz

aron

/cha

rter

ed 2

tier

Exa

mpl

e

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ConclusionsUnprecedented advances in IC technology are offering new ways to implement readout systems (for all kind of detector systems).New challenges seem to be more addressable with scaled down technologies. Future systems will require smaller geometries, lower power, higher level of processing, high radiation tolerance, lower cost per function, …etcAmong the advantages of newer technologies are:

Very high integration densityInherent high radiation toleranceA reasonable number of device types for extra design flexibilityAvailability of high quality passivesA high number of metal levels

Skewing the mix of functional blocs towards digital would result in a better area usage and chip yield. Not to mention flexibility (programmability) and Productivity (think advanced digital tools)A myriad of challenges related to ultra complex processes and ultra small devices are associated with these technologies. For some of these, mitigation techniques are readily availableA unique challenge to the research community is perhaps the cost of these advanced processes (given the low volume usually involved). Common wisdom applies: for some applications plain old technologies would remain the optimal choice.

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AcknowledgementsMany Thanks to all people whose work has been mentioned and to my colleagues at LBNL For their help.Please refer to the referenced work for more exciting details.

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Backup slides

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ATPIX65: ENC Vs Diode bias

42

ATPIX65: ENC Vs Preamp Bias

43

ATPIX65: ENC Vs IFF (feedback current)

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ATPIX65: Threshold Vs Preamp current

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ATPIX65: Threshold Vs feedback current

46

Timewalk @Preamp current of 2ma and 0.2mA

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ATPIX65: Fe55 spectrum as detected by one of the integrated sensors

Chip2 high gain mode. Sensor@0V

(V)

Very preliminary! Work in progress!

?

?

48

Lower part of the Am241 spectrum as detected by one of the integrated sensors

http:

//sp

ie.o

rg/x

2006

0.xm

l?Ar

ticle

ID=x

2006

0

Chip1 low gain mode(V)

Very preliminary! Work in progress! Low statistics

?

?