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346 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 52, NO. 2, MAY 2010

Overview of Power Integrity Solutions on Packageand PCB: Decoupling and EBG Isolation

Tzong-Lin Wu, Senior Member, IEEE, Hao-Hsiang Chuang, and Ting-Kuang Wang

(Invited Paper)

AbstractMitigating power distribution network (PDN) noiseis one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are basedon decoupling or isolation concept, for suppressing PDN noise onpackage or printed circuit board (PCB) levels are reviewed in thispaper. Keeping the PDN impedance very low in a wide frequencyrange, except at dc, by employing a shunt capacitors, which canbe in-chip, package, or PCB levels, is the first priority way for PIdesign. The decoupling techniques including the planes structure,surface-mounted technologydecoupling capacitors, and embedded

capacitors will be discussed. The isolation approach that keepspart of the PDN at high impedance is another way to reduce thePDN noise propagation. Besides the typical isolation approachessuch as the etched slots and filter, the new isolation concept usingelectromagnetic bandgap structures will also be discussed.

Index TermsElectromagnetic bandgap (EBG), ground bouncenoise (GBN), high-speed digital circuits, mixed-signal circuits,power integrity (PI), simultaneously switching noises.

I. INTRODUCTION

POWER distribution network (PDN) design has became one

of the major concerns in designing high-speed circuits or

mixed-signal systems in recent years [1][4]. The challenge is

expected to increase in next decade, as electronic systems aredriven in the direction of faster digital speed, higher integration

with RF circuits, and higher throughput of data communica-

tion [5]. Table I shows the trend of high-performance micropro-

cessors predicted by the International Technology Roadmap of

Semiconductors (ITRS) in 2008 for the next decade [6]. As the

interconnect pitch decrease to 11.3 nm in 2022, the power and

on-chip clock speed are expected to increase to 14.3 GHz with

a corresponding decrease of the power supply level to 0.8 V

and a corresponding increase of the maximum power density

to 1.73 (W/mm2 ). These trends imply that the demands of fast

transient currents above the gigahertz range will significantly

increase for IC with lower dc power levels. The PDN noise

above gigahertz will be expected to be serious because the dis-tributed and parasitic effects of the PDN become dominant at

higher frequencies. The power integrity (PI) design will be more

Manuscript received October 30, 2009; revised December 7, 2009. Firstpublished February 17, 2010; current version published May 19, 2010. Thiswork was supported in part by the National Science Council, Taiwan, Chinaunder Grant NSC 96-2628-E-002-001-MY3 and in part by the National TaiwanUniversity under Grant 98R0062-3.

The authors are with the Department of Electrical Engineering and GraduateInstitute of Communication Engineering, National Taiwan University, Taipei10617, Taiwan, China (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TEMC.2009.2039575

TABLE ITREND OF THEHIGH-PERFORMACEMICROPROCESSORPREDICTED BY

INTERNATIONALTECHNOLOGYROADMAP OFSEMICONDUCTOR

challenging due to the wider bandwidth of the noise energy on

the PDN with a smaller noise margin in the dc power level.

The coupling between the PDN and the high-speed signal

channels will be another main source of PDN noise [7][10].

It is predicted that the speed of the point-to-point differential

signals for chip-to-board peripheral buses will be 40 Gb/s in the

next decade [6], [9]. The gigahertz-band noise caused by thedifferential via transition between the power/ground planes [7],

the crossing of the reference plane discontinuities like slots [8],

[9], and the unbalanced discontinuities on the connectors will

couple to the PDN [10]. The noise will either degrade the PI

or become a source of radiated emission [or electromagnetic

interference (EMI)] [10].

Three main issues could result from poor PDN design. They

are signal integrity (SI) issue, EMI issues, and platform in-

terference [also called RF interference (RFI)] issues. SI has

shown to be strongly correlated to the PI because the pull-up

or pull-down capability of the transistors is dependent on their

dc bias level. The SI in terms of jitter and the eye opening of

high-speed signals will be degraded by the fluctuated (or thenoisy) dc power level [1], [2]. The PDN noise can also prop-

agate through the package or printed circuit board (PCB) and

be the source of EMI. The radiation is through the antenna-like

structures, such as the I/O cables, chassis slots, connectors, or

heatsinks [11][13]. The RFI issue is the sensitivity (or through-

put) degradation for the RF communication circuits caused by

the near-field interference due to the PDN noise. It is expected

to be a challenging problem for the high-density integration of

RF and digital circuits in a compact package or system boards

[12][14].

There are two possible ways to reduce PDN noise. The first

priority way is keeping the PDN impedance very low in a wide

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WUet al.: OVERVIEW OF POWER INTEGRITY SOLUTIONS ON PACKAGE AND PCB 347

Fig. 1. Typical computer circuit system and the corresponding PDNs.

Fig. 2. Conceptual circuit model of a simple signal path from a transmitter toa receiver IC and their corresponding PDN.

frequency range, except at dc, by employing shunt capacitors,

which can be in-chip, package, or PCB levels [15][28]. Ide-

ally, it is the most effective approach to reduce PDN noise

because the low impedance PDN can immediately provide the

required transient currents to the switched transistors, and at

the same time, eliminate the noise from spreading throughoutthe whole PDN. However, practically, decoupling capacitors are

band-limited for providing a low-impedance path between the

power and ground due to the inevitable series inductance in

the implementation of the capacitor. The decoupling capacitors

will become inductive and ineffective in reducing the PDN noise

above the self-resonance frequency. In this scenario, the isola-

tion approach that keeps part of the PDN at high impedance is

another way to mitigate the PDN noise propagation. The typical

isolation approaches include etched slots on power or ground

planes [13], [29][34], a filter with beads [35], or electro-magnetic bandgap (EBG) structures [36][57]. This approach

is effective to prevent the PDN noise from coupling throughout

the whole PDN and is useful in solving some EMI and RFIproblems, but it is short of providing the transient current to the

switched transistors due to the inherent series high impedance

on the PDN.

II. FUNDAMENTALCONCEPT OFPI

A. Power Distribution Networks

Fig. 1 shows a typical computer/communication circuit sys-

tem and the corresponding PDNs. The CPU, memory circuits,

and the RF communication system in package (SiP) are the

three main parts of the system. Fig. 2 shows the conceptual

circuit model of a simple signal path from a transmitter to a

receiver IC and their corresponding PDN. The PDN from the

transistor level to the system level can be mainly described by

three kinds of elements, shunt capacitors, series inductors, and

distributed transmission lines.

The shunt capacitors are the key element to keep the PDN at

low impedance and to provide the necessary transient current.

The effective series inductance (ESL) of the capacitor causes

an ideal short-circuit at the self-resonant frequency (SRF). The

capacitor will become inductive above the SRF. In general, the

decoupling capacitors on-chip, package, or PCB levels can re-

sponse to the transient current in the frequency band of above

gigahertz, several hundred megahertz to gigahertz, and kilohertz

to megahertz, respectively, because the ESL is increased from

pico henry (pH) on the chip level to several nano henry (nH) on

the PCB level.

The other two elements, series inductor and the transmission

line, are the parts that cause PDN noise because they will impede

the transient current demand from a switched transistor. The

electrically short power/ground interconnects from chip to PCB,

such as the bonding wires that connect from the chip pads tothe package substrate or the soldering balls that connect the

package to the PCB are described by the series inductor. The

distributed power/ground traces or planes on the package or

PCB are described by the transmission lines.

B. Mechanism of PDN Noise Generation

As shown in Fig. 2, there are two main mechanisms for ex-

plaining PDN noise generation. The first is the transistor tran-

sient current passing through theseries inductor of thePDN [58].

The induced voltage variation (V =L(di/dt)) on the poweror ground nets will be enhanced as many transistors are switched

simultaneously. The second mechanism is the voltage fluctua-

tion caused by the standing wave or the cavity resonance on

the distributed power/ground traces or planes [59][62]. This

power/ground bounce noise (GBN) can couple throughout the

distributed PDN and degrade the PI of the circuits that share

the same PDN. As shown in Fig. 2, the PDN resonance can be

excited through the interaction of the signal traces and the PDN,

such as the via transition through the power/ground planes or a

signal passing through the etched power/ground planes.

C. PDN Performance Evaluation

The impedance parameter and the scattering parameters aretwo different ways to evaluate the PDN performance. The

Z-parameter in terms of self-impedance Z11 (or targetimpedance) and transfer impedance Z21 is generally used toevaluate the low impedance PDN with decoupling capacitors

[16]. However, theS-parameter in terms of insertion loss (S21 )is often employed to evaluate the high impedance part of the

PDN with the isolation solutions.

As shown in Fig. 2, the target impedance ( Z11 ) is a usefulparameter to relate the active circuits design with the PI design

by [16]

Zr = V

50% Im ax(1)

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Fig. 3. Typical example of the power/ground plane structure for package and

PCB.

where V is the allowed power supply ripple for the activecircuits andIm ax is the maximum transient current demandedfrom circuits. Ideally, if the PDN can be designed to satisfy

the criterion Z11 < ZT in all frequency bands of interest, thecircuit can work well and be stable. However, in reality, it is

a strict criterion that is not easy, and sometimes, not necessary

to satisfy. The reasons are the target impedance based on (1)

will be very small for future high-performance circuits. It is

not easy to achieve in practical PDN design. Another point is

that the target impedance should be frequency dependent due

to the allowed voltage variation Vand the transient currentdemand for the active circuits are frequency dependent. How to

define a suitable specification for the frequency-dependent target

impedance profile is another challenge for both circuit and PDN

designers, but it is not the focus of this paper. However, it is clear

that keeping the PDN impedance as low as possible in a wide

frequency range, is helpful for avoiding SI and electromagnetic

compatibility (EMC) issues. Discussing all possible solutions

for reducing the PDN impedance is one of the main purposes of

this paper.

Another important parameter to evaluate the low impedance

PDN is the transfer impedance Z21 . This parameter can describehow large is the voltage perturbation induced from the transient

current excitation at port 1 to the other part of the PDN at port 2,

as shown in Fig. 2. Similarly, keepingZ21 as low as possible ina wide frequency range is helpful for reducing the PDN noise

propagation.

III. DECOUPLINGCAPACITORS

A. Power/Ground Planes

Planes for power and ground levels are commonly used for

the PDN in multilayer packages or PCBs. The static capaci-

tance formed between the power and ground planes provides

natural decoupling capacitors at low frequency. However, as

frequency increases, the planes structure becomes a parallel-plate waveguide with cavity resonances at resonant frequencies.

Theresonance effects will cause an increase of the self and trans-

fer impedance, which enhances the coupling of PDN noise.

Fig. 3 shows a typical example of the power/ground plane

structure for a package and PCB [63]. There is the ball grid

array (BGA) package of 2.7 cm 2.7 cm mounted on a testPCB of 10 cm 8 cm through 32 solder balls of 670 m di-ameter. The BGA package consists of four copper layers with

a total substrate thickness of 350 m. The inner two layers areground and power layers with 150 m spacing. A two layerPCB with substrate thickness 700m is the power and ground

planes on the PCB. The dielectric constant (DK) of the BGA

Fig. 4. Measured |S21 | for three different PDN combinations.

and PCB is 4.3. Fig. 4 shows the measured |S21 | for three dif-

ferent PDN combinations. The combinations are the packageonly, PCB only, and the PCB with package attached [63]. The

PDN of the package behaves as a pure capacitor for frequen-

cies up to 2 GHz, because the first cavity resonance occurs

above 2.8 GHz due to its small size. In this frequency range,

the noise coupling on the package significantly decreases as the

frequency is increased. For the PCB planes only, there are sev-

eral noise coupling peaks occurring at 0.76, 0.95, 1.22, 1.52,

and 1.79 GHz. These peaks correspond to the resonant cav-

ity modes TM10 , TM01 , TM11 , TM20 , and TM21 , respectively.Comparing these two cases, the PCB planes provide better noise

suppression below approximately 0.7 GHz than the package

planes only due to the larger parallel-plate capacitance.At higher frequencies, the PCB planes have higher noise

coupling than the package planes because of the larger resonant

cavity with lower resonance frequencies.

With the package mounted on the PCB, the noise coupling

seen on the package shows interactions between the package

and PCB. As shown in Fig. 4, the PDN behavior is derived

by the two shunted capacitors (CPC B =0.38 nF for PCB andCpk g =0.23 nF for package) at frequencies below 0.4GHz [63].At frequencies above 0.4 GHz, there are four peaks. The first

peak at 0.58 GHz could be explained as the parallel resonance

of the capacitance of the package and PCB, and the equivalent

inductance (Leff =0.48 nH) of the interconnection between the

package and PCB. The next three peaks in |S21 | are due to thecavity resonance coupling (or interaction) between the PCB and

the package. Because the power noise fed through the package

excites the resonant TM01 and TM11 modes inside the PCB, the

energy of the resonant modes is coupled to the BGA packages

through the solder balls and results in the second and third peaks,

respectively. The last peak in |S21 | at 1.45 GHz is due to thehigher order TM20 mode on the PCB cavity [7], [13].

Damping the resonant peak by reducing the Q-factor of thecavity is a way to reduce the noise coupling on the plane-typed

PDN. Using the conductive layer with inherent skin loss or

a magnetic material coating on the power/ground planes have

been shown to be effective in reducing the target impedance

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Fig. 5. Corresponding |S21 | for the combined PDN with and withoutcapacitors.

of the PDN near the resonant frequencies [64][66]. Because

the resonance results from the reflection at the power/ground

planes edge, another way to reduce the Q-factor of the cavity

is providing loss at the edge of the power/ground planes [67].The loss can be obtained by using the dissipated edge termina-

tion combining series R andC[68], whereCis for blockingdc, or by using absorbing material with large magnetic loss

at microwave frequencies [69]. Besides providing loss at the

board edge, it has been shown that the Q-factors can be reducedby putting coupled resistive terminations at suitable positions

of the PDN [70]. Another interesting way to reduce the PDN

impedance at the resonant frequencies is employing the effec-

tive series resistor (ESR) of the surface-mounted technology

(SMT) decoupling capacitors [71]. The optimum ESR (RN) forNuniformly distributed capacitors on the PCB board can bedecided by [72]

RN = N Qh

2r 0 A (2)

where A is the area of the power/ground planes, h is the substratethickness between power and ground planes, r is the relativepermittivity of the substrate, andQis the desired quality factor.In general,Q 1for a smooth impedance profile at those res-onant frequencies. It is effective only as the ESL impedance is

smaller than theRN.

B. SMT Capacitors

Adding ceramic SMT capacitors on a package or PCB is the

common way to reduce the PDN impedance. Because there isinevitable series ESL of the capacitor as they are mounted on the

substrate, the decoupling capacitor will become inductive andbe

short of providing the transient current to the switched IC. This

phenomenon can be seen for the aforementioned package and

PCB planes structures, shown in Fig. 3, with an additional eight

SMT capacitors of 100 nF mounted on the PCB. The locations

of the capacitors can refer to [63]. Fig. 5 shows the correspond-

ing |S21 | for the combined PDN with and without capacitors.The |S21 | for the case with decoupling capacitors is signifi-cantly decreased below approximately 200 MHz, because there

is a transfer impedance zero at approximately 23 MHz, which

results from the series resonance of the decoupling capacitors

and their ESL. However, in the frequency range between 200

and 500 MHz, the PDN with eight capacitors on the PCB has

a noise peak at approximately 400 MHz. The reason could be

the parallel resonance of the ESL of the decoupling capacitor

and the shunting capacitance of the PCB and package. Above

500 MHz, the noise coupling behavior is similar to the case

without SMT capacitors on the PCB. It implies that the SMT

capacitors are not able to provide the displacement current at

higher frequency due to the ESL.

Decreasing the connection inductance between the chip

power/ground pads to the decoupling capacitors, which include

the traces, pads, vias, and the ESL of the decoupling capacitor,

is important for enhancing their effective bandwidth. Several

approaches have been reported to reduce these inductances. The

intuitive way is putting the SMT capacitors as close as possible

to the chips with shorter power/ground traces [15]. It has been

proved that putting the capacitors on the package substrate has

a lower PDN impedance over a wider frequency range com-

pared to putting on the PCB due to a smaller length for the

power/ground interconnects [63]. The connection inductancecan be further reduced using a package technology called the

capacitor inside the substrate, which can put the discrete capac-

itor just beneath the chip with lower ESL [27]. Another way

to reduce the connection inductance is using multiple identical

capacitors in parallel [16], [19], [21]. The effective bandwidth

could be further enhanced by parallel capacitors with different

capacitor values, but the unwanted antiresonance occurred due

to the parallelLCresonance [16], [21]. It is associated with thecircuit that one capacitor has become inductive and the other

one is still capacitive. The antiresonance peaks can be reduced

by using the low-Q-controlled ESR decoupling capacitors or

using the annual embedded resistor on the package substrate toincrease the ESR of the decoupling capacitors [20].

For multilayer package or PCB, SMT capacitors are com-

monly connected to the power/ground planes. The space be-

tween the power and ground planes could affect the PDN noise

suppression capability for the SMT capacitors [17], [18], [22],

[26]. When the space is small as shown in Fig. 6(a), the small

loop area and wide power/ground conductors causes the con-

tribution of the planes to the overall connection inductance to

become negligible compared to the parasitic inductance of the

interconnects between the capacitor and the planes. The loca-

tions of the decoupling capacitors are not critical below the

SRF because their performance is dominated by the connection

inductance to the planes [15]. However, if the spaces betweenthe power and ground planes are not small, the local decou-

pling phenomenon by placing the capacitors very close to the

active device power/ground pin can be seen because the planes

inductance and the mutual inductance between the vias going

through the planes cannot be ignored [17], [18], [23]. As shown

in Fig. 6(b), the reduction of the transfer impedance between

two ports on the PDN can be derived as [22], [24], [27]

|Z21 | 20 log10

(1 k) + L3 /L2

1 + L3 /L2

(3)

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Fig. 6. Multilayer package or PCB, SMT capacitors are commonly connectedto the power/ground planes. (a) Small (30 mils).

where k is the mutual magnetic coupling coefficients betweenthe local decoupling capacitors and IC vias, L3 is the intercon-nection inductance above the planes, which is comprised of the

capacitor vias above the planes pair, the traces, and the ESL of

the capacitor, andL2 is the partial inductance of the capacitor

via between the power and ground planes. As shown in (3),two factors play an important role in reducing the PDN transfer

impedance, i.e., the ratio L3 /L2 and the coupling coefficientk. The decrease of the transfer impedance |Z21 | can be en-hanced by decreasing L3 /L2 and increasing k . It implies thatthe effective local decoupling may be achieved when the spaces

between the power and ground planes are large and the vias

are very close with strong magnetic coupling. It is worth not-

ing that the local decoupling effect is still valid at frequencies

above the SRF and is a broadband behavior. Fig. 7 shows a

simulated local decoupling example on a 10 12 inch two-layer PCB with a space between power and ground planes of

35 mil [21].

A SMT decoupling capacitor of 1F, an ESL of 0.5 nH, andan ESR of 0.3 , is movable with a distance ofs from port1. The transfer impedance Z21 is plotted in Fig. 7 with threedifferents(10, 100, and 800 mil) for frequencies below 1 GHz.The transfer impedance decrease is approximately frequency-

independent with about a 36 dB reduction compared to the

case ofs=100 and 800 mil.Another approach to reduce the target or transfer impedance

of a PDN is, employing the optimization method [24], [28]. A

generic algorithm has been used to optimize the locations and

the values of the SMT decoupling capacitors mounted on the

power/ground planes. An efficient core PDN simulator, such as

cavity model [24], [25] or the multiple layer finite-difference

Fig. 7. Transfer impedanceZ21 for a simulated local decoupling example ona 10 12 inch two-layer PCB with space between power and ground planesequal to 35 mil. [21].

method [34], is required to efficiently decide the optimum ca-

pacitor design.

C. Embedded Capacitors

Embedded capacitors areanother wayto enhance theeffective

bandwidth of the PDN [73][80]. They are broadly classified

into two categories. One is the planar embedded capacitor that

is fabricated on the whole power/ground planes pair with a very

thin dielectric substrate between the planes [77]. It can be in

package or on the PCB level. The other type is the discrete

embedded thick film (or thin film) capacitors [76]. These can be

embedded inside the package substrate and the capacitor size is

small because a very high DK material, say reaching 3000, could

be used. The PDN noise suppression performance for these twotypes of embedded capacitors is decided mainly by the thickness

and the DK of the dielectric layer. A thinner dielectric and

higher DK have a lower PDN impedance. Another advantage

of the embedded capacitor is lower ESL [78] compared to the

conventional SMT capacitors. Because the embedded capacitors

can be located just beneath the IC, only through hole (or buried)

vias are needed to connect the IC to the capacitor. The SRF of

the embedded capacitors can be shifted to higher frequencies

due to the decrease of the ESL. It has been reported that the

embedded capacitors can efficiently reduce the PDN noise in

the gigahertz range [75]. Although the fabrication cost of the

embedded capacitor is higher, it could partially replace the SMTcapacitors and saves package or PCB area.

IV. ISOLATIONUSINGSLOTS ORFILTER

Using isolation slots is a common way to suppress PDN

noise. A complete segmentation employing surrounding slots

on either the power or ground planes can achieve signifi-

cant PDN noise isolation, but it lacks a dc connection [13].

In some applications, keeping the same dc level between the

two sides of the slots is important. A narrow conducting trace

(called bridges) connecting two sides of the PDN could pro-

vide the good dc reference, but the isolation performance is

degraded in low-frequency range [13]. Fig. 8(a) shows a typical

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Fig. 8. (a) Typical four-layer PCB of 10 cm 8 cm. (b) Noise is coupled fromthe PDN at port 1 to the signal trace at port 2 through the via.

four-layer PCB of 10 cm 8 cm. The power and ground planesare on layer two and three with a space of 1 mm. There are

three terminated 50 transmission lines of 4 cm length withvia transition from the top to bottom layers at the center of the

line. As shown in Fig. 8(a), an isolation slot of 4 cm 4 cm

with a bridge of 4 mm width is designed both on the power andground planes. The noise coupled from the PDN at port 1 to

the signal trace at port 2 through the via is shown in Fig. 8(b).

The case of continuous power and ground planes without the

slots is also shown in Fig. 8(b) for comparison. 3-D finite-

difference time domain (FDTD) simulation is used to verify

the accuracy of the measurements. It is found that the isolation

slots could result in about 10 dB PDN coupled noise reduction

on average from 800 MHz to 3 GHz, except at the resonance

frequencies at 1.3 and 1.9 GHz. However, the noise coupling

is significantly enhanced at frequencies below 0.7 GHz due to

the isolation slot and the bridge. The coupling peak at about

400 MHz could be explained by the resonance on a longer path

formed by the isolated area and the bridge. The SI and EMIperformance will be significantly degraded if the signal crosses

the etched slots on the reference plane. Special care is generally

required.

Using a filter, consisting of one SMT ferrite bead in seriesand two SMT decoupling capacitors in parallel, to replace the

bridge on the isolation slots, is another approach to suppress

PDN noise [35]. It has been demonstrated that this method can

efficiently reduce the PDN noise from dc to high frequencies.

The dc connection between the two sides of the slot is achieved

by the ferrite bead, and the noise isolation can be enhanced by

the filter in the frequency range, where these SMTcomponents

are still effective.

Fig. 9. Two typical EBG structures. (a) Mushroom type. (b) Coplanar type.

The aforementioned isolation approaches have been widelyused in practical packages or PCB designs due to their sim-

plicity in implementation, but there are two drawbacks. One

is that they provide the local isolation. The isolation is ef-

fective only for the area surrounded by the slots. The cavity

resonance still occurs between the power and ground planes

and could degrade the isolation effectiveness. The other one is

that the isolation level (or insertion loss) is not very high be-

cause there is capacitive coupling between the two sides of the

slot at high frequencies. A high isolation level is required in a

highly integrated package or PCB system, especially, with RFI

issues.

V. EBG STRUCTURES

A. Models

EBG structures applied on the PDN could be one of the

possible solutions for the problems faced by the conventional

isolation approaches. The basic idea of an EBG PDN is cre-

ating a 2-D periodic structure on the whole or partial power

and/or ground planes. The inherent stopband within which the

parallel-plate modes cannot propagate will appear on the pe-

riodic structures. Ideally, the isolation level can approach in-

finity, as there are infinite number cells. However, in reality,

it has been shown that only a few cells can achieve high in-

sertion loss (over 30 dB) for well-designed EBG structures ona PDN.

Fig. 9(a) and (b) shows two typical EBG structures of mush-

room type and coplanar type, respectively [36][38], [40][43],

[45], [48], [49]. As shown in Fig. 9(a), the mushroom-shaped

unit cells are periodically embedded between the power and

ground planes. The pads between two planes are connected

to one of the planes through the vias. Three metal layers at

a minimum are required to implement this type of PDN. The

additional layer and the vias increase the fabrication cost. A se-

ries LCresonator formed between the power and ground planescould intuitively explain the mechanism of the PDN noise sup-

pression [36], [37]. The capacitor C is provided by the thin

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Fig. 10 One-dimensionalmodel for(a) mushroomtype, and(b) coplanar type.

substrate between the top layer and the pad on the second layer,

and the inductor is provided mainly by the long and thin via

connecting the pad and the bottom layer. As the PDN noise is

close to the resonance frequency of this series resonator, the

noise is shorted to ground and suppressed. The bandwidth of

the stopband will be broadened for cascading more unit cells.

Fig. 10(a) shows a 1-D equivalent circuit model for the unit

cell [56]. The parallel plate between the top and bottom lay-

ers is modeled by Lp3 and Cp4 . A parallel LC of Lv 1 andCp 3 describes the parallel plate between the pad (second layer)and the ground (bottom layer) and the shorting via. A-modelfor Lp1 , Cp2 , andCp1 describes the parallel plate between thepower layer (top layer) and the pad (second layer) with the mu-

tual inductive coupling Lp2 . This mutual coupling Lp2 is thesame with the self-inductance of the pad because they have the

same overlapping area with layer three under the assumption

of thin substrate layer. It is noted that Cp 1 = 2Cp2 because ofsymmetry. The lower side and upper side cutoff frequencies

(fL andfH) for the 1-D mushroom-type EBG can be derivedas [68]

fL = 12

2

2Cp1 (Lp1 + Lp3 + 2Lv 1 ) (4a)

fH = 1

4

2(((Lp 2 /Lv 1 ) + 4)

((Lp2 /Lv 1 )2 + 16))

Cp 3 Lp2.

(4b)

It has been shown that the 1-D model gives reasonable accuracy

for the cutoff frequencies prediction and is helpful for engineer-

ing design.

The coplanar EBG approach of designing periodic patterns

directly on the power or ground planes (hereafter assumed on

Fig. 11. Two-dimensional dispersion diagram for mushroom-type EBG.

the power plane) is shown in Fig. 9(b) [39], [43], [44]. The

pattern is built by periodic square patches that connect to their

adjacent patches by thin bridges. The bridge location could also

be designed close to the corner of the square pad like alternating

impedance EBG [39]. It does not require an additional metallayer and the vias for the coplanar EBG structure, but the power

plane is periodically etched by slots and will degrade the SI for

thesignal tracesreferredto such patternedplanes [44]. Basically,

the coplanar EBG structure behaves like a low-pass filter with

a large shunt capacitor Cand large series inductance L thatis provided by the patches and the bridges, respectively. The

1-D model for one unit cell is shown in Fig. 10(b). The bridge

inductance isLb . The square pad is modeled as two cascading-models, which are described by Lp1 , Cp1 , and Cp2 , whereCp1 = 2Cp2 . The lower side and upper side cutoff frequencies(fL andfH) for a 1-D coplanar EBG can be derived as [52],[56]

fL = 1

2

2

(Cp1 + 2Cp2 ) Lb(5a)

fH = 1

2

1

Cp2Lp1(5b)

which correspond to the cutoff frequency of the low-pass filter

and the first resonance frequency of the patches, respectively.

B. Dispersion Diagram for an EBG Structure

EBG structures applied in PDNs are commonly 2-D. Theaforementioned 1-D equivalent model and corresponding de-

rived cutoff frequencies are only an approximation, but they are

useful to understand the mechanism of the band rejection be-

havior. 2-D dispersion diagram calculated by full-wave methods

can provide the most rigorous stopband behavior. All modes are

solved for the unit cell with the boundary conditions satisfy-

ing the Bloch theory. The frequency ranges in which no modes

can propagate in any direction are considered as the stopband.

Fig. 11 shows the2-D dispersion diagram for themushroomwith

the same unit cell size of 20 mm. The via length, pad size, and

substrate thickness between top and second layers are 0.875, 15,

and 0.125 mm, respectively. The dispersions diagrams only for

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first two modes are simulated by a full-wave tool high-frequency

structure simulator. The stopband is marked in Fig. 11. The inset

of Fig. 11 shows the irreducible Brillouin zone for the square

unit cell. The dispersion curves are plotted along the phase vec-

tor ofXM [81]. The dispersion diagram for the planarEBG can be seen in [45].

C. Progress of EBG Structures Applied to PDN

Recently, two main research efforts are emphasized for EBG

structures applied to PDN noise suppression. One is stopband

bandwidth enhancement because of switching noise from digital

circuits covering a wide frequency band [36][38], [40][43],

[45], [48], [49]. The other is miniaturization techniques due to

the trend of system in package [45], [49], [50]. The progress of

these two research directions will be discussed for both types of

EBG structures, respectively.

An intuitive approach to broaden the stopband or reduce the

structure size of the mushroom EBG is increasing the capaci-

tance (C) between the pads on the second layer to the top planes.Using a thin-film high DK substrate between the top and second

layers can significantly increase the capacitance [42]. As shown

in (4a) and (4b), fLcanbe decreasedas theCis increased but fHis not changed too much. The main drawback of this approach

is high material and fabrication cost. Another way to enhance

the bandwidth is by cascading two or more EBG structures with

different unit cell periods that have different stopbands [40],

[45].

The different EBG configurations can be cascaded either hor-

izontally [40] or vertically [45]. The mushroom EBG structure

could be miniaturized by increasing the equivalent inductance

between second and the bottom layers, but the stopband band-width generally becomes narrower. It could also be understood

by (4a) and (4b) that fL andfHare both reduced as L is in-creased. The inductance can be increased by using a spiral via

between the second and bottom layers [37] and/or using spiral

pads on the second layer.

For coplanar EBG structures, the bandwidth enhancement or

the unit cell size reduction could be achieved by increasing the

bridge inductance (Lb ). As shown in (5a) and (5b), fL can bereduced by increasing Lb while fHis kept almost the same. Theinductance can be increased by using an L-shaped [43] or me-

ander bridge that has a longer length of the bridge [51]. Another

idea for increasing the bridge inductance is replacing the bridge

by a SMT lumped inductor [52], [53]. It could significantlyreduce fL by using a large lumped inductor with additionalcomponent cost. A ground surface perturbation lattice (GSPL)

embedded between thepower andgroundplanes hasbeen shown

to have a good effect on enlarge the stopband for the coplanar

L-bridged EBG structure [56]. Fig. 12 shows the top and side

views of the GSPL structure with the geometrical notations be-

ing denoted. Fig. 13 shows the measured noise insertion loss

(S21 ) for three different EBG structures, mushroom, L-bridged,and GSPL, applied on the same PDN with dimensions of

60 mm 60 mm. The unit cell size for these three EBGstructures is 20 mm 20 mm, and their detailed geometri-

cal dimensions are shown in Table II. It is clearly seen that the

Fig. 12. Top and side views of the GSPL structure with the geometricalnotations being denoted.

Fig. 13. Noise insertion loss (S21 ) for three different EBG structures: mush-room, L-bridged, and GSPL.

TABLE IIGEOMETRICALPARAMETER

stopband bandwidth is 0.42, 3, and 4.57 GHz, respectively. The

mushroom-shaped EBG has smallest bandwidth and the GSPL

has the widest one under the same fabrication limitation.

All aforementioned approaches design the periodic structureon the metal layers using etched slots. SI and EMI problem be-

low or above stopband could be caused for the high-speed sig-

nals traces passing through the discontinuous reference planes.

Another idea of creating a periodic structure on the dielectric

substrate has been shown effective in forming the stopband on

the PDN. A photonic crystal power layer that periodically em-

beds high DK rods between the power and ground planes, has

demonstrated good noise suppression performance [46], [57].

This approach keeps the power and ground planes continuous,

and will improve both the power and signal integrity behavior.

High fabrication and material costs are the challenges of this

technique.

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VI. CONCLUSION

Noise on PDNs of high-speed or mixed-signal circuits is one

of the main challenges for PI and EMC design. This paper

describes the fundamental concepts for PI design on a package

or PCB. The possible solutions for PI based on decoupling and

isolation concepts have been reviewed.

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Tzong-Lin Wu (S93M98SM04) received theB.S.E.E. and Ph.D. degrees from the National TaiwanUniversity (NTU), Taipei, Taiwan, in 1991 and 1995,respectively.

From 1995 to 1996, he was a Senior Engineerwith the Microelectronics Technology, Inc., Hsinchu,Taiwan. From 1996 to 1998, he joined the Cen-tral Research Institute, Tatung Company, Taipei,where he was involved with the analysis and mea-surement of electromagnetic compatibility (EMC)/electromagnetic interference (EMI) problems of

high-speed digital systems. From 1998 to 2005, he was with the Electrical En-gineering Department, National Sun Yat-sen University (NSYSU), Kaohsiung,Taiwan. He is currently a Professor with the Department of Electrical Engi-neering and Graduate Institute of Communication Engineering, NTU. He wasa Visiting Professor with the Electrical Engineering Department, University ofCalifornia at Los Angeles (UCLA), Los Angeles, CA, in the summer of 2008.Since 2006, he has been an Associate editor of the International Journal of

Electrical Engineering(IJEE). His current research interests include EMC/EMIand signal/power integrity design for high-speed digital/optical systems.

Dr. Wu was a recipient of the Excellent Research Award and the ExcellentAdvisor Award from NSYSU, in 2000 and 2003, respectively, the Outstand-ing Young Engineers Award from the Chinese Institute of Electrical Engineers(CIEE), in 2002, the Wu Ta-You Memorial Award from the National ScienceCouncil, in 2005, and the Technical Achievement Award from IEEE EMC So-

ciety, in 2009. He was the Treasurer of Taipei Section, IEEE, in 20072008, andthe Chair of the Taipei Section, Institute of Electronics, Information and Com-munication Engineers (IEICE) from 2007 to 2011. He was also engaged as theBoard of Directors of IEEE Taipei Section, in 20092010. He has been electedas a Distinguished Lecturer of IEEE EMC Society for the term of 2008 to 2009.He is the Cochair of 2007 IEEE Electrical Design of Advanced Packaging andSystems (EDAPS) workshop and the Chair of 2008 International workshop onEMC. He is a member of IEICE and CIEE.

Hao-Hsiang Chuang was born in Taipei, Taiwan,China, in 1985. He received the B.S. degree in elec-trical engineering from National Taiwan University,Taipei, in 2007, and is currently working toward thePh.D. degree with the Graduate Institute of Commu-nication Engineering, National Taiwan University.

His current research interests include the designof power distribution network of high-speed memoryI/O circuits.

Ting-Kuang Wang was born in Tainan, Taiwan,China, on December 27, 1980. He received theB.S.E.E. and M.S. degrees from National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2003 and2005, respectively. He is currently working towardthe Ph.D. degree with the Graduate Institute of Com-municationEngineering, National Taiwan University,Taipei, Taiwan.

His current research interests include power in-

tegrity design in high-speed packages and printedcircuit boards.

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