abstract interface. (under the direction of veena misra
TRANSCRIPT
ABSTRACT
HANEY, SARAH KAY. Investigation of Low Temperature, Atomic-Layer-Deposited Oxides on 4H-SiC and their Effect on the SiC/SiO2 Interface. (Under the direction of Veena Misra and Justin Schwartz).
Silicon carbide has long been considered an excellent substrate for high power, high
temperature applications. Fabrication of conventional MOSFETs on silicon carbide (SiC)
relies on thermal oxidation of the SiC for formation of the silicon dioxide (SiO2) gate oxide.
Historically, direct oxidation was viewed favorably due to ease of fabrication. However, the
resulting MOS devices have exhibited significant interface trap densities, Dit, which reduce
effective inversion layer mobility by capturing free carriers and enhancing scattering. While
nitridation has been shown to reduce Dit, the inversion layer electron mobility of these devices
is still limited by the presence of carbon near the interface. Studies have suggested a low
mobility transition region between the SiC and SiO2, on the SiC side, attributed to increased
carbon concentration resulting from the thermal oxidation of the SiC. In this work, we have
investigated the low temperature, atomic layer deposition (ALD) of SiO2 onto SiC compared
to thermal oxidation of SiC for the fabrication of MOS devices. Avoiding the carbon out
diffusion and subsequent carbon build-up resulting from thermal oxidation is expected to
result in a superior, higher mobility MOSFET.
A three-step ALD process using 3-aminopropyltriethoxysiliane (3-APTES), ozone and
water was evaluated on silicon and SiC substrates. Ellipsometry and XPS were used to
characterize blanket films, and showed good results. Capacitors fabricated on SiC showed the
need for optimized post deposition anneals. The effect of post oxidation anneals in nitrogen,
forming gas and nitric oxide were examined. The standard nitric oxide (NO) anneal that is
used to improve Dit after thermal oxidation was also shown to be the best anneal for the low
temperature deposited ALD oxides.
Materials characterization of the nitrided ALD and nitrided thermal oxide samples was
completed using STEM/EELS techniques in addition to the ellipsometry and XPS.
STEM/EELS analysis of the samples revealed no significant difference in transition regions
on either side of the SiC/SiO2 interface regardless of oxidation technique or anneal
temperature or ambient. All samples analyzed exhibited approximately 2-3nm of transition
region on either side of the interface with no evidence of carbon or silicon rich regions. XPS
was also used to determine a valence band offset of 2.43eV for the ALD oxide on 4H-SiC.
Lateral MOSFETs were fabricated on 4H-SiC substrates with the following oxidation
treatments: thermal oxidation at 1175°C, thermal oxidation at 1175°C followed by a nitric
oxide (NO) anneal at 1175°C, and ALD of SiC at 150°C followed by an NO post oxidation
anneal (POA) at 1175°C. ALD of the SiO2 was performed using 3-aminopropyltriethoxysiliane
(3-APTES), ozone and water. Field effect mobility values were comparable for these samples,
suggesting common thermal oxidation steps were still limiting the mobility. As such additional
lateral MOSFETs were fabricated without the incoming sacrificial oxidation steps. This
sacrificial-oxidation free experiment showed a 15% improvement in peak field effect mobility
for the nitrided ALD oxide samples as compared to the nitrided thermal oxides. SIMS of the
interfaces revealed nitrogen concentrations of ~6E21 at/cc in the nitrided ALD sample
compared to ~4-6E20 in the nitrided thermal sample. This extremely high level of nitrogen
incorporation, which is unparalleled in NO annealed thermal oxides, is accountable for the
increase in field effect mobility. The low deposition temperature of the ALD oxide causes
high levels of carbon incorporation and greater number of dangling bonds at the interface.
Both the dangling bonds and excess carbon acts as binding sites for the nitrogen, increasing
the nitrogen concentration and resulting in higher mobilities.
Results presented support the use of SiO2 deposited using low temperature atomic
layer deposition for improved gate oxides on 4H-SiC MOSFETs given the opportunity for
increased nitrogen incorporation. The elevated levels of nitrogen measured in the NO
annealed ALD SiO2 sample are unique and are directly attributed to the low temperature ALD
process. As such, high peak field effect mobilities can repeatably be achieved with optimization
of the nitrided ALD process.
Investigation of Low Temperature, Atomic-Layer-Deposited Oxides on 4H-SiC and their Effect on the SiC/SiO2 Interface
by Sarah Kay Haney
A dissertation submitted to the Graduate Faculty of North Carolina State University
in partial fulfillment of the requirements for the Degree of
Doctor of Philosophy
Materials Science and Engineering
Raleigh, North Carolina
2012
APPROVED BY : ___________________________________
Dr. Justin Schwartz
___________________________________
Dr. Alan D. Batchelor
__________________________________
Dr. Veena Misra ___________________________________
Dr. Daniel Lichtenwalner ___________________________________
Dr. Anant Agarwal
ii
DEDICATION
This thesis is dedicated to my best friend
and husband Sean, to our son Finn and to
my parents. The continual encouragement
and support that I received from all of you
made this work possible. Thank you.
iii
BIOGRAPHY
Sarah Kay Haney was born and raised in Pittsburgh, Pennsylvania. After beginning her
undergraduate studies at Case Western Reserve University, she transferred and graduated from
the University of Pittsburgh with a bachelor’s degree in Materials Science and Engineering in
2003. After completion of her degree Sarah accepted a position with Olympus Industrial and
moved to North Carolina. After marrying her husband Sean in the fall of 2004, Sarah accepted
a position at Cree, Inc. working with SiC power devices. Enjoying her work at Cree, Sarah
decided to begin her graduate studies while continuing to work full-time. Sarah completed her
masters in Materials Science and Engineering at NCSU in 2008, with a concentration in
Electrical Engineering will conclude her Ph.D. studies in fall 2012. Her current research
focuses on enhancing electron mobility at silicon carbide and silicon dioxide interfaces for SiC
MOS devices. If not working or studying, Sarah is enjoying life with her husband Sean and
son, Finn. Sarah is very active in the IEEE Eastern North Carolina Section, serving as section
secretary for 2012.
iv
ACKNOWLEDGMENTS
I wish to express sincere appreciation to everyone at the university and those on my
committee who have helped me during my graduate studies. First and foremost, to Dr. Anant
Agarwal, who encouraged me to pursue this degree and supported my research for the past 7
years. The support of Dr. Veena Misra, who welcomed me into her group and assumed
direction of my research when I was advisor-less was also essential. I am also very grateful to
Dr. Justin Schwartz for jumping on board and supporting my work as MSE Co-chair when I
feared all was lost. I would also like to recognize Dr. Daniel Lichtenwalner, for always asking
good questions and pushing me to question my work, and Dr. Dale Batchelor for being an
excellent resource for FIB, TEM sample preparation and characterization questions. Edna
Deas also deserves special thanks for being the most organized, caring and helpful person at
North Carolina State University.
I am also indebted to my coworkers, past and present, who supported me in this endeavor.
Notably Dr. Sarit Dhar, from whom I learned so much about the SiO2/SiC interface and Jeff
Whitt, for help with processing all of my tiny pieces in the fab. I am also forever grateful to Dr.
John Palmour, and everyone else at Cree who understands the importance of pursuing
graduate degrees.
I would like to thank Dr. Juan Carlos Idrobo and Dr. Gerd Duscher from Oak Ridge National
Labs for their guidance and assistance with the STEM/EELS data that I have amassed
throughout this research. I would also like to thank the ORNL Center for Nanophase
Materials Sciences for their support of my work through research grants.
Finally, of course, I never would have made it through all of this without my family and
friends. I would like to thank Dr. Ginger Wheeler for making so many classes, homework
assignments and study sessions both rewarding and fun. Lastly, thank you to my husband, son
and parents who have taken so much time out of their own lives to give me time to work.
Without the four of you, this would never have been possible.
v
TABLE OF CONTENTS
LIST OF TABLES ............................................................................................ ix LIST OF FIGURES .......................................................................................... x CHAPTER 1: INTRODUCTION AND OVERVIEW ................................... 1
1.1 Research Motivation .............................................................................. 1 1.2 Dissertation Structure ............................................................................ 3 1.3 References .............................................................................................. 5
CHAPTER 2: BACKGROUND ....................................................................... 7
2.1 Silicon Carbide ....................................................................................... 7 2.1.1 Crystal Structure ............................................................................. 7 2.1.2 Semiconductor Properties of SiC .................................................. 9 2.2 Interface of SiC and SiO2 .................................................................... 10 2.2.1 Oxidation of SiC .......................................................................... 10 2.2.2 Problems at the Interface of SiC and SiO 2 .................................. 11 2.2.3 Interface Passivation .................................................................... 14 2.3 SiC MOSFETs ..................................................................................... 16 2.3.1 MOSFET Operation .................................................................... 17 2.3.2 MOSFET Characteristics ............................................................. 19 2.3.3 Oxide and Interface Charge ......................................................... 22 2.3.4 Non-Ideal Charge Effect on I-V Characteristics ........................ 23 2.3.5 Non-Ideal Charge Effect on C-V Characteristics ....................... 25 2.4 Summary ............................................................................................... 26 2.5 References ............................................................................................ 27
CHAPTER 3: RESEARCH METHODOLOGY ........................................... 32
3.1 Atomic Layer Deposition .................................................................... 32 3.2 Materials Characterization Techniques ............................................... 37
3.2.1 Ellipsometry .................................................................................. 37 3.2.2 X-Ray Photoelectron Spectroscopy ............................................. 38 3.2.3 Scanning Transmission Electron Microscopy ............................. 39 3.2.4 Electron Energy-Loss Spectroscopy ............................................ 42 3.2.5 Secondary Ion Mass Spectrometry ............................................... 45
3.3 Electrical Characterization Techniques .............................................. 45 3.3.1 Capacitance – Voltage Measurement ........................................... 45 3.3.2 Current - Voltage Measurements ................................................. 48 3.3.3 Interface Trap Density Measurement .......................................... 49
3.4 Electrical Modeling .............................................................................. 52 3.4.1 Capacitors ..................................................................................... 53 3.4.2 MOSFETs ..................................................................................... 54
vi
3.5 SiC Sample Fabrication ....................................................................... 55 3.5.1 Capacitors ..................................................................................... 55 3.5.2 Lateral MOSFET structures ........................................................ 55
3.6 STEM Lamella Fabrication .................................................................. 57 3.6.1 Focused Ion Beam Milling ........................................................... 57 3.6.2 Lamella Preparation .................................................................... 57
3.7 References ............................................................................................ 61 CHAPTER 4: ALD OF SIO2 RESULTS AND DISCUSSION ..................... 63
4.1 Development of ALD Process ............................................................ 63 4.2 Capacitor Results on Silicon ............................................................... 70 4.2.1 Ellipsometry ................................................................................. 70 4.2.2 C-V ................................................................................................ 71 4.3 Conclusions .......................................................................................... 72 4.4 References ............................................................................................ 73
CHAPTER 5: CAPACITORS ON SIC RESULTS AND DISCUSSION ..... 74 5.1 Optimization of the Process on SiC ................................................... 74
5.1.1 Effect of Pre-deposition Surface Cleans ..................................... 74 5.1.2 Effect of Post-deposition Forming Gas Anneal ......................... 76 5.1.3 Effect of Post-deposition Nitric Oxide Anneal .......................... 78 5.1.4 Electrical Modeling ...................................................................... 81
5.2 Materials Characterization of the ALD SiO 2/SiC Interface .............. 82 5.2.1 XPS Results .................................................................................. 82 5.2.2 STEM/EELS Results ................................................................... 88
5.3 Conclusions .......................................................................................... 90 5.4 References ............................................................................................ 92
CHAPTER 6: STEM/EELS INVESTIGATIONS OF THE SIC/SIO2 INTERFACE ................................................................................................... 93
6.1 Investigation of Miscut Effects on Nitrided Thermal Oxides ........... 95 6.1.1 Materials Characterization of Nitrided Thermal Oxide on 2
Degree Offcut Material ......................................................................... 95 6.1.2 Materials Characterization of Nitrided Thermal Oxide on 4
Degree Offcut Material ......................................................................... 96 6.1.3 Materials Characterization of Nitrided Thermal Oxide on 8
Degree Offcut Material ......................................................................... 98 6.2 Investigation of Miscut Effects on Nitrided ALD Oxides .............. 102 6.2.1 Materials Characterization of Nitrided ALD Oxide on 4 Degree
Offcut Material .................................................................................... 103 6.2.2 Materials Characterization of Nitrided ALD Oxide on 8 Degree
Offcut Material .................................................................................... 105 6.3 Sacrificial Oxidation-Free MOSFET Comparison ........................... 110
vii
6.4 Conclusions ........................................................................................ 116 6.5 References .......................................................................................... 117
CHAPTER 7: MOSFETS ON SIC RESULTS AND DISCUSSION .......... 118
7.1 Sacrificial Oxidation-Free MOSFET Comparison ........................... 118 7.1.1 Electrical Characterization ......................................................... 119 7.1.2 Electrical Modeling .................................................................... 120 7.2 Experimental Verification ................................................................. 121 7.2.1 Electrical Characterization ......................................................... 121 7.2.2 Electrical Modeling .................................................................... 122 7.3 Role of the Nitric Oxide Anneal ...................................................... 123 7.4 Conclusions ........................................................................................ 129 7.5 References .......................................................................................... 130
CHAPTER 8: CONCLUSION ..................................................................... 131
8.1 Description of Findings..................................................................... 131 8.2 Future Work ....................................................................................... 133 8.3 References .......................................................................................... 135
APPENDICES............................................................................................... 136
Appendix A: EELS Quantification Methods .......................................... 137 Appendix B: Energy band Alignment of ALD SiO2 on SiC................... 143
Appendix C: Modeling Options and Materials Files .............................. 152
viii
LIST OF TABLES
Number Page Table 1.1 Physical property comparison of Si and 4H-SiC ........................ 1
Table 1.2 Comparisons of SiC MOSFET experimental mobility and Dit
to SiC theoretical and silicon results ..................................................... 2
Table 2.1 Material properties of some common SiC polytypes ................. 9
Table 2.2 Material properties comparisons of common semiconductors
for power electronic devices ................................................................ 10
Table 3.1 Processing parameters for high temperature oxidation recipes56
Table 4.1 Process parameters for SiO2 ALD recipe ................................. 64
Table 4.2 Ellipsometry data for different surface cleans for ALD SiO 2
on silicon .............................................................................................. 70
Table 5.1 Ellipsometry data for different surface cleans for ALD SiO 2
on SiC ................................................................................................... 75
Table 5.2 Extracted parameters from capacitance-voltage modeling ...... 82
Table 6.1 Comparison of SiC side transition region thickness, SiO 2 side
thickness and lateral MOSFET field effect mobility for the three
nitrided thermal oxide samples studied ............................................. 102
Table 6.2 Comparison of SiC side transition region thickness, SiO2 side
thickness and lateral MOSFET field effect mobility for the nitrided
ALD oxide samples studied ............................................................... 108
Table 6.3 Comparison of SiC side transition region thickness, SiO 2 side
thickness and lateral MOSFET field effect mobility for the four
process splits investigated with the sacrificial oxidation-free
process ................................................................................................ 115
Table 7.1 Comparison of Hauser Mob2d model results for both
sacrificial oxidation-free experiments. .............................................. 123
ix
Table 7.2 Ellipsometry data for ALD oxides before and after Nitric
Oxide annealing. ................................................................................ 126
x
LIST OF FIGURES
Number Page Figure 2.1 Illustration of a SiC tetrahedron ............................................... 8
Figure 2.2 Site locations for close packed hexagonal planes ..................... 8
Figure 2.3 Stacking sequence of 4H, 6H, 15R and 3C silicon carbide in
the [1120] plane ...................................................................................... 8
Figure 2.4 Depiction of the charge balance in a SiC MOS system with
interface traps illustrated ..................................................................... 12
Figure 2.5 Depiction of the assumed distribution of interface states at
the SiC/SiO2 interface for 4H-SiC, 6H-SiC and 15R-SiC .................. 13
Figure 2.6 Depiction of the charge balance in a SiC MOS system with
both interface and bulk traps .............................................................. 14
Figure 2.7 4H-SiC interface trap densities near the conduction band for
varying post oxidation anneal ambients .............................................. 15
Figure 2.8 Schematic of a SiC metal-oxide-semiconductor capacitor ..... 15
Figure 2.9 Band offsets for 4H-SiC MOSFETs........................................ 16
Figure 2.10 Schematic of a 4 terminal p-type, n-channel MOSFET ....... 17
Figure 2.11 Band diagrams showing the 4 modes of operation for an n-
channel MOSFET (a) Equilibrium or Flat band (b) Accumulation
(c) Depletion and (d) Inversion ........................................................... 18
Figure 2.12 Schematic of a 4 terminal p-type MOSFET showing (a) the
depletion region and (b) the inversion layer and depletion regions .. 19
Figure 2.13 Typical MOSFET family of curves showing I d-Vds behavior
for varying gate voltages ...................................................................... 20
Figure 2.14 Typical p-type MOS capacitor high frequency and low
frequency C-V curves showing the three regions of operation ......... 20
Figure 2.15 The four types of charges, labeled by color, in the MOS
system .................................................................................................. 22
xi
Figure 2.16 Illustration of injection and tunneling mechanisms that can
cause leakage in MOSFETs ................................................................. 25
Figure 3.1 Schematic of a four step ALD sequence resulting in one
complete reaction cycle ........................................................................ 33
Figure 3.2 The ALD process window as related to growth rate versus
temperature .......................................................................................... 34
Figure 3.3 Thickness plotted as a function of flow direction for varying
precursor doses and process conditions ............................................. 35
Figure 3.4 STEM images. Left: Bright field (BF) image. Right: High
angle annular dark field (HAADF) image. The left side of both
images is SiO2 with crystalline SiC on the right side .......................... 41
Figure 3.5 Schematic of a dedicated STEM showing various detectors .. 41
Figure 3.6 Schematic of an EELS spectrometer and HAADF detector
in a STEM ............................................................................................ 43
Figure 3.7 Example spectra of a SiC sample. Peaks include silicon (100
eV), carbon (284.5 eV) and oxygen (532 eV) ...................................... 44
Figure 3.8 Examples of the effect of charges on C-V curves a) C-V
curve with no charge(a), injected charge (b) and mobile charge (c),
b) shift in C-V curves caused by injected charges, c) shift in C-V
curve due to mobile charges ................................................................ 47
Figure 3.9 Sample capacitance-voltage curves from a p-type capacitor.
Both the low frequency and high frequency curves are shown to
highlight the different behavior in the strong inversion region ... 50
Figure 3.10 High frequency capacitance measurements taken as part of
the Gray-Brown method. ..................................................................... 51
Figure 3.11 Dit values as determined using the Gray-Brown method .... 52
Figure 3.12 Experimental and modeled data for an n-type capacitor .... 53
Figure 3.13 Experimental data for nitrided thermal oxide compared to
calculated data and data modeled with varying interface state densities. Left:
xii
Across all measured gate voltages Right: Low voltage region used to obtain
the most accurate fit................................................................................. 54
Figure 3.14 Cross-section of typical lateral MOSFET used for this
research ............................................................................................... 55
Figure 3.15 Left: sample die showing the device patterns. Right: 5x
microscopic view showing circular FETs as well as the gated lateral
MOSFET used for this research .......................................................... 56
Figure 3.16 View of the TEM lamella preparation before lifting out of
the lateral MOSFET sample ................................................................ 58
Figure 3.17 The states of TEM lamella preparation using the FIB a)
pre-polish lamella attached to grid, b-c) polished lamella, and d) top
down view of lamella ........................................................................... 59
Figure 4.1 Proposed 3 step sequence for atomic layer deposi tion of
SiO2 using water, ozone and 3-APTES ............................................... 63
Figure 4.2 Plot illustrating the 30 pulse ozone line purge sequence ....... 64
Figure 4.3 Plot illustrating the beginning of a standard SiO 2 deposition
run. The initial 30 pulses of ozone are shown, followed by the 3 -
APTES, water and ozone pulse sequences.......................................... 65
Figure 4.4 Measured “as deposited” ALD SiO2 thickness variation
across half of a 3” wafer. ..................................................................... 66
Figure 4.5 Variation in refractive index for the “as deposited” ALD
SiO2 ....................................................................................................... 66
Figure 4.6 Plot of ψ as a function of wavelength for ALD SiO2 deposited on
silicon ..................................................................................................... 67
Figure 4.7 Plot of Δ as a function of wavelength for ALD SiO2 deposited on
silicon .................................................................................................... 67
Figure 4.8 Summary spectrum for “as deposited” ALD SiO 2 with Si 2p,
O 1s and C 1s peaks reviewed ............................................................. 68
xiii
Figure 4.9 O 1s (left) and Si 2p (right) spectrum for as deposited ALD
SiO2 with peak fitting ........................................................................... 69
Figure 4.10 Normalized capacitance-voltage measurements comparing
pre-deposition cleans for ALD SiO2 deposited on silicon ................. 71
Figure 5.1 Relative activation energies for –OH removal from silicon surfaces,
Si-face SiC surfaces and C-face SiC surfaces. .............................................. 74
Figure 5.2 Plots of ψ and Δ for the BOE and HF cleans. BOE data is shown in
a) and c), while HF data is presented in b) and d). ...................................... 76
Figure 5.3 Capacitance-voltage measurements for ALD SiO2 capacitors on SiC
after varying forming gas anneals .............................................................. 77
Figure 5.4 Normalized capacitance-voltage measurements comparing ALD
SiO2 with varied NO anneal temperatures to ALD with 600˚C N2 post
deposition anneal..................................................................................... 78
Figure 5.5 Normalized capacitance-voltage measurements comparing various
anneal treatments for ALD and thermal oxides. ......................................... 79
Figure 5.6 Density of interface traps (calculated from hilo CV) as a function of
trap energy distance from the conduction band for NO annealed ALD SiO2
and thermal oxides with and without NO anneal........................................ 80
Figure 5.7 Breakdown of an NO annealed ALD SiO2 compared to nitrided
thermal oxide on 4H-SiC ......................................................................... 81
Figure 5.8 Survey spectrum of NO annealed ALD SiO2 on SiC. N 1s peak is
indicative of nitrogen bonding .................................................................. 84
Figure 5.9 Silicon 2p spectrum and peak fitting for unannealed ALD SiO2 ....... 85
Figure 5.10 Oxygen 1s spectrum and peak fitting for unannealed ALD SiO2 .... 86
Figure 5.11 Carbon 1s spectrum and peak fitting for unannealed ALD SiO2 .... 87
Figure 5.12 Bright field (left) and HAADF (right) images of an NO anneal
ALD SiO2 on 4H-SiC .............................................................................. 88
xiv
Figure 5.13 Relative composition across the SiC/SiO2 interface determined
through EELS and the corresponding Z-contrast image showing the sample
area ........................................................................................................ 89
Figure 5.14 Relative composition across the SiC/SiO2 interface determined
through EELS, the corresponding BF image and intensity profile of the
image ..................................................................................................... 90
Figure 6.1 Offcut angles of 2,4, and 8 degrees illustrated using STEM HAADF
images and Si-C tetrahedrons ................................................................... 93
Figure 6.2 Field effect mobility versus field for the varying offcut nitrided
thermal oxidation samples measured with Vd = 50mV ................................ 94
Figure 6.3 STEM Images of the 2 degree offcut thermal + NO anneal sample
left: HAADF image, right: BF image ......................................................... 93
Figure 6.4 EELS quantification plots and bright field image of the 2 degree
offcut thermal oxidation + NO anneal sample ........................................... 95
Figure 6.5 HAADF image for the 4 degree offcut sample ............................... 97
Figure 6.6 EELS quantification plots and HAADF image for the 4 degree
offcut sample .......................................................................................... 98
Figure 6.7 HAADF image for the 8 degree thermal oxidation sample .............. 99
Figure 6.8 EELS plots, HAADF image and image intensity profile for the 8
degree offcut thermal + NO sample ....................................................... 100
Figure 6.9 EELS quantification plots showing silicon, carbon and oxygen
composition, the HAADF image and the image intensity profile for the 8
degree thermal + NO sample. ................................................................ 101
Figure 6.10 Field effect mobility versus field for the 4 and 8 degree offcut
nitrided thermal oxidation and nitride ALD oxide samples measured with Vd
= 50mV ................................................................................................ 103
Figure 6.11 STEM HAADF image for the 4 degree nitrided ALD sample ..... 104
Figure 6.12 Relative composition from EELS and HAADF image for the 4
degree ALD + NO anneal sample .......................................................... 105
xv
Figure 6.13 HAADF (left) and LAADF (right) images of the 8 degree ALD +
NO anneal lateral MOSFET sample ....................................................... 106
Figure 6.14 Relative Composition, HAADF image and Intensity profile for the
8 degree ALD + NO anneal sample ........................................................ 107
Figure 6.15 Additional Relative Composition, HAADF image and Intensity
profile for another 8 degree ALD + NO sample shows repeatable EELS
results ................................................................................................... 108
Figure 6.16 Capacitance-voltage measurements of the four process splits from
the sacrificial oxidation-free experiment .................................................. 110
Figure 6.17 Plot field effect mobility (calculated from transconductance and
measured with a drain voltage of 50 mV) of the four process splits from the
sacrificial oxidation-free experiment ........................................................ 111
Figure 6.18 Relative composition from STEM/EELS and HAADF STEM
image from the sacrificial oxidation-free, unanneal thermal oxide process
sample .................................................................................................. 112
Figure 6.19 Relative composition from STEM/EELS and HAADF STEM
image from the sacrificial oxidation-free, nitrided thermal oxide process
sample .................................................................................................. 113
Figure 6.20 Relative composition from STEM/EELS and HAADF STEM
image from the sacrificial oxidation-free, nitrided ALD oxide process
sample .................................................................................................. 113
Figure 6.21 Relative composition from STEM/EELS and HAADF STEM
image from the sacrificial oxidation-free, low temperature annealed, ALD
oxide process sample ............................................................................. 114
Figure 7.1 Capacitance-voltage measurements of the four process splits from
the sacrificial oxidation-free experiment .................................................. 118
Figure 7.2 Plots of Id-Vg (top) and field effect mobility (calculated from
transconductance) of the four process splits from the sacrificial oxidation-
free experiment ..................................................................................... 119
xvi
Figure 7.3 Experimental data for nitrided ALD oxide compared to calculated
data and data modeled with varying interface state densities ...................... 120
Figure 7.4 Field effect mobility as a function of gate voltage for the nitrided
thermal and ALD oxides from both sacrificial oxidation-free experiments . 122
Figure 7.5 SIMS nitrogen concentration profiles for the nitrided thermal and
nitrided ALD samples from sacrificial oxidation-free experiments 1 and 2 . 124
Figure 7.6 SIMS nitrogen concentration profiles for blanket ALD oxides
annealed in NO at 950 °C for 30 and 120 minutes ................................... 125
Figure 7.7 Curves of the relationship between mobility and onset of conduction
for nitrided thermal oxides on 4H-SiC. Peak mobility data from this work is
included ................................................................................................ 128
Figure A.1 Example of signal, background and edge set up for quantification 138
Figure A.2 Digital Micrograph quantification output graphs as a function of
scan distance. Top: Extracted core-loss signal. Middle: Areal Density.
Bottom: Relative composition ................................................................ 139
Figure A.3 Relative composition plot with high scan resolution provides more
data at the interface................................................................................ 142
Figure B.1 XPS C 1s spectra for a thin (2.5 nm) ALD SiO2 on SiC sample and
bulk SiC sample showing good peak alignment ........................................ 144
Figure B.2 XPS O 1s spectra for a thick (16.8 nm) ALD SiO2 and thin (2.5 nm)
ALD SiO2 on SiC sample showing good peak alignment .......................... 145
Figure B.3 XPS valence band spectra for a thick (16.8 nm) ALD SiO2 and a
bulk SiC sample. The VBM was determined to be 3.39 eV for the SiO2 and
0.96 eV for the 4H-SiC .......................................................................... 146
Figure B.4 a) Deconvolved energy loss spectra for 4H-SiC showing a bandgap
onset at 3.1 eV b) Published band structure for 4H-SiC showing a bandgap
of 3.23 eV ............................................................................................. 147
Figure B.5 Deconvolved energy loss spectra for 4H-SiC showing a bandgap
onset at 9 eV ......................................................................................... 148
xvii
Figure B.6 Energy band diagram for p-type polysilicon on 16.8nm of ALD
SiO2 deposited on n-type 4H-SiC ............................................................ 149
Figure B.7 Energy band diagram for a capacitor fabricated with p-type
polysilicon on 16.8nm of ALD SiO2 deposited on n-type 4H-SiC shown
biased into accumulation at 12 V ............................................................ 150
1
C H A P T E R 1
INTRODUCTION AND OVERVIEW
1.1 Research Motivat ion
Silicon carbide (SiC) MOSFETs have been a long-time goal of SiC research. SiC
MOSFETs provide many advantages over traditional silicon (Si) MOSFETs for high
temperature, high power applications. The wide bandgap and high thermal conductivity of
SiC allow for device operation at high junction temperatures making it particularly suitable
for high temperature applications. Simultaneously, the high critical breakdown field
provides advantages over Si for both device specific on-resistance and OFF state blocking
for high power applications. These benefits are clearly shown in Table 1.1, which
summarizes a few comparisons of Si and 4H-SiC.1,2,3,4
Table 1.1 Physical Property Comparisons of Si and 4H-SiC
Si 4H-SiC
Bandgap (eV) 1.1 3.26
Electron Mobility (at 300K) (cm2/V·s) 1350 950
Critical Breakdown Field (MV/cm) 0.3 2.0
Thermal Conductivity (W/K·cm) 1.5 4.5
However, there are still roadblocks to SiC MOSFET development. A significant
hurdle associated with SiC MOSFET development is poor channel mobility, compared to
theoretical. While the natural tendency of SiC to oxidize to silicon dioxide (SiO2) has been
viewed as a benefit of SiC, the low observed mobility is generally attributed to the SiC/SiO2
interface. Oxidation of the SiC leads to a high density of interface traps, Dit, at the SiC/SiO2
2
interface, associated with excess carbon from the oxidation process. The high Dit causes
increased Coulombic scattering which reduces mobility. Additionally before an inversion
layer can form, the free electrons must fill all of the interface traps. This further decreases
the mobile charge available for conduction. Starting in 1997, anneals in nitric oxide (NO)
were shown to reduce the Dit by an order of magnitude.5 Continued studies also revealed a
significant increase field effect mobilites from <5 cm2/Vs to 30 cm2/Vs.6 Additional
methods of getting nitrogen to the interface have been investigated and have shown similar
results with lower Dit and higher field effect mobilities (μFE).7,8,9 In addition to the use of
nitrogen to passivate the interface, oxidation in the presence of sodium has also been
shown to lower Dit and enhance μFE as compared to oxides grown through dry oxidation
techniques.10 These comparisons can be seen below in Table 1.2 which illustrates the
experimental results from various oxidation techniques compared to theoretical SiC and Si
limits.4,7,10,11,12,13,14
Table 1.2 Comparisons of SiC MOSFET experimental mobility and Dit to SiC
theoretical and silicon results.
μFE @ 300K
(cm2/Vs)
μHALL @ 300K
(cm2/Vs)
Dit(eV-1cm-2) @ 0.2eV from Ec
Thermal - Dry ≈ 5 ≈ 40 2 x 1013
Nitric Oxide
Anneal
≈ 35 ≈ 60 - 110 1 x 1012
Sodium Enhanced ≈ 100 - 175 ≈ 65 – 200 @225K 1 x 1012
SiC Theoretical ≈ 850 ≈ 1011
Silicon ≈ 500 ≈ 1000 ≈ 1010
3
This data indicates that even though Dit is lowering, the mobility does not evenly
scale with this Dit reduction. An additional factor, which does not have a clear relationship
to the Dit, may be causing mobility degradation. Two main ideas have been put forth to
explain the mobility problems. First, that surface roughness at the interface is the mobility
limiting factor.12 Second, that there is a lower mobility transition region on the SiC side of
the SiO2 and SiC interface. This second claim is related to the bulk trap theory which
postulates the existence of traps in the bulk on either side of the interface which effect μFE
in the same manner as interface traps.15 The development and composition of this
transition region and its relationship to μFE and Dit is not completely understood but is
critical to improving SiC MOS structures.
The use of low temperature oxide deposition methods to improve MOSFET
performance has not been extensively studied. The use of low temperature deposition has
centered around PECVD oxides which show no benefit compared to thermally oxidized
samples while introducing other problems associated with plasma damage.16,17,18,19,20 Other
deposition techniques have not been thoroughly reviewed. Atomic layer deposition (ALD)
is an attractive technique for investigation as it allows for low temperature deposition while
avoiding damage associated with plasma dependent techniques. ALD also provides
additional benefits including high conformality of deposited films even at high aspect ratios
and thickness uniformity across wafer. Further characterization of the transition region and
its relationship to μFE and Dit without the defects associated with thermal oxidation, is an
additional benefit to investigating ALD as a low temperature gate oxide process.
1 .2 Disserta t ion Structure
The structure of this dissertation is designed to provide a straightforward narrative
for those interested in the complete work while also allowing for effortless review of a
specific section of interest. Chapter 1 serves as an introduction to the research material and
discusses the motivation for the research. Chapters 2 and 3 provide the reader with
4
background information on the SiC/SiO2materials system, MOSFETs and the analytical
methods used to complete the research. Chapter 4 discusses the development of the SiO2
ALD process and initial results on silicon, with Chapter 5 reviewing capacitor work on
silicon carbide. Chapter 6 reviews material characterization results of the transition region
of lateral MOSFETs fabricated with ALD SiO2 on SiC compared to thermally oxidized
samples. Chapter 7 reviews the electrical characterization results of these lateral MOSFETs
fabricated with ALD SiO2 on SiC. Modeling results for lateral MOSFETs are also included
in Chapter 7. Chapter 8 serves as a summary and presents the conclusions drawn from the
data presented in Chapters 5, 6 and 7. The appendices review specific information and
procedures related to the research methods. Appendix A discusses EELS quantification
with Appendix B presenting band offset measurements and band alignment for ALD SiO2
on 4H-SiC. Appendix C outlines the procedures and program options used to model the
experimental data. References are provided at the end of each chapter to allow for easy
look-up of a noteworthy citation.
5
1.3 References
1. T.P. Chow. Microelectronic Engineering 83, 112(2006).
2. S.J. Pearton, C.R. Abernathy, M.E. Overberg, G.T. Thaler, A.H. Ostine, B.P. Gila, F.
Ren, B. Lou, and J. Kim. Materials Today 6, 24(2002).
3. D.C. Look, J.R. Sizelove. Appl. Phys. Lett. 79, 1133(2001).
4. Materials properties taken from
http://www.ioffe.rssi.ru/SVA/NSM/Semicond/index.html (April 2012).
5. H.-F. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, Appl. Phys. Lett. 70, 2028
(1997).
6. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, R. A. Weller,
S. T. Pantelides, L. C. Feldman, O. W. Holland, M. K. Das, and J. W. Palmour,
IEEE Electron Device Lett. 22, 176 (2001).
7. L. A. Lipkin, M. K. Das, and J. W. Palmour, Materials Sci. Forum 389, 985 (2002).
8. F. Ciobanu, G. Pensl, V.V. Afanas’ev, and A. Schoner, Materials. Sci. Forum 483, 693
(2005).
9. A. Poggi, F. Moscatelli, Y. Hijikata, S. Solmi, and R. Nipoti, Microelectronic Engineering
84, 12 (2007).
10. E. O. Sveinbjornsson, G. Gudgonsson, F. Allerstam, H.O. Olafsson, ,P –A. Nilsson,
H. Zirath, T. Rodle and R. Jos, Materials Sci Forum 527, 961 (2006).
11. S. Wang, S. Dhar, S.-r. Wang, A. C. Ahyi, A. Franceschetti, J. R. Williams, L. C.
Feldman, and S. T. Pantelides, Physical Review Letters 98, 026101 (2007).
12. V. Tilak, Phys Status Solidi A. 206, 101 (2009).
13. N. S. Saks, S. S. Mani, and A. K. Agarwal, Applied Physics Letters 76, 14 (2000).
14. N. S. Saks in Silicon Carbide: Related Major Advances, Eds. W.J. Choyke, H.
Matsunami and G. Pensl. (Springer, Berlin 2003).
15. A. Agarwal and S. Haney, Journal of Electronic Materials 37, 5 (2008).
16. Masato Noborio, Ph.D. Thesis, Kyoto University, 2009.
6
17. P. Mandracci, S. Ferrero, C. Ricciardi, L. Scaltrito, G. Richieri and C. Sgorlon, Thin
Solid Films, 427 (2003).
18. A. Golz, S. Gross, R. Janssen, E. Stein von Kamienski, H. Kurz, Diaomd Relat. Mat.,
6 (1997).
19. E. Augustyniak, K.H. Chew, J.L. Shohet, R.C. Woodsa, J. Appl. Phys., 85 (1999).
20. C.E. Viana, N.I. Morimoto, O. Bonnaud, Microelectron. Reliab., 40 (2000).
7
C H A P T E R 2
BACKGROUND
2.1 Si l icon Carbide
In 1907 Captain H J Round demonstrated electroluminescence of diode made from a
metal probe and a SiC crystal.1 Since then, silicon carbide has been the focus of a range of
electronic materials research work. Today a variety of SiC devices are commercially available
including Schottky diodes, LEDs, MOSFETs and thyristors.
2.1.1 Crysta l St ruc tur e
The structural building block of silicon carbide is the Si-C tetrahedron. This
tetrahedron, as seen in Fig. 2.1, consists of one silicon atom bonded to four carbon atoms or
one carbon atom bonded to 4 silicon atoms.2 An important property of the SiC tetrahedron
is the 1.89Å Si-C bond length, which is appreciably smaller than the Si-Si bond length
(2.35Å). This short bond length is responsible for the stiffness and microscopic hardness of
SiC, which are its best knownand most commonly employedqualities. Silicon carbide is a
polymorphic material meaning that it can exist in more than one crystal structure. Over 250
different polymorphs of silicon carbide exist ranging from amorphous films to crystalline
forms called polytypes. The difference between SiC polytypes is determined by the stacking
sequence of the Si-C tetrahedron in the <0001> direction.1 SiC tetrahedron are ordered into
close packed hexagonal as shown by the “A” atoms in Fig. 2.2. A second close packed
hexagonal plane can be layered onto the “A” layer. The arrangement of these atoms could be
either on the “B” sites or on the “C” sites. These sequences determine the SiC polytype.
While silicon carbide crystallizes in over 200 polytypes with lattice periods of up to 1000Å,
only a handful have been investigated for electronic applications. Table 2.1 outlines some of
8
the properties of common SiC polytypes. The stacking sequence of these common SiC
polytypes is illustrated in Fig. 2.3
AB
CB
AB
CB
A
A B C A B C
4H
10
.05
Å
AB
CA
CB
AB
CA
CB
A
A B C A B C A
6H
15
.12
Å
AB
CA
CB
CA
BA
CA
BC
BA
A B C A B C A B C
15R
37
.7 Å
A B C A B C A
AB
CA
BC
3C
Of these polytypes 4H-SiC is the most commonly used for power device applications. This
is due to its wide band gap, high electron mobility and high breakdown field (as compared to
3C), as can be seen in the previous table. These properties make 4H-SiC ideal for high
Si
C
CC
C1.89 Å
3.08 Å
A A A A
A A A A A
A A A A
B B B BC C C C
B B B BC C C C
Figure 2.1 Illustration of a
SiC tetrahedron
Figure 2.2 Site locations for close
packed hexagonal planes.
Figure 2.3 Stacking sequence of 4H, 6H, 15R and 3C silicon carbide in the [1120]
plane.
9
power, high temperature applications. Since the 1993, Cree has been the largest commercial
producer of 4H-SiC substrates. As of August 2010, after 17 years of development, Cree has
been commercially offering high quality 150mm 4H-SiC wafers. These large diameter, high
quality substrates have allowed for the growth of the SiC power device market. Several
companies currently have commercially available SiC power devices.
Table 2.1 Material properties of some common SiC polytypes3-8
3C - SiC 4H - SiC 6H - SiC 15R - SiC
Crystal Structure Cubic Hexagonal Hexagonal Rhombohedral
Stacking Sequence ABC ABCB ABCACB ABCBACAB
ACBAACB
# of atoms/cell 2 8 12 10
Eg (eV) 2.36 3.23 3.0 3.0
μe||c(at 300K)
(cm2/V·s)
800 950 600
λtherm (W/K·cm) 1 4.5 4.5
ε 9.72 10 9.66
Bulk Modulus (Mbar)
2.5 2.2 2.2 2.2
2.1.2 Semiconduct or Proper t i e s o f S iC
The great potential of SiC due to its improved properties has been known for
decades. Like other wide band gap semiconductor materials, SiC has the potential for higher
temperature operation, higher frequency operation and better efficiencies than conventional
silicon high-voltage power electronics. The high breakdown field (Eb) of silicon carbide
supports large voltages for high power operation, while a high thermal conductivity (λtherm)
allows for significantly higher junction operation temperature by virtue of low leakage
10
currents. Table 2.1 below outlines various materials properties for silicon versus some
common wide band gap materials.
Table 2.2 Material properties comparisons of common semiconductors for power
electronic devices 3-9
Si 4H-SiC 6H-SiC GaN
Eg (eV) 1.1 3.23 3.0 3.4
μe||c(at 300K)
(cm2/V·s)
1350 950 600 1350
Eb (MV/cm) 0.3 2.0 3.0 3.3
λtherm (W/K·cm) 1.5 4.5 4.5 1.7
ε 11.8 10 9.66 9.5
Ultimate Tj (°C) 200 >350 >350 700
ni (cm-3) 1.5x1010 8.2x10-9 2.3x10-8 1.9x10-10
2 .2 Interface of SiC and SiO 2
Similar to silicon, SiC forms a high quality SiO2 as a native oxide. From a device
fabrication standpoint, this likeness has been viewed favorably as it allowed for many of the
techniques developed for Si to be used on SiC.
2.1.3 Oxidat ion o f SiC
While there is no indication of differences in the bulk of thermal oxide grown on SiC
compared to Si, the oxidation process itself is quite different due to the carbon in the SiC.
Under varying pressures and temperatures, oxygen can either etch or cause oxidation of the
11
SiC surface.10The surface areal density of the carbon controls the SiC oxidation rates due to
the removal of carbon through out-diffusion of the carbonaceous species. As seen in the
oxidation reaction below, oxygen is required both to form SiO2 and is needed for the out
diffusion of CO:
2 SiC + 3 O2 → 2 SiO2 + 2 CO (2.1)
This results in a notably slower oxide growth rate for SiC as compared to Si at the
same temperature. This also results in different oxide growth rates for different crystal faces
of SiC. For MOS fabrication, SiO2 on SiC is generally grown between 1100°C and 1300°C in
an oxidizing ambient. While (2.1) illustrates one oxidation reaction, there could be other
reactions including:11
SiC + O2 ↔ SiO2 + C (2.2)
The carbon produced by this reaction would have to undergo an additional reaction,
as shown below in (2.4), or would be left at the interface. Carbon left in the oxide would be
determined by:
SiC + 2 CO ↔ SIO2 + 3 C (2.3)
2 C + O2 ↔ 2 CO (2.4)
This complex oxidation process leads to a variety of interface defects. Various
methods have been studied to improve the interface quality and resulting device
performance. These methods generally include pre-oxidation surface cleans, optimized
oxidation conditions and post-oxidation anneals to increase electron mobility and reduce the
density of interface traps.
2.1.4 Prob l ems a t the Inter fa c e o f S iC and SiO 2
The quality of the SiC/SiO2 interface is reflected in the channel mobility of the SiC
MOSFETs. Generally the carrier mobility is subjected to several scattering mechanisms.
The Hall mobility is defined as:
12
(2.5)
where τ is the mean scattering time for the speed v = μξ of a carrier in a solid. When
subjected to scattering processes, the mobility of a carrier can be determined by combining
the reciprocal mobilities of each scattering process.
(2.6)
Contributing scattering processes are phonon scattering, Coulomb scattering from charged
centers, carrier trapping and surface roughness scattering. As the relationship explained in
equation (2.6) is reciprocal, the mobility is dominated by the smallest component of τ. The
dependence of the bulk mobility, μbulk, on electric field and temperature can be used to
determine the dominating scattering process.12 Thus at room temperature the bulk mobility
is generally limited by phonon scattering. As phonon scattering increases with electric field,
the μbulk is usually taken to be the ‘low-field’ value.
The presence of interface
defects and of interfacial transition
layers also result in localized energy
states in the band gap. In n-channel
devices under gate biases high
enough to cause inversion, the
Fermi level nears the conduction
band edge. This allows these states
below the Fermi level to fill with
electrons, acting as traps for the
free carriers. This process is
illustrated in Fig. 2.4. This trapping
reduces the carrier lifetime and also
forms negatively charged centers
Figure 2.4 Depiction of the charge balance in a
SiC MOS system with interface traps illustrated.28
13
which increase Coulombic scattering. These mechanisms cause reduced effective mobility in
SiC MOSFETs. In silicon MOSFETs the effective mobility is typically 40-50% of the bulk
mobility. In 6H and 4H-SiC the effective mobility, µeff, is typically about 25% and 1% of the
bulk respectively. Schorner13 initially suggested that lower 4H-SiC MOSFET mobility was
caused by large numbers of interfacial defects producing interface states near the conduction
band of 4H-SiC. These states are neutral when empty and negatively charged when occupied
by an electron and are thus referred to as ‘acceptor-like’ states. Fig.2.5 illustrates the
distribution of these states at
the SiC/SiO2 interface. It is
clear from Fig. 2.5 that 4H-
SiC is sensitive to a larger
amount of states due to the
width of the 4H-SiC band gap
as compared to other SiC
polytypes.
In addition to surplus
states due to the wide band
gap of 4H-SiC, the presence
of carbon at the SiC/SiO2
interface results in additional
interface traps. There is no
evidence of any difference in bulk of the thermally grown SiO2 between oxide grown on Si
and oxide grown on SiC. However the presence of carbon in the oxidation process due to
the SiC has been shown to result in excess carbon at the SiC and SiO2 interface. This
interfacial carbon has been shown in the form of an SixCyO transition layer, through a wide
variety of techniques including scanning transmission electron microscopy (TEM) and
electron energy loss spectroscopy (EELS),14,15,16 Rutherford backscattering (RBS),17,18,19,20 x-
ray photoelectron spectroscopy (XPS), 21,22,23,24,25 and electron spin resonance (ESR).26,27While
Figure 2.5 Depiction of the assumed distribution of
interface states at the SiC/SiO2 interface for 4H-SiC, 6H-
SiC and 15R-SiC (adapted from Ref. 13)
14
these studies all deal with carbon at the SiC/SiO2 interface, new studies have shown the
presence of defects on the SiC side of the interface. This idea of “bulk traps” or defects on
the SiC side, initially introduced by Agarwal28, proposes that in addition to the acceptor-like
and donor-like interface traps shown in Fig 2.5, free carriers can be lost to traps in the bulk
of the SiC. Fig 2.6 shows an illustration of the band gap which has been revised to include
these bulk traps. Like interface traps, bulk traps in the SiC would affect µeff, through electron
trapping and Coulombic scattering. The existence of bulk traps in the SiC has been well
documented.29,30,31,32,33 These traps could be caused by a variety of sources including, carbon
and silicon vacancies, interstitials, impurities, carbon clusters, etc. Standard device
processing, notably implantation, high temperature annealing and thermal oxidation have all
been shown to promote these defects. The defects due to high temperature oxidation of SiC
have also been examined extensively using STEM and EELS.33,34,35 Hornetz used ARXPS to
investigate carbon containing near- interface oxides on the Si-face of 6H-SiC in 1994.36The
oxidation induced defects shown in
Fig 2.6, have been shown to exist
on both sides of the SiC/SiO2
interface, as oxide traps in the bulk
of the SiO2, as a transition layer on
the SiC side and as interface traps
in between. In addition, the depth
of the transition layer on the SiC
side has been shown to be related
to the processing and is proposed
to have a relationship to the device
mobility.35 Figure 2.6 Depiction of the charge balance in a
SiC MOS system with both interface and bulk
traps.28
15
Models of the SiC/SiO2
interface when paired with
experimental data, have been
constructive in understanding the
effect of defects. Several groups
have proposed models notably
groups led by Pantelides37,38,39 and
Deák40,41,42. The study of interfacial
carbon and its related defects
remains an area of interest due to the
difficulties in accurately
characterizing such low defect levels,
about 1013 cm-2. While this level is
low from a physical standpoint, the
electrical effects on the device are paramount. Thus complete characterization and
understanding of the defect and its effects on the band gap lies in the critical path of 4H-SiC
MOSFET development.
2.1.5 Inter fa c e Pas s iva t i on
As reducing the band gap of 4H-SiC is not an
option, work to reduce Dit has centered around the
oxidation process and post oxidation anneals (POA).
Varying the oxidation process by adding Ar anneals43 or
by re-oxidizing at lower temperatures44, have been
demonstrated to provide a minor reduction in states
deep in the band gap. Hydrogen has also been used
successfully to passivate dangling Si bonds at the
interface, reducing Dit in the mid-gap by an order of
Figure 2.8 Schematic of a SiC
metal-oxide-semiconductor
capacitor
Figure 2.7 4H-SiC interface trap densities near the
conduction band for varying post oxidation
anneal ambients.49
16
magnitude.45 However H passivation does not affect the near-interface states and as such
hydrogen alone does not significantly improve device performance. In 1996, mid –gap states
were shown to be reduced by the pioneering “wet reox” 950 ºC anneal process. However
this mid-gap reduction had no effect on µeff. In 1997, POA in nitric oxide (NO) at the high
temperature of 1100ºC was shown to reduce Dit in 6H-SiC MOS systems.47 Similar positive
results were demonstrated for SiO2/4H-SiC interfaces using both NO44,47and N2O.48 With
NO anneals trap densities near the conduction band have been reduced from ~ 1013 cm-2eV-1
to ~1012 cm-2eV-1, as shown in Fig. 2.7. This reduction in near-interface states has led device
mobilities approaching 60 cm2V-1s-1.50,51,52 These mobility values have designated NO
anneals as an essential processing step for the fabrication of SiC MOSFETs for both
scientific and industrial applications. While the benefits of NO anneals have been ascribed to
bonding of nitrogen at the interface, the kinetics of the process are still under
investigation.Exposure to NO at high temperatures has been shown to reduce the amount
of excess carbon at the interface through both AFM53, which shown a smoother surface post
anneal and through XPS54. XPS studies have revealed both a reduction in C containing
compounds at the interfaces, as well as formation of Si-N and C-N bonds. These studies
have encouraged the notion that nitrogen is either operating via two possible paths: nitrogen
binding at defect sites/dangling bonds
or through nitrogen substitution for a
three-fold C or Si. However the
mobility of SiO2/4H-SiC interface as a
percentage of the bulk mobility is still
low compared to silicon. Additional
improvements must be made to the
interface in order to determine the
maximum inversion mobility of 4H-
SiC MOS systems.
The alternate faces of SiC, a-
Figure 2.9 Band offsets for 4H-SiC MOSFETs
with an aluminum gate. 58, 59
17
face and C-face, have also been investigated for increased mobility. Both faces have great
potential for development with increased oxidation rates as well as improved mobility over
the commonly used Si-face. However the relationship between increased oxidation rates and
carbon related defects requires further investigation. Deposited oxides, notably low
temperature PECVD oxides, have also been studied in the past decade but have not shown
benefits over thermally oxidized samples.55,56 Low temperature deposition is desired as a
means of avoiding any defect creation from the high temperature thermal oxidation.
However PECVD oxides have not shown any improvement over thermally grown oxides,
perhaps related to the plasma damage imparted to the gate oxide through this deposition
technique. As such a low temperature technique that does not involve exposure to plasma,
such as atomic layer deposition, is an ideal candidate for evaluation.
2 .3 SiC MOSFETs
As discussed previously, the ability of SiC to form SiO2 as its native oxide is an
advantage when comparing SiC to other wide band-gap materials. The deposition of a metal
onto this native oxide results in the formation of a metal-oxide-semiconductor (MOS)
capacitor. MOS capacitors, as shown in Fig.2.8,
are valuable test devices that also form the
functional core of the metal-oxide-
semiconductor field effect transistor
(MOSFET). The relationship between the
energy levels of the metal (assuming Al), oxide
and semiconductor is shown in Fig 2.9. This
figure shows an ideal system with no states in
the gap. Actual devices are far from perfect and
contain numerous states in the gap as discussed
in the previous sections.
Figure 2.10 Schematic of a 4 terminal
p-type, n-channel MOSFET
18
MOSFETs are four terminal transistors used for switching or amplification of small
signals. They are the most common transistor used in digital or analog circuits. To operate a
MOSFET a potential is applied to a gate electrode to regulate the flow of minority carriers
from the source to the drain. This turns the device off and on or can be used to amplify
signals.57 MOSFETs are typically fabricated with highly doped contacts in a lightly doped
substrate, a gate oxide and contacts. Figure 2.10 illustrates a simple four terminal MOSFET.
MOSFETs can be fabricated to be enhancement or depletion mode devices with an n-type
or p-type channel. Enhancement mode devices are normally off and exhibit negligible
current flow with zero volts on the gate while depletion mode devices are normally on and
require reverse biased gates to turn off the device.The following MOSFET descriptions will
be based on an n-channel MOSFET as seen in fig. 2.10.
2.3.1 MOSFET Operation
As described above the operation of the MOSFET is controlled by applying a
positive or negative voltage to the gate electrode. With no voltage applied to the gate the
Fermi levels of the metal,
oxide and semiconductor
align assuming no fixed
oxide charges, interface
states and work function
difference between metal
and SiC. This is considered
equilibrium or flat band
condition. Figure 2.11
shows the operation modes
of an n-channel MOSFET.
Schematic a show the flat
Figure 2.11 Band diagrams showing the 4 modes of
operation for an n-channel MOSFET (a) Equilibrium or
Flat band (b) Accumulation (c) Depletion and (d) Inversion
19
band condition with all
Fermi levels aligned. The
application of a negative
gate voltage results in
hole accumulation at the
oxide/semiconductor
interface. As seen in Fig
2.11b this causes upward
band bending.
When a positive
voltage is applied from the gate electrode to the body, VGB, the positively charged holes are
repelled away from the oxide/semiconductor interface forming a depletion region. This
region filled with negatively charged acceptor ions accounts for the negative charge at the
semiconductor surface. As seen in Fig 2.11c, the bands in this region bend downward to
bring Ei closer to EF. A schematic of a depletion region in a MOSFET can be seen in Fig
2.12. When VGB is sufficiently positive, the large positive gate potential attracts free electrons
to the surface and creates an inversion layer, or channel. In this channel region Ei is below
EF as show in Fig. 2.11d. A schematic depicting a MOSFET with an inversion channel can
be seen in Fig 2.12. The extremely large electron concentration results in an n-type
conducting layer. The minimum gate voltage required for channel formation is called the
threshold voltage, Vth. Although inversion layers are formed when φs is greater than φF, a
true conducting channel only exists under strong inversion (φs≥ 2φF).
2.3.2 MOSFET Charac t er i s t i c s
MOSFETs are generally tested by applying a variable gate voltage and examining the
relationship between the drain current and the drain to source voltage. This typical
measurement, generally referred to as the family of curves, can be seen in Fig. 2.13. Current
saturation can occur at all applied gate voltages and is shown in the saturation region. The
Figure 2.12 Schematic of a 4 terminal, p-type MOSFET
showing (a) the depletion region and (b) the inversion layer
and depletion regions
20
point at which current saturation begins, or the pinch-off voltage, is where the resistance of
the channel is too great to move additional carriers through the channel. This relationship is
expressed as:57
(2.7)
where W and L are the depletion region
width and length, Cox is the oxide
capacitance and VG is the gate bias. Thus
the saturation current is dependent on the
effective mobility, oxide capacitance and
threshold voltage all of which can be
engineered to change device characteristics.
The MOS structure is also often
evaluated using capacitance-voltage, C-V,
measurements. A sample C-V curve
illustrating the three regions of operation is
shown below in Fig. 2.14. C-V
measurements are performed by sweeping
the gate voltage and monitoring the
capacitance. These measurements can be
taken at high frequencies (> 1MHz) or at
low frequencies (between 1-100Hz). At
high frequencies, carriers in the inversion
layer do not have time to respond to the
rapidly changing gate voltage. Unlike in a
Figure 2.13 Typical MOSFET family of
curves showing Id-Vds behavior for varying
gate voltages.58
Figure 2.14 Typical p-type MOS capacitor
high frequency and low frequency C-V
curves showing the three regions of
operation
21
MOSFET with source and drain regions, within a MOS capacitor, the electron concentration
is determined by the slow process of thermal generation and recombination. Thus in strong
inversion at high frequencies, there is no electron contribution to the capacitance and the
capacitance is at a minimum, Cmin. At low frequencies, there is ample time for minority
carrier generation in the bulk and carriers can move into the inversion layer or recombine in
the bulk of the substrate. Operation in the accumulation region does not vary with frequency
due to the faster response of the majority carriers.
The relationship between the capacitance and the charge at the semiconductor
surface for all regions is defined as:61
(2.8)
where Qs is the surface charge. The total capacitance can be written as the sum of the oxide
capacitance and the semiconductor capacitance as shown below.7
(2.9)
The semiconductor capacitance can be further explained as the sum of the depletion
layer charge and the inversion layer charge. From these relationships the C-V curveillustrated
in Fig. 2.14 can be explained. When the device is in accumulation and the semiconductor
capacitance is large, the total capacitance is approximately Cox. As the gate voltage increases
and the device enters depletion and weak inversion, the inversion capacitance become
negligible and the total capacitance is a series combination of Cox and Cd, the depletion
capacitance. With low frequency measurements, the inversion capacitance, Ci, increases
rapidly and becomes the largest contributing factor to the semiconductor capacitance in
strong inversion. The total of Cd and Ci increases and the total capacitance approaches Cox.
22
2.3.3 Oxide and Inte r f a ce Charge
Thus far, explanations of MOS capacitor and MOSFET operation have assumed an
ideal MOS system with no imperfections. Unfortunately the semiconductor, oxide and metal
all have intrinsic imperfections. There are four major sources of charge at the
oxide/semiconductor interface and in the oxide that can affect MOS performance. These
charges are illustrated in Fig. 2.15. The four major charges include: interface trap charge,
oxide fixed charge, oxide trapped charge and mobile ionic charge. Interface trap charges, as
discussed in the previous sections, are
present at the oxide/semiconductor
interface due to defects at the interface.
These defects can include dangling
bonds from the termination of the
crystal lattice or residual carbaceous
species from the oxidation of the
semiconductor. Interface traps can
trade mobile carriers with the substrate,
acting as donors or acceptors
depending on the trapped carrier. Fixed charges in the oxide are generally located near the
transition region on the oxide side of the interface. These charges are the created by the
oxide formation process and are not related to oxide thickness. Oxide trapped charges
generally found at the oxide interfaces with the gate or semiconductor. These are most
commonly a consequence of oxide imperfections, ionizing radiation, high-energy carrier
injection via avalanche or tunneling from the surface. Lastly mobile ionic charges are the
result of contaminates introduced through device processing. The mobile nature of the ions
means that they move freely in the oxide under the presence of an electric field and thus are
easily screened for. A clean process environment, high grade consumables and proper wafer
handling greatly reduce the likelihood of mobile contamination.
Figure 2.15 The four types of charges, labeled
by color, in the MOS system.12
SiO2
23
The primary bulk electron trap in SiO2 is reported to be related to water, as the trap
density scales with vapor pressure during gate oxide growth.45,62 These traps are neutral but
become negatively charges after electron capture. The negative charge is not removed by
photo-excitation after capture. This suggests that the trapping mechanism is an electro-
chemical reaction that changes the local oxide structure. For holes, excess positive charge
appears most stable close to the SiO2 interfaces the metal and semiconductor.18 This positive
charged region near the interface is enhanced in nitrided SiO2 on silicon.63-68 In nitrided SiO2
grown on SiC, the hole trap density has been reported to scale with the nitrogen
concentration at the oxide/semiconductor interface.69 It is expected that an SiOxNy
transition region would result in hole traps as the band-gap of Si3N4 falls within the SiO2
band-gap.70 Calculations have shown that nitrogen provides a lone pair of electrons in Si-N-
Si or Si-NO-Si configurations that can capture a hole.69 While research has shed light on the
effects of excess carriers in the SiO2 and provided several possible models, the specifics
associated with charge trapping and interface state generation on the atomic-scale are still
unclear.
2.3.4 Non-Id ea l Charge e f f e c t on I -V Charac t e r i s t i c s
As these added charges do not balance out, the ideal flatband condition, seen in Fig.
2.11, is only achieved by applying a bias to the device. This shifts the whole C-V curve by
the amount necessary to overcome the oxide charge. Since the threshold voltage is defined
as the onset of strong inversion, then the VT is also shifted. The additional oxide charges are
included in the calculation of the threshold voltage as:61
(2.10)
where ΦMS is the work function potential difference between the gate and the
semiconductor, and Qi and Qdare the interface and depletion charges. While this equation is
valid for both n-type and p-type devices, it predicts a negative VT for p-channel devices. VT
could be positive or negative for an n-channel device. Thus for an n-MOSFET a negative
24
threshold is symptomatic of a normally-on device, while a positive threshold indicates an
enhancement-mode device.
Non-ideal oxides also exhibit electric field dependant conduction of gate leakage
current. As the device ages during normal operation, charges are built up in the gate
dielectric and interface states are generated. These processes and the associated leakage
currents can result in reduced inversion layer mobility, threshold voltage instabilities and the
ultimate breakdown of the gate dielectric. Excess carriers in the dielectric are impossible to
avoid due to low and high field injection and tunneling mechanisms including: thermionic
emission, Fowler-Nordheim tunneling, Frenkel-Poole emission, trap assisted tunneling and
direct tunneling.
As shown in Figure 2.9, the 4H-SiC/SiO2 conduction band offset is about 2.7eV, which
should be enough to provide a barrier to thermionic excitation of carriers through the oxide
layer. The current due to thermionic emission is given by:71
(2.11)
where A* is the effective Richardson constant for thermionic emission in Acm-2K-2. For free
electrons A is 120 Acm-2K-2 and for SiC A* ≈ 2.1 x A.71, 72From the equation for current
density due to thermal emission one can verify that under temperatures of 600 ºC or greater,
currents due to thermionic emission areinsignificant.
Fowler-Nordheim (F-N) occurs at high enough oxide fields, where carriers from the
metal or semiconductor can tunnel through a portion of the oxide. The triangular barrier
related to F-N injection can be seen in Fig. 2.16. This tunneling results in an intrinsic
leakage current, JFN. The tunneling current density can be expressed as:73
(2.12)
where m is the free electron mass and m*ox is the effective mass in the oxide. F-N injection is
not likely to be encountered in normal operating conditions, except in ultra-thin devices.
25
Frenkel-Poole (F-P) emission is commonly seen at high temperature and high fields.
It is due to emission of carriers from the localized states within the oxide. The presence of
an electric field modifies the potential energy profile such that the work required to free a
trapped carrier is reduced. The current density for Frenkel-Poole emission is given by:71
(2.13)
Like thermionic emission, Frenkel-Poole emission is driven by thermal emission. However
there are differences, including that carriers process by drift conduction in F-P emission and
that F-P is defect-mediated and thus
extrinsic.
Trap assisted tunneling occurs
through defects in the oxide. These
traps act as stepping stones for charge
carriers. This process is also referred to
as stress-induced leakage currents when
the traps are formed through prolonged
exposure to high electric fields. For both
processes the limiting step of the
process is tunneling from the traps to
the conduction band. Thus reducing the
number of traps available is critical to
deterring this type of tunneling.
Direct tunneling occurs when
electrons from the metal or semiconductor can tunnel through the gate oxide without going
through the conduction band. Oxide thickness and dielectric constant can be varied to
increase the barrier and reduce direct tunneling. The use of high-k dielectrics has allowed for
similar effective oxide thicknesses to be achieved with physically thinner oxides.
Figure 2.16 Illustration of injection and
tunneling mechanisms that can cause leakage
in MOSFETs
26
2.3.5 Non-Id ea l Charge E f f e c t on C-V Charac t er i s t i c s
The addition of non-ideal charges increase the density of interface states as previously
discussed. C-V measurements are often used to investigate Dit as trap response changes with
frequency and bias. Traps can change their charge state quickly to respond to varying gate
biases, moving above or below the Fermi level. States below the Fermi level are more likely
to be occupied than those above. As the bias changes, traps above the Fermi level give up
their electrons to the semiconductor, while those below the Fermi level will trap electrons
from the semiconductor. Further discussion of the affect of interface traps on C-V
measurement is provided in Chapter 3.
2 .4 Summary
As thoroughly reviewed in this chapter, the quality of the gate oxide in MOSFETs is
critical. The standard method of thermally oxidizing the SiC results in a high density of
interface traps, Dit, at the SiC/SiO2 interface, associated with excess carbon from the
oxidation process. Low temperature deposited gate oxides avoid the problems exhibited by
thermal oxidation of 4H-SiC. The low temperature technique of atomic layer deposition is
attractive as it provides not only the ability to deposit at low temperatures while avoiding
plasma damage associated with PECVD, but also provides an extremely conformal coating.
This would be beneficial when dealing with implanted regions as the increased oxidation rate
due to high levels of damage can lead to preferential consumption of implants and reduced
device performance. The conformal nature of ALD would also be an advantage when
dealing with trench structures as the varied oxidation rates of SiC crystal planes, results in
different oxide thicknesses from trench sidewalls to wafer surface and trench bottoms. The
use of low temperature deposited ALD oxides to improve MOSFET performance will be
investigated in this thesis.
27
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Raashkeev, L. Tsetseris, M. H. Evans, I. G. Batyrev, L. C. Feldman,et al., Materials
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Feldman, and S. T. Pantelides, Physical Review Letters 98, 026101 (2007).
40. J. M. Knaup, P. Deák, T. Frauenheim, A. Gali, Z. Hajnal, and W. J. Choyke,Physical
Review B 71, 235321 (2005).
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Science Forum 556-557, 541 (2007).
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Applied Physics 79, 2529 (1996).
44. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. D. Ventra, S. T.
Pantelides, L. C. Feldman, and R. A. Weller, Applied Physics Letters 76, 1713
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50. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, R. A. Weller,
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(2000).
32
C H A P T E R 3
RESEARCH METHODOLOGY
3.1 Atomic Layer Deposit ion
Atomic layer deposition (ALD) was first introduced by Suntola and co-workers in
the late 1970s as atomic layer epitaxy (ALE).1 It was initially presented as a new technique to
deposit amorphous and polycrystalline thin films. In the decades since its introduction ALD
has become a technique of great interest due to its many benefits. The primary benefits
include complete control over the deposition process and ability to achieve conformal pin-
hole free coatings even in high aspect ratio and complex structures.
ALD growth chemical gas phase process is based on alternative, self – limiting
surface saturating reactions. A monolayer of precursor saturates the surface with each
exposure step. The simplest ALD cycle is based on the following four step sequence:
1) Exposure of the first precursor, precursor A, resulting in a reaction of the surface
with precursor A
2) Purge of non-reacted precursor A and gaseous reaction by-products through gas
flow or evacuation of the process chamber
3) Exposure and self-terminating reaction of the second precursor, precursor B
4) Purge or evacuation
These steps represent one complete reaction cycle and can be repeated as necessary
to achieve the desired film thickness. Additional precursors can be added to create reaction
cycles with six or more steps provided complimentary self-limiting reactions are formed. An
illustration of the four step sequence can be seen below in Fig. 3.1. In this illustration the
initial surface can be seen in step a and the exposure of the first vapor precursor (the green
symbols) is show in drawing b. When the reaction is complete, as seen in schematic c, the
33
excess precursor is
purged or evacuated.
The second
precursor (the blue
symbols) is pulsed
into the chamber and
begins to react in
drawing d. Finally
when the self-
limiting reaction is
complete the excess
precursor is again
purged and the
reaction cycle can
begin again. In each
of these chemical
reactions the entire
surface reacts to
complete saturation,
ensuring that other
reactions do not
occur. This self –
limiting feature
directly leads to a
number of
advantages of ALD
including:
Figure 3.1 Schematic of a four step ALD sequence resulting in
one complete reaction cycle.
34
Easy and precise thickness control
Exceptional conformality, even with complex structures and high aspect ratios
High quality films even at low process temperatures
Good reproducibility
Ability to vary deposited film materials or create multilayer structures in situ
Ability to achieve sharp interfaces between films
In an ALD process, a plot of the growth rate versus substrate temperature is often
used to determine the optimal processing region. These plots show the “ALD process
window” as a flat plateau region where self-limiting reaction takes place. An example of
these plots can be seen below in Fig. 3.2. This figure clearly illustrates how temperature is
the most important parameter in controlling the saturation mechanism. If low growth rates
are observed, temperatures could be too low to achieve the required activation energy for
the reaction or temperatures could be so high that the monolayer of precursor is desorbing
from the surface. Low temperatures with high growth rates indicate condensation of the
precursor on the surface. Finally when temperatures are too high, the precursor can
decompose on the
surface thus
prohibiting self-
limited growth.
ALD
processes are
performed in a flow
reactor. The main
inert gas flow feeds
reactants into the
process chamber.
The pressure, timing
Figure 3.2 The ALD process window as related to growth rate
versus temperature.
35
and flow speed of the
main gas flow are
controlled to ensure
adequate purging
between cycles as well
as fully separate
reaction sequences for
each precursor. Flow
reactors are beneficial
as they are easily
scalable to larger
batches, but also allow
for the study of
reaction kinetics of the
ALD process. This
study can be
completed by
examining the film thickness for a variety of precursor dosages and chamber conditions as
related to the flow direction. Fig. 3.3 shows possible outcomes and explanations for study
results. Graph a) in Fig. 3.3, shows the ideal ALD growth case, where the thickness is even
across the entire sample. Complete surface saturation has been achieved and no problems
with desorption, condensation or decomposition of the precursors are seen. In b) thickness
is higher near the precursor inlet area which indicates insufficient purging. This could be due
to CVD growth due to precursors being in the sample chamber concurrently or due to
thermal decomposition of a precursor. Graph c) shows the thickness decreasing steadily
across the width of the sample. This is generally due to insufficient dose of the precursor to
accomplish complete surface saturation. Insufficient dose is also the problem shown in d)
where under-dosing combined with high reactivity result in a steep drop-off in thickness
farther away from the precursor inlet. Finally graph e) shows lower thicknesses at the
Figure 3.3 Thickness plotted as a function of flow direction for
varying precursor doses and process conditions.2
36
precursor inlet side of the sample most likely caused by desorption of a monolayer possibly
related to long pump times or higher than needed temperatures.
Precursor dosage and chamber conditions are critical to achieving a stable,
reproducible ALD process. The importance of temperature, purge time, carrier gas pressure
and exposure time to ensure good surface saturation are apparent. Proper precursor dosage
is also important as longer pulse times not only waste precursor but also cause longer purge
times, lengthening a complete reaction cycle time. Proper precursor dosage depends on
several variables including, total surface area of the substrates, monolayer saturation density,
chamber used, pressure and flow of inert carrier gas and the sticking probability of the
precursor on the sample surface. The density of molecules in a gas is shown as:
(m-3) (3.1)
where k is Boltzmann’s constant, T is the temperature (K), and PR is the partial pressure of
the reactant in the source. In terms of partial pressure and volume, the dose of the reactant,
X, can be shown by:
(3.2)
where V is the volume of the gas (m3) containing the reactant, X, at partial pressure PR, A is
the sample surface area, as is the monolayer saturation density (molecules/m2), and u is the
materials utilization coefficient. Materials utilization coefficients typically range from 0.1 to
0.8 and are related to the feeding time and mass flow of the reactant.
There are relatively few limitations of ALD. The foremost limitation is the slowness
of the process. Since a monolayer of the film is deposited per reaction cycle, growth rates
can be quite slow. This is especially true for more involved reaction cycles that use more
than 2 precursors, or require extra time to complete steps. Exposure times, where the
precursor remains in the chamber for a set time to allow complete surface reaction, are a
source of longer cycle times. Stickier precursors, such as water at lower chamber
37
temperatures, also often cause longer cycle times as longer purge times are needed to remove
them from the chamber. Fortunately, as the scaling down of microelectronics continues, film
thickness requirements are also dropping, making ALD more attractive due to its various
benefits.
3 .2 Materia l s Characterizat ion Techniques
3.2.1 El l ipsomet ry
Ellipsometry is a method often used to measure film thickness. It is based on
measuring the change in the polarization state of light after interacting with the surface of a
sample. In a basic setup light from a light source is linearly polarized. The polarized light
falls on the sample and is reflected, transmitted or refracted. The reflected light passes back
up through another polarizer before hitting the detector. The complex reflectance ratio, , is
measured and is given by:
(3.3)
where rp is the amplitude oscillating parallel to the plane of incidence, rs is the amplitude
oscillating perpendicular to the plane of incidence, tan (ψ) is the amplitude ratio after
reflection and Δ is the phase shift. Ψ and Δ are typically measured as a function of wave
length and incident angle. Optical constants and thickness parameters are then varied to find
the best fit for Ψ and Δ to the experimental data.
Ultraviolet ellipsometry is very useful for making optical measurements in the
transparent spectral range of some materials. This is especially the case with 4H-SiC which is
uniaxially anisotropic being a hexagonal structure. In the UV range the SiC absorbs incident
light, thus avoiding problems with reflection from the backside of the sample. These
reflections make it particularly difficult to accurately model and interpret SiC results. Thus
38
fitting SiC ellipsometry data at wavelengths below 350nm allows for improved accuracy and
solves problems with backside reflectance.
3.2.2 X-ray Photoe l e c t r on Spec t ro s copy
X-ray photoelectron spectroscopy (XPS) is a type of spectroscopic characterization
that employs the photoelectric effect. This technique is also known as electron spectroscopy
for chemical analysis (ESCA). A photon source in the X-ray range is used to irradiating the
surface of a material. Direct transfer of energy from the photons to core-level electrons
causes emission of characteristic photoelectrons. Generally Al Kα (1486.6 eV) or Mg Kα
(1253.6 eV) X-rays are used. While the X-rays can penetrate the sample up to a micron or so,
only information from 10 to 100Å from the surface is part of the XPS spectrum. Analysis
the kinetic energy and number of the photoelectrons emitted from the near surface is
completed using a cylindrical mirror analyzer. The concentration of the emitting atom in a
sample determines the number of the electrons measured, while the energy is related to the
atomic and molecular location. A spectrum is then plotted from which elements present and
the binding energies of these elements can be determined. All elements (excluding hydrogen
and helium) can be detected and identified at concentrations > 0.1 atomic percent using
XPS.3 The basic Einstein equation, seen below, can be used to describe the photoemission
process.3
(3.4)
where BE is the binding energy of the electron in the sample atom, hν is the energy of the X-
ray source and KE is the energy measured by the spectrometer. As we know hν and measure
KE, then BE can easily be determined. From the binding energy, the type of atom can be
determined as well as the existence of other atoms bound to the emitting atom. Variations in
binding energy can be associated with covalent or ionic bonds between atoms. Secondary
39
peaks can also appear in XPS spectra, generally due to Auger transitions, plasmon processes
and other energy loss processes.
There are two types of electron energy levels for an atom: tightly bound core levels
and weakly bound valence levels. As binding energies are unique characteristics of each
element, identification of core-level BEs can be used to identify all elements in the periodic
table. Performing quantitative analysis on XPS data can yield relative atomic concentrations
in the sample. This requires measurement of relative peak values as well as cross section
values. Many software programs used today for XPS analysis including CASA XPS, are
capable of these calculations. These softwares also work correctly calibrate spectrum to a
known peak value, such as the carbon 1s peak, to ensure proper measurement of other peaks
relative to the C 1s. Peak fitting can also be performed using these softwares and helps to
account for variations in peak widths and line shapes often due to the existence of
contributory features. Understanding of the background signal as well as a good knowledge
of your sample chemistry is important to peak fitting.
There are few shortcomings with current XPS technology, though some still exist.
XPS requires ultra-high vacuum to avoid surface contamination that could influence results.
General sensitivity for XPS tools is between 0.01 and 0.3 atomic percent.3 Insulating samples
may charge when exposed to the X-ray beam, distorting the spectra and causing inaccurate
BE results.
3 .2 .3 Scanning Transmiss ion El ec t ron Micros copy
Scanning transmission electron microscopy (STEM) is form of electron microscopy.
STEM in similar to other forms of electron microscopy, notably SEM, except samples are
thinned to be typically less than 100 nm and are used in conjunction with high energy
electron beams often around 200 keV. This pairing allows for low sample interaction
volumes and lower beam spreading within the sample which results in superior resolution
40
compared to other electron microscopy techniques. The STEM is a good choice for
investigating compositional and structural properties of a sample at high resolutions.
In a STEM the beam of electrons is converged onto a narrow spot using the
electron optics. In a traditional TEM, a nearly parallel beam of electrons is created by two
condenser lenses. An objective lens is then used to focus the beam of electrons and form a
real image. Aligning the condenser lenses to produce the original gun crossover as a spot on
the sample is called convergent beam TEM.4,5 This spot (approximately 1-10Å) is then
rastered across the specimen through the use of scanning coils. Many TEMs are currently
equipped with STEM capabilities. There are also dedicated STEM tools. The electron optics
in a dedicated STEM more closely resembles an SEM than a TEM. This difference in
electron optics generally allows for better resolution in a dedicated STEM tool over a TEM
operating in STEM mode.
Electrons transmitted through the sample are detected with a detector at the bottom
of the column. The raster of the beam allows for additional sample data to be collected,
including x-rays, secondary electrons and backscattered electrons. The collection of
incoherent electrons, elastically scattered at high angles, in conjunction with a high-angle
annular dark-field (HAADF) detector placed in the post specimen optical axis allows for
HAADF imaging. This imaging technique is also called Z-contrast as the cross section for
Rutherford elastic scattering is related to Z2.4,5 Z-contrast imaging results in atomic
resolution images where the contrast is related to the atomic number of the specimen.
Higher Z regions, scatter more electrons and have a higher image intensities than low Z
regions in the sample.4,5 Fig. 4 illustrates the differences in a bright field (BF) versus HAADF
STEM image. The bright field image on the left is formed by transmitted electrons and a
bright field detector. These transmitted electrons have been either inelastically scattered at
low angles or not scattered at all. Phase contrast is the main contrast mechanism in the BF
image. This means that the intensity of the image is related to the crystal orientation,
structure and sample thickness. The HAADF image is a result of incoherent elastically
scattered electrons that have traveled close to the sample atomic nuclei. Phase differences
41
Figure 3.4 STEM images. Left: Bright field (BF) image. Right: High angle annular dark field
(HAADF) image. The left side of both images is SiO2 with crystalline SiC on the right side.
Figure 3.5 Schematic of a dedicated STEM showing various detectors.
42
between scattered electrons are irrelevant and there is no interference of the wave function
phases. The image intensity can be related to the atomic number squared as described above.
The HAADF detector used increases the collection angle to the point that no Bragg
diffracted electrons are detected. As such compositional changes and atomic positions can
be more straightforwardly construed from HAADF images. This is clearly illustrated by the
HAADF image in Fig. 3.4 where the silicon atoms in the SiC are the ordered white dots on
the right half of the image. The same regions can be seen in the BF image however the
atomic positions are not as clearly seen. A schematic of a dedicated STEM with a HAADF
detector can be seen in Fig. 3.5.
The resolution of a STEM is limited by the round electron optics that cause spherical
aberrations, Cs.7 These aberrations limit spatial resolution to about 1-2Å for electron energies
of 100 – 200keV. Scherzer offered three ways to address the problem of spherical
aberration: 1) use non-round lenses 2) uses lenses with charge on axis and 3) use time-
varying fields. Major advancements have been realized in the decades since Scherzer offered
his solutions. Several STEM tools are currently outfitted with third order spherical
aberration correctors. These correctors use non-round lenses to vary the aberration
coefficients and minimize the aberration function. Fifth and seventh order rotationally
symmetric aberrations can be offset through the use of today’s correctors and future
correctors will correct to the fifth order or higher.8 This has greatly improved the resolution
limits of aberration corrected STEM tools and sub-angstrom resolution approaching 50pm is
a reality.9,10,11 However chromatic aberrations, higher order aberrations and instabilities
caused by both electrical and mechanical systems still leave room for further improvements.
3.2.4 Elec t ron Energy -Loss Spe c t r os c opy
Electron energy-loss spectroscopy (EELS) is an analytical absorption spectroscopy
technique used routinely in transmission and scanning transmission electron microscopy.
EELS is a popular STEM technique that is used to determine information on local chemistry
43
and structure. The EELS technique is actually rather simple. After high-energy electrons
have passed through the sample, the energy loss of the electrons is measured. A high
resolution electron spectrometer below the CCD is used to bin the electrons by kinetic
energy. A schematic of a common EELS setup can be seen in Fig. 3.6 below.
Figure 3.6 Schematic of an EELS spectrometer and HAADF detector in a STEM.6
An electron energy-loss spectrum is produced which show the intensity as a function
of the electron energy. A sample spectra is show in Fig. 3.7. This spectra shows the most
prominent inner shell energies of silicon (100eV), carbon (284.5eV) and oxygen (532eV).
The lack of an extended broad hump after the peaks in Fig. 3.7 indicates that there is little to
no plural scattering as can been seen with thicker samples. The black line at 284.5eV is used
to calibrate the spectrum to ensure proper analysis of the EELS data. The zero loss peak and
plasmon peaks do not appear separately on the spectra due to the x-axis resolution shown.
44
Figure 3.7 Example spectra of a SiC sample. Peaks include silicon (100eV), carbon
(284.5eV) and oxygen (532eV).
Of great importance with EELS data collection is the ability to correlate the area the
EELS scan was taken from to a specific location on the sample. The use of EELS in
conjunction with Z-contrast imaging allows for the EELS sampling area to be set based on
the Z-contrast image. This allows for precise sampling of interfaces, grain boundaries,
inclusions and a variety of other specific areas of significance. Another benefit of EELS is
the accuracy of quantification. No standards are required for quantification. Through the use
of cross sections the measured core-loss intensities can be converted into elemental ratios.
Knowledge of the collection angle, range of energy-loss and incident-electron energy are
required to complete the quantification calculations.12 Cross sections are known within 5%
for K-edges and within 15% for most L-edges.13 The use of the Hartree – Slatter method (as
used by Digital Micrograph) allows for determination of cross sections with higher precision.
This combined with EELS probe resolutions approaching 1-2Å, allows for highly accurate
elemental ratios to be determined. For these critical experiments low sample drift is of acute
importance and often involves waiting for the microscope power supplies and stage to
45
stabilize. With proper tool stabilization, Z-contrast STEM combined with EELS is an
excellent technique for determining the chemistry and structure of a specific region.
3.2.5 Secondary Ion Mass Spec t romet ry
Secondary ion mass spectrometry is an analytical technique often used to study the
composition of thin films and solid surfaces. The sample surface is bombarded with a
primary ion beam. The emitted secondary ions are analyzed by mass spectrometry. Static
SIMS is generally used for sub-monolayer elemental analysis. Dynamic SIMS can be used to
obtain compositional information as a function of depth. These depth profiles can be
generated by monitoring the secondary ion count rate of selected elements as a function of
time. Relative sensitivity factors (RSFs), which describe the sensitivity of an element of
interest, are used to convert the vertical axis from ion counts into concentrations. Dynamic
SIMS is often preferred over other depth profiling techniques due to its sensitivity to very
low concentrations (parts per billion) of elements.
3 .3 Electr ica l Characterizat ion Techniques
3.3.1 Capac i tance – Vol tage Measurements
Capacitance – voltage (C-V) measurement is one of the most common electrical
characterization techniques. Oxide thickness, flat band voltage, doping density and even the
density of interface traps can be determined through C-V measurements. As the gate voltage
is swept, the width of the space charge region varies. The width of this space charge region
as a function of capacitance for an MOS capacitor can be defined as:14
(cm) (3.5)
where C is the capacitance in F, Ks is the semiconductor dielectric constant, A is the area in
cm and εO is the permittivity of free space (8.854 x 10-14 F/cm). Since in accumulation there
46
is no depletion layer, the oxide capacitance, Cox, is determined from the accumulation
capacitance. The oxide thickness can then be calculated as:
(cm) (3.6)
where KO is the oxide dielectric constant. By plotting 1/C2 versus V and taking the slope
d(1/C2)/dV, the doping concentration can be obtained from:
(cm-3) (3.7)
where q is the magnitude of electronic charge (1.602 x 10-19 C). For accurate doping
profiling it is important that the device remain in deep depletion and that the area used be
very precise due to the A2 dependence.
Four main types of charges can also be measured using the C-V method on MOS
capacitors. These charges include: the fixed oxide charge, Qf, primarily caused by defects in
the oxide assumed to be near the interface, the mobile ion charge, Qm, due to mobile ionic
impurities in the oxide, generally group 1A elements such as Na+, charges trapped in the
oxide, Qot, caused by holes or electrons trapped in the oxide bulk and finally interface
trapped charge, Qit. Interface trapped charges can be caused by structural defects, oxidation
induced defects, radiation induced defects, metal impurities and other defects. All charges
denoted by “Q” nomenclature reflect the net effective charge per unit area in C/cm2. The
effects of these charges are often studied by comparing theoretical and experimental C-V
curves. Experimental curves may be stretched out or shifted in comparison to ideal curves.
Shifts are often compared at the flat band capacitance, CFB, which is then used to determine
the corresponding flat band voltage, VFB. The flat band capacitance can be calculated as:14
(F) (3.8)
where for C to equal CFB, Cs is given by:
47
(F) (3.9)
and LD is the Debye length given by:
(cm) (3.10)
where k is Boltzmann’s constant (1.3805 x 10-23 J/K), T is the temperature in K, and p and n
are the hole and electron concentrations in cm-3. The flat band voltage can be taken as the
voltage at CFB, or can be calculated if the values of the four charge types are known. This is
given by:
(V) (3.11)
where фMS is the metal-semiconductor work function, фS is the semiconductor work function
and γ is a factor used to account for possible charge distribution throughout the oxide.
When the charge is located at the oxide-gate interface γ = 0 and when the charge is located
at the oxide-semiconductor interface γ = 1.
These analyses that result from C-V including doping profiling and the
determination
of oxide
thickness and
flat band
voltage, provide
an easy way to
compare
capacitor
samples.
Deviations from
Figure 3.8 Examples of the effect of charges on C-V curves. a) C-V
curve with no charge (a), injected charge (b) and mobile charge (c), b)
shift in C-V curves caused by injected charges, c) shift in C-V curve due
to mobile charges. 14
48
ideal can indicate the type of charges present. Fig. 3.8 illustrates this, where injected charge
and mobile charges are shown in relation to no charge C-V curves. A high density of oxide
interface traps, Dit, can also be seen in a C-V curve, where high Dit often contributes to
stretch out of the C-V curve or steps in the C-V curve.
3 .3 .2 Current – Vol tag e Measurements
By taking current-voltage (I-V) measurements on a MOS capacitor, breakdown
voltage of the oxide can be determined. The method is very similar to the C-V method in
that the gate voltage is swept and the current is measured. Gate voltage is swept positive or
negative depending on the doping of the substrate. As the gate voltage is swept and the field
increases, more carriers tunnel from the channel into the oxide. Evidence of direct tunneling,
Fowler-Nordheim tunneling and eventually avalanche can be seen and analyzed using this
method.
Taking current-voltage measurements on a MOSFET is also a useful technique. For
an n-channel MOSFET measured with respect to the source, the drain current can be
determined as a function of drain voltage, VDS, and gate voltage, VGS, by: 15
(A) (3.12)
where is the MOSFET mobility, W is the sample width (cm), L is the sample length (cm)
and VT is the threshold voltage defined by:
(V) (3.13)
where is the Fermi potential given by:
(V) (3.14)
49
where VBS= VB-VS and is the substrate voltage with respect to the source, NA is the acceptor
doping concentration (cm-3), ni is the intrinsic carrier concentration and γ is the body factor
given by:
(3.15)
This body factor is used to describe the doping charge in the space-charge region.
Due to additional scattering mechanisms, including Coulomb scattering, interface
traps and surface roughness scattering, the MOSFET channel mobility is significantly
reduced from the bulk mobility. Several component mobilities are used to characterize the
total mobility in the inversion layer of a MOSFET. These include effective mobility (μeff),
field-effect mobility (μFE) and MOS Hall mobility (μH). As the threshold voltage does not
need to be known to measure the μFE, the field effect mobility is often easier to determine
than the effective mobility. Since mobility determined through the drain conductance, i.e.
μeff, or the transconductance, i.e. μFE, does not take into account the effect of electrons
trapped in the MOS inversion layer, the MOS Hall mobility is highly desirable. The
transconductance of the MOSFET is given by:
(3.16)
solving this equation for mobility yields:
(cm2/Vsec) (3.17)
As the field effect mobility is easily calculated from a measured transconductance, it is a
popularly used mobility term for sample comparison.
50
3.3.3 Inte r f a ce Trap Densi ty Measur ements
There are several methods used to determine the density of interface traps. Two
main methods of Dit determination were used for this work. One method of extracting Dit
values involves recording simultaneous high-frequency (AC) and low-frequency (quasi-static)
CV measurements. This technique is known as the hi-lo method of Dit measurement. At
high frequencies, generally > 1MHz,
the inversion layer charges do not have
time to respond to the changing gate
voltage. Therefore the electrons do not
contribute to the capacitance. This is
the minimum capacitance (Cmin),
which corresponds to the maximum
depletion width. While this high
frequency capacitance is low for MOS
capacitors, in MOSFETs it is high due
to electrons flowing from the source
and drain regions as opposed to
generation-recombination electron
creation in the bulk.
At low frequencies, typically between 1 – 100 Hz, electrons generated in the bulk
have the time to flow across the depletion region into the inversion layer or recombine in the
substrate. Maximum capacitance (Cox) can be reached in strong inversion. In the
accumulation region of operation variation with frequency is not observed as majority
carriers in the accumulation layer can respond much faster than minority carriers. As the
definition of capacitance can be given as:
(3.18)
Figure 3.9 Sample capacitance – voltage curves
from a p-type capacitor. Both the low frequency
and high frequency curves are shown to highlight
the different behavior in the strong inversion
region.
51
The quasi-static capacitance Cq can be extracted using the displacement current as:
(3.19)
The high-frequency capacitance Ch is extracted from the amplitude of the AC signal as:
(3.20)
As can be seen in Fig 3.9, Dit is extracted from depletion region CV behavior where electron
response time yields two different curves. As the voltage is swept from accumulation to
depletion traps empty as the Fermi level at the interface crosses the corresponding energy in
the band-gap. For a given DC bias, the interface band bending is equal for Cq and Ch such
that their difference reveals the density of interface traps at this energy. For the low
frequency capacitance:
(3.21)
And for high-frequency capacitance:
(3.22)
As such:
(3.23)
The difference between the low frequency and high frequency curves can also be written as:
(3.24)
52
The corresponding trap energy value
can be calculated using Berglund’s
method.16 Limitations for this
technique are due to its dependence
on the emission time of traps.
The Gray-Brown method is
another method for determining the
interface trap density. In this method
the high frequency capacitance is
measured as a function of
temperature.17 This method can be
used to obtain Dit values closer to the
conduction band edge than by the Hi-
Lo method. Traps respond to ac probe
frequencies differently at lower
temperatures due to the interface time
constant increasing at and the Fermi
level shifting towards the conduction
band edge. Therefore at lower
temperatures traps near the band edge
should not respond, while at room
temperature they do.14
High frequency CV
measurements are recorded at various
temperatures. The flat band voltage, Vfb, is used to determine the Dit value at a given
temperature. An example of CV measurements collected using this method can be seen in
Fig 3.10. As the temperature increases and Vfb reduces, traps deeper in the band gap
respond. Results from this method can be seen in Figure 3.11. This shows Dit data collected
Figure 3.11. Dit values as determined using the
Gray-Brown method.
Figure 3.10 High frequency capacitance measurements taken as part of the Gray-Brown method.
53
for many samples over a range of trap energies. As the CV measurement temperatures
increase, band states farther away from the conduction band are probed and the calculated
Dit decreases. There are some limitations to the Gray-Brown technique for true quantitative
results. These limitations are due to the high measurement frequencies (~ 200 MHz)
required to maintain high frequency conditions near the band edges. However the method is
valuable for fast, qualitative indications of traps as well as approximate sample to sample
comparisons.
3 .4 Electr ica l Model ing
Results from electrical measurements will also be used for modeling. Capacitance-
voltage and transconductance/mobility models developed by Dr. John Hauser at North
Carolina State University were used for the modeling. Parameters extracted from the models
provided additional data for comparison. Materials files and modeling options are reviewed
in Appendix C.
3.4.1 Capac i tors
Experimental
capacitance-voltage data was
modeled using the Hauser
CVC modeling program.
Measured capacitance and
voltage data is used to create
an ideal fit. Examples of
experimental and fitted data
are shown below in Fig 3.12. Figure 3.12 Experimental and modeled data for an n-
type capacitor.
54
This figure illustrates the difficulty encountered in fitting the modeled data to the
experimental data in the accumulation region. Device parameters are then calculated from
the fitted data. These parameters include equivalent oxide thickness, flat band voltage,
threshold voltage, oxide charge, surface and bulk doping, Debye length and various
capacitance values. The quality of the extracted parameters are closely linked to the quality of
the model fit, such that poor fits often result in parameter values with increased potential
error.
3.4.2 MOSFETs
Extracted parameters from the modeled capacitance-voltage data are combined with
experimental Id-Vg data to model the transconductance and mobility using the Hauser
SiC_Mob2d modeling program. Modeling options for this program are also reviewed in
Appendix B, however no materials files are used, as this program is specifically optimized for
SiC. An important feature of this optimized model is the ability to fit the data for a specified
value of interface state density. This allow for comparison between samples of Dit values
derived from the model.
Fig 3.13 Experimental data for nitrided thermal oxide compared to calculated data and data modeled with varying interface state densities. Left: Across all measured gate voltages Right: Low voltage region used to obtain the most accurate fit.
55
Experimental data and modeled data values with different interface state densities are
shown in Fig 3.13. The effect of varying interface state densities is also shown. Spread in the
calculated data is a result of the measurement resolution. Dit values from 1E12 up to 2E13
appear to have good correlation with the experimental data at gate voltages greater than 5
volts. Figure 3.13 also shows an additional plot on the left of this data focusing on the turn-
on region. In this plot is it more clearly shown that the experimental data falls between the
data modeled with a Dit value of 1E13 and 5E12, suggesting a Dit of around 7.5E12. Dit
values of 7.5E12 to 8.5E12 provided the most accurate fit for all samples modeled in this
work.
3 .5 Sample Fabricat ion
3.5.1 Capac i tors
All sample devices were fabricated at Cree, Inc in RTP, NC. Capacitors were
fabricated on both silicon and 4H-SiC substrates off-cut 4o from the (0001) Si-face vicinal
surface. After incoming cleans including a sacrificial oxidation, a gate oxide was formed
in one of two ways either through ALD deposition of SiO2 at 150°C or through a
thermal oxidation process. The thermal oxidation process consists of an O2 oxidation at
1175°C with time dependent on required thickness, followed by an 1175°C 30 minute Ar
anneal and finally a 3 hour wet O2 anneal at 950°C. Both gate processes were concluded
with a 2 hour nitric oxide (NO) anneal at 1175°C. These high temperature oxidation
processes are summarized below in Table 3.1. A boron-doped polysilicon pattern was
used as a gate contact. Aluminum was used as needed to provide a lower resistance gate
contact for electrical measurements.
56
3.5.2 Latera l MOSFET Stru c ture s
Lateral MOSFETs were also
fabricated on p-type epi grown on 4H-SiC
substrates off-cut 4o from the (0001) Si-
face vicinal surface. Following an
incoming sacrificial oxidation, N+ regions
were formed using phosphorus implants.
All wafer then had implants activated at
1650C for 30 minutes with a graphite
cap for all wafers. The varying high
temperature oxidation procedures are
outlined below in Table 3.1. A polysilicon
gate was patterned from blanket
polysilicon and metal contacts were deposited. Nickel ohmic contacts were annealed at
825C after deposition only as needed. The cross section of the lateral MOSFETs is
shown above in Fig. 3.14.
Table 3.1 Processing parameters for high temperature oxidation recipes.
Oxidation Type Temperature Ambient Time
Sacrifical Oxidation
1200 ˚C Dry O2 Varies
Nitrided Thermal 1175 ˚C Dry O2 Varies
1175 ˚C Ar 30 min
950 ˚C Wet O2 180 min
1175 ˚C NO 120 min
Thermal 1175 ˚C Dry O2 Varies
1175 ˚C Ar 30 min
950 ˚C Wet O2 180 min
NO Anneal 1175 ˚C NO 120 min
Figure 3.14 Cross – section of typical n-
channel lateral MOSFET used for this
research.
57
An example sample piece and 5x microscopic image of a 400µm x 400µm lateral
MOSFET are show in Figure 3.15. The mask set used consisted of several different
devices including circular FETs, capacitors, and lateral MOSFETs aligned parallel to and
perpendicular to the wafer major flat.
3 .6 STEM Lamella Fabricat ion
3.6.1 Focused Ion Beam Mil l ing
Focused ion beam (FIB) milling is a popular TEM sample preparation technique. In
a FIB a primary ion beam, generally gallium, is focused onto the sample surface resulting is
sputtering of the sample material. At low beam currents, small amount of material are
sputtered and the sputtered ions or secondary electrons can be used for imaging. At high
beam currents, large amounts of sample material are removed providing the precision
shaping of the sample. The FIB can also be used to deposit materials, commonly carbon,
platinum or tungsten, in specific patterns onto a sample. The disadvantages of using FIB
milling for TEM sample preparation are related to sample damage from the gallium beam.
Figure 3.15 Left: sample die showing the device patterns. Right: 5x microscopic view
showing circular FETs as well as the gated lateral MOSFET used for this research.
58
As such, very low beam currents should be used to clean the sample surface when preparing
TEM lamella to reduce the effects of gallium beam damage.
3 .6 .2 Lamel la Preparat ion
The NB-5000 was used to prepare TEM samples. Samples were prepared from the
square gate areas seen in Fig. 3.15. After the FIB was aligned and the sample set at eucentric
height, the sample area was determined and a carbon rectangle was deposited to protect the
surface. Then a tungsten rectangle was subsequently deposited and the area surrounding the
rectangle was rough milled using a 40kV beam accelerating voltage. This can be seen in Fig.
3.16 which shows 2 sample preparation areas. The leftmost milled area still has the sample
lamella in the center of the milled area, while in the right region, the lamella has already been
lifted out. Once the lamella is rough milled a liftout needle is attached to the top and the
bottom of the section is cut. The free lamella is lifted from the sample and then attached to a
special TEM probe grid.
Figure 3.16 View of the TEM lamella preparation before lifting out of the lateral
MOSFET sample.
59
The rough lamella attached to a copper grid can be seen in Fig. 3.17a. After attaching to the
grid the lamella is polished using sequentially lower beam currents and finally lower
accelerating voltages to reduce beam damage to the sample. Image b of Fig 3.17 shows a
final TEM lamella. Another polishing job can be seen in part c of the figure, where the
thinnest areas are lighter in color. It is also clear in the center of part c that the tungsten and
carbon have been consumed and polysilicon layer had been compromised. This could lead to
damage of the oxide and confuse results at the interface in this region. Section d shows a
top view of the prepared TEM lamella. For the initial sample preparation sample thickness
ranged from 25nm to 50nm. Subsequent samples prepared aimed for a thickness of 50nm to
reduce the possibility of energetic damage from the gallium beam. While tilting and looking
top down at the sample is the only way to judge lamella thickness during preparation, it is
not the best
way. This is
because only
the top layer
thickness can
be judged by
looking top
down. Areas
closer to the
interface
could be
thinner or
thicker,
making it very
difficult to
determine the
thickness of
Figure 3.17 The stages of TEM lamella sample preparation using the FIB
a) pre-polish lamella attached to grid, b-c) polished lamella, and d) top
down view of lamella.
60
your sampling region during preparation.
A portion of samples made were also cleaned using a Nanomill tool available at Oak
Ridge National Labs, before running in the STEM. The Nanomill is a tool made by
Fischione specifically for post-FIB TEM sample preparation. The tool provides milling at
energies as low as 50eV, allowing for extremely gentle cleans of the sample surface. Samples
were milled for 10-20 minutes at positive 10° tilt and then for another 10-20 minutes at
negative 10° tilt. While the Nanomill is the best option for post-FIB cleans of the sample
surface, it can also cause addition problems such as copper redeposition on the sample from
milling of the copper lamella support if the beam is not well positioned on the sample.
Copper redeposition from the lamella support frames is normally seen on samples as cloud-
like areas on the sample. As these areas are very visible, when spotted they are easily avoided
when choosing areas and positioning for EELS characterization. However to avoid
unnecessary problems due to this redeposition, the Nanomill was removed from the sample
preparation procedure after the first set of samples.
61
3.7 References
1. Suntola, T. and Antson, J., US Patent 4.058, 430, 1977.
2. Suntola, T. Handbook of Thin Film Process Technology B.1.5, Glocker, D.A., ed.
(IOP, 1995).
3. Brundle, C. R., Evans, C.A., and Wilson, S.: Encyclopedia of Materials
Characterization (Butterworth – Heinemann, Boston 1992).
4. D.B. Williams and C. B. Carter: Transmission Electron Microscopy (Plenum Press,
New York 1996).
5. R.J. Keyse, A.J. Garratt-Reed, R.J. Goodhew, and G.W. Lorimer: Introduction to
Scanning Transmission Electron Microscopy (Springer, New York 1998).
6. B. Fultz and J. M. Howe: Transmission Electron Microscopy and Diffractometry of
Materials (Springer, New York 2008).
7. O. Scherzer, Journal Applied Physics 20, 20 (1949).
8. O. L Krivanek, P. D. Nellist, N. Dellby, M. F. Murfitt, and Z. Szilagyi, Ultramicroscopy
96, 229 (2003).
9. A. Y. Borisevich, A. R. Lupini, and S. J. Pennycook, Proceedings of the National Academy
of Sciences 103, 9 (2006).
10. P. E. Barston, N. Delby and O.L Krivanek, Nature 418 (2002).
11. P.D. Nellist, M.F. Chisholm, A. R. Lupini, A. Borisevich, W. H Sides, S. J.
Pennycook, N. Delby, R. Keyse, O. L. Krivanek, M. F. Murfitt and Z. S. Szilagyi,
Journal of Physics, 26 (2006).
12. DigitalMicrograph EELS Anaylsis User’s Guide, Published by Gatan, Inc., 1.2.1
(2003).
13. R.F. Egerton, Electron Energy-Loss Spectroscopy in the Electron Microscope
(Plenum Press, New York 1996).
14. D. Schroder, Semiconductor Material and Device Characterization (Wiley, New
York, 2006).
15. S. M. Sze, Semiconductor Devices, Physics and Technology (Wiley, New York 1981).
62
16. C. N. Berglund, IEEE Transactions on Electron Devices 13, 701 (1966).
17. P.V. Gray and D.M. Brown, Applied Physics Letters 8, 2 (1966).
63
C H A P T E R 4
ALD OF SiO 2 RESULTS AND DISCUSSION
4.1 Development of ALD Process
Low temperature atomic layer deposition (ALD), also known as atomic layer epitaxy,
provides an attractive means of depositing silicon dioxide (SiO2) for SiC MOS devices.
For the initial process development, silicon substrates were used. An initial run examined
the importance of the pre-deposition surface clean, results are shown below. For all other
runs the substrates were either cleaned with a standard RCA bath clean, followed by
buffered oxide etch (BOE) or solely with BOE immediately before being loaded into the
ALD chamber. A Cambridge Nanotech Savannah tool was used for all ALD work. The
SiO2 was deposited in a 3 step process using 3-aminopropyltriethoxysilane,
H2N(CH2)3Si(OEt)3, (heated
to 100°C), water,
H2O,(60°C) and ozone,O3,
(~10% in O2).1 The
proposed sequence for this
reaction is illustrated in
Figure 4.1 and begins with
exposure of an –OH
terminated surface to the 3-
aminopropyltriethoxysilane
(3-APTES). These surface
hydroxyls break the Si-OEt
allowing for chemisorption
of the Si on the substrate
surface, step (a). In step (b)
Figure 4.1.Proposed 3 step sequence for atomic layer
deposition of SiO2 using water, ozone and 3-APTES.1
64
water is pulsed to remove remaining ethoxy groups from the chemisorbed Si. Finally ozone
is pulsed to remove the remaining amino alkyl arm and the –OH terminated surface is ready
for the process to repeat, steps (c) and (d). The process time for one complete cycle of this
process in the Savannah tool is approximately 50 seconds, with a deposition rate of
0.67Å/cycle. The chamber temperature is held at 150 ºC with the additional process
parameters shown below in Table 4.1.
Table 4.1 Process parameters for SiO2 ALD recipe
Precursor Temperature
(ºC)
Pulse Time
(sec)
Exposure
Time (sec)
Pump Time
(sec)
3-APTES 100 0.1 28 18
Water 28 1 7 18
Ozone 28 0.2 7 13
All deposition
runs began with
30 ozone pulse
cycles to purge
the ozone line of
any decomposed
ozone. A plot of
the chamber
pressure versus
time for these an
ozone purge
sequence can be
seen in Fig 4.2.
Chamber pressure Figure 4.2 Plot illustrating the 30 pulse ozone line purge sequence
65
over time for a deposition run is shown in Fig 4.3. The three pulses of 3-APTES, water and
ozone can each be observed in this plot. It is important to monitor the base pressure
between pulses to ensure that the pump time is sufficient, allowing all excess precursor to
be pumped from the process chamber before the next precursor is pulsed.Initial blanket
deposition runs were characterized with ellipsometry to determine the deposition rate.
Ellipsometry data for thickness variation and index of refraction from initial runs on silicon
substrates are shown in Figs 4.4 and 4.5. These figures illustrate variation across one half
of a 4 inch silicon
monitor wafer
run for 250
cycles. Good
uniformity for
both the
thickness and
index of
refraction were
observed. The
index of
refraction
measured is
slightly higher
than the standard
value of 1.46,
most likely due to non-ideality of the as deposited ALD SiO2. Improvement of this
parameter through post deposition anneals was anticipated. The ellipsometry data was taken
over 40 cycles at 65°. Figures 4.6 and 4.7 shows the experimental data and model fit for the
psi and delta as a function of the wavelength. Good correlation between the experimental
and model data was observed. XPS was also used to evaluate the quality of the
Figure 4.3 Plot illustrating the beginning of a standard SiO2
deposition run. The initial 30 pulses of ozone are shown, followed by
the 3-APTES, water and ozone pulse sequences.
66
Figure 4.4 Measured “as deposited” ALD SiO2 thickness variation across half of a 3” wafer.
Figure 4.5 Variation in refractive index for the “as deposited” ALD SiO2.
Index@632nm
Mean = 1.4783Min = 1.4627Max = 1.4904Std Dev = 0.0066175Uniformity = 0.44766 %
1.49041.48581.48121.47651.47191.46731.4627
PECVD SiO in Å
Mean = 125.01Min = 117.62Max = 136.24Std Dev = 5.0301Uniformity = 4.0239 %
136.2133.1130.0126.9123.8120.7117.6
67
Figure 4.7 Plot of Δ as a function of wavelength for ALD SiO2 deposited on silicon.
Figure 4.6 Plot of ψ as a function of wavelength for ALD SiO2 deposited on silicon.
Generated and Experimental
Wavelength (nm)
0 300 600 900 1200 1500 1800
in
de
gre
es
10
15
20
25
30
35
40
Model Fit Exp E 65°
Generated and Experimental
Wavelength (nm)
0 300 600 900 1200 1500 1800
in
de
gre
es
80
100
120
140
160
180
Model Fit Exp E 65°
68
deposited SiO2. These XPS results can be seen below in Fig 4.8 which shows XPS of the as
deposited SiO2 film. The high carbon concentration in this data indicates high surface
carbon content as well as carbon incorporation in the ALD film. This suggests the need for
post deposition annealing/densification. Figure 4.9 illustrates additional XPS data from a
thick SiO2 film, showing in detail the oxygen 1s and silicon 2p peaks.Following this initial
characterization, the appropriate surface clean for silicon substrates was evaluated before
capacitors were fabricated on Si.
Figure 4.8 Summary spectrum for “as deposited” ALD SiO2 with Si 2p, O 1s and C 1s
peaks reviewed.
69
Analysis of these ellipsometer and XPS results revealed a stable SiO2 deposition recipe. The
O1s spectrum shown in Fig 4.9 exhibits oxygen predominant peak at 532.7eV and smaller
peak at 533.5 eV.2 These peaks have been attributed to SiO2 and various silicon oxycarbide
species, respectively. The silicon oxycarbide species of Si2C4-xO2 and Si4C4O4are related to
carbon present in the unannealed low temperature deposited oxide as well as adventitious
carbon at the sample surface.It is also important to note that there is no evidence of an H2O
peak at 536 eV due to unreacted precursor. The Si2p spectrum is presented in Fig 4.9. A
clear SiO2 electron binding energy was measured at 103.5 eV. A small shoulder peak was
seen at 102.4 eV, which has been attributed to SiO3C.3 Following this initial materials
characterization, capacitors were fabricated to evaluate the electrical properties of the
dielectric.
Figure 4.9 O 1s(left) and Si 2p (right) spectrum for as deposited ALD SiO2 with peak
fitting.
70
4.2 Capacitor Results on Si l icon
Capacitors were fabricated on silicon substrates following the fabrication process
outlined in Chapter 3. To summarize, ALD SiO2 was deposited silicon wafers after a BOE
clean. The targeted thickness was 200Å , with approximately 214Å achieved. Platinum metal
gates were deposited for form the capacitor structure. Subsequent lots were not processed
using platinum metal, as spiking of the platinum through the gate oxide was seen after
anneal at temperatures of 450 °C and above.
Two surface cleans of the silicon surface prior to ALD treatment were investigated.
ALD deposition is very sensitive to surface cleans as the reaction sequence is dependent on
the surface termination. The cleans used for this initial investigation were 5 minutes in
buffered oxide etch (BOE) or 5 minutes in a 10:1 aqueous solution of hydrofluoric acid (HF)
and were compared to an uncleaned (native oxide terminated) surface. The samples were
processed together for 250 cycles of the SiO2ALD recipe.
4.2.1 Ell ipsometr y
Ellipsometry results for the thickness and index of refraction are summarized below
in Table 4.2. This data indicates a native oxide layer of 14 - 20Å on the silicon substrate that
did not receive a pre-deposition clean.
Table 4.2 Ellipsometry data for different surface cleans for ALD SiO2 on silicon.
Clean Thickness (Å) Index of Refraction (n(λ))
No clean 161.51 +/- 0.13 1.462
HF 145.85 +/- 0.159 1.4601
BOE 143.44 +/- 0.158 1.4577
71
This value is consistent with previously published values of 20Å +/- 3Å of native oxide on a
silicon substrate.4 The index of refraction measured for all samples run is close to the ideal
value of 1.46.5
4.2.2 Capac i tance – Vol tage Measur ements
Additional capacitors were fabricated in silicon to look at the electrical quality of the
ALD SiO2. Capacitors were fabricated using the BOE and HF cleans before the ALD SiO2.
A control capacitor was also fabricated by growing thermal SiO2. The capacitance – voltage
measurements from this series are shown below in Fig 4.10. The capacitance shown is the
high frequency capacitance divided by the oxide capacitance. This allows for easy
comparison between capacitors with varying oxide thicknesses. Thickness of the ALD
samples is
described in
table 4.2 and the
thermal oxide
was measure to
be
approximately
30nm thick.
The two
C-V curves for
the ALD oxides
show greater
stretch-out
compared to the
thermal oxide.
Figure 4.10 Normalized capacitance-voltage measurements comparing
pre-deposition cleans for ALD SiO2 deposited on silicon.
ν = 100 kHz
72
This is indicative of a higher density of interface states, which is not surprising due to the
non-ideal structure associated with low temperature deposited films. The BOE cleaning
method yielded a more ideal curve with less stretch-out than the HF clean. As such
subsequent runs on silicon substrates were run with the BOE clean.
4 .3 Conclusions
Initial results for the 3 step 3-APTES, water and ozone ALD SiO2 process on silicon
are presented in this chapter. XPS and ellipsometry results indicate a stable, repeatable
process for SiO2 deposition at a low chamber temperature of 150 ˚C. Improved
capacitance-voltage curves were seen for the BOE cleaned substrate compared to the HF
clean. These encouraging results on silicon support continued development of the ALD
SiO2 on SiC.
73
4.4 References
1. J. Bachmann, R. Zierold, Y. T. Chong, R. Hauet, C. Sturm, R. Schmidt-Grund, B.
Rheinlander, M. Grundmann, U. Gosele, and K. Nielsch, Angewandte Chemie
International Ed. 47, 33 (2008).
2. B. Hornetz, H-J. Michel and J. Halbritter, Journal of Materials Research 9, 12 (1994).
3. Anna Onneby, Ph.D. Thesis, The Pennsylvania State University, 1997.
4. M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, M. Ohwada, Journal of Applied
Physics 68, 3 (1990).
5. H.G. Tompkins and W. A. McGahan, Spectroscopic Ellipsometry and Reflectometry
(John Wiley and Sons, New York 1999).
74
C H A P T E R 5
CAPACITORS ON SIC RE SULTS AND DISCUSSIONS
5.1 Optimizat ion of the Process on SiC
After reviewing the good electrical data from the capacitors fabricated on silicon,
preliminary work was begun for fabrication on SiC. As the ALD process is exceptionally
dependent on the substrate surface termination, work on SiC substrates also began with an
investigation of the influence of surface cleans.
5.1.1 Effec t o f Pr e -depos i t i on Sur fa ce Cleans
As with the capacitors fabricated on silicon, the effect of surface clean was also
examined before fabricating capacitors on SiC substrates. HF and BOE pre-deposition
cleans for 5 minutes were examined and compared to a native oxide. Previous investigation
of the termination of the SiC
surface has shown that the
surfaces are –OH
terminated, as compared to
the pure hydrogen
termination of silicon.1
Dhar et al. also showed that
the activation energies for
removal of the –OH from
the surface of both the C-
and Si-face of SiC are much
higher than for silicon.
Figure 5.1 illustrates this
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
R RC TS PC P
Reaction Coordinate
Re
l. E
nerg
y (
eV
)
HO/Si
HO/Si-SiC
HO/C-SiC
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
R RC TS PC P
Reaction Coordinate
Re
l. E
nerg
y (
eV
)
HO/Si
HO/Si-SiC
HO/C-SiC
+ +
Figure 5.1 Relative activation energies for –OH removal
from silicon surfaces, Si-face SiC surface and C-face SiC
surfaces. 1
75
difference in activation energies. As the SiO2 ALD recipe used depends on removal of the
surface terminating –OH bonds to begin the deposition sequence, the higher activation
energy for the Si-face of SiC is notable.
Single point ellipsometry data was used to compare the effect of the surface cleans,
due to the small size of the samples. Data was taken while varying the angle from 60 - 75º.
Thickness and means-squared error (MSE) results are shown in Table 4.3.
Table 5.1 Ellipsometry data for different surface cleans for ALD SiO2 on SiC.
Clean Thickness (Å) MSE
No clean 160.66 +/- 0.143 5.012
HF 153.83 +/- 0.122 4.387
BOE 153.30 +/- 0.103 3.631
The MSE reported is a merit value used to describe the quality of match between the
measured and calculated data. The plots of the calculated and experimental ψ and Δ as a
function of wavelength are shown in Fig 5.2 for both the BOE and HF cleans. While the fit
appears to be close for both data sets, it is clear from the MSE value that the fit is better,
and thus more ideal, for the BOE cleaned surface. As such subsequent ALD runs on SiC
substrates included a final 5 minute BOE clean before loading into the ALD chamber.
76
5.1.2 Effec t o f Post -depos i t i on Forming Gas Annea l
The benefits of a post deposition anneal (PDA) for ALD films are well understood
and widely accepted.2,3,4,5 The low deposition temperatures and high carbon content in most
ALD films necessitate a post-deposition anneal to optimize the stoichiometry and reduce the
leakage current through the film. As such the effects of a PDA in a forming gas ambient on
ALD SiO2 on SiC were investigated. Anneals were performed in a rapid thermal anneal
system in forming gas for 5 minutes at 450 °C, 500 °C and 650 °C. C-V measurements for
the as deposited condition and the 3 anneal temperatures are shown below in Fig 5.3.
Figure 5.2 Plots of ψ and Δ for the BOE and HF cleans. BOE data is shown in a) and
c), while HF data is presented in b) and d).
77
The forming gas appeared to have little to no effect on stretch-out and therefore interface
states. The benefits of the hydrogen passivation exhibited by the Si/SiO2 system were not
evident for these samples. It was also noted that the flatband voltage initially shifted ~5V
positive and then reduced for additional higher temperature anneals. This could be due to
residual stresses from partial densification of the film or from unwanted carbon compounds
that were not annealed out. Further investigation of anneals at temperatures over 650 °C was
implied by the data trends. However this was not possible with the existing devices, as the Pt
gate metal was seen to spike through the oxide at anneal temperatures above 650 °C,
shorting the devices.
Figure 5.3 Capacitance-voltage measurements for ALD SiO2 capacitors on SiC after
varying forming gas anneals.
ν = 100 kHz area = 0.00196 cm
2
ave thickness = 30nm
78
5.1.3 Effec t o f Post -depos i t i on NO Annea l
Results from the forming gas anneal study and pre-deposition clean investigation
suggests that the ALD SiO2 on SiC suffers from a high amount of interface states and high
flatband voltage. Advantages of higher temperature anneals were also indicated by the post-
deposition anneal study. As such capacitors were fabricated to compare the effect of high
temperature nitric oxide anneals on ALD SiO2. The positive effects of PDA in NO ambient
on thermally grown oxide were reviewed in Chapter 2. Fabrication of the devices was
identical to previous capacitors but a 2 hour anneal in NO was performed at 950, 1050 and
1175 ˚C after the ALD SiO2 deposition. The NO anneal was run in a combined furnace
step with the thermal oxidation. An additional ALD SiO2 sample was fabricated that did not
undergo the NO anneal but instead received a 1 minute 600 ˚C PDA in nitrogen. High
frequency C-V measurements from the capacitors are shown below in Fig. 5.4.
Figure 5.4 Normalized capacitance-voltage measurements comparing ALD SiO2 with
varied NO anneal temperatures to ALD with 600˚C N2 post deposition anneal.
ν = 100 kHz area = 0.00126 cm
2
ave thickness = 45nm
79
The results showed a remarkable improvement in the ALD SiO2 capacitors that received the
highest temperature NO anneal with CV curve behavior much closer to ideal. Additional
capacitors were fabricated to compare the 1175 ˚C NO annealed ALD oxide to 1175 ˚C NO
annealed thermal oxide as well as unannealed thermal and ALD oxide. Capacitor –voltage
data from these additional capacitors is shown in Fig 5.6. It is clear from the figure that the
ALD+NO process data was nearly identical to the thermal oxide + NO, differing only by
exhibiting a slightly more negative flatband voltage. The control, unannealed ALD SiO2
capacitor is also shown in Fig 5.5 and exhibits significant stretch-out, as well as high Vfb. Dit
was calculated for these capacitors using the hilo method described in Chapter 3. Figure 5.6
shows the Dit as a function of the trap energy distance from the conduction band. Similarly
to the C-V results shown above, the Dit from ALD+NO is equivalent to Dit measured from
the thermal oxidation + NO process. Both of these capacitors exhibited significantly lower
Dit than the unannealed thermal oxide capacitor.
Figure 5.5 Normalized capacitance-voltage measurements comparing various anneal
treatments for ALD and thermal oxides. (* as deposited ALD values given in Fig 5.3)
ν = 100 kHz area* = 0.00126 cm
2
ave thickness* = 20nm
80
In addition to measuring C-V and Dit from the capacitors, the oxide breakdown of the
ALD+NO capacitor was also probed. Current density as a function of field for both the
nitrided ALD and nitrided thermal oxide is shown below in Fig 5.7. Differences in low field
current densities are due to limitation of testing equipment. As seen in the figure, Fowler
Nordheim tunneling is seen for both samples starting around 6 MV/cm. The nitrided ALD
sample entered the breakdown regime at around 7.5 MV/cm. The nitrided thermal oxide
did not breakdown till fields exceeded 11.5 MV/com.
Figure 5.6 Density of interface traps (calculated from hilo CV) as a function of trap
energy distance from the conduction band for NO annealed ALD SiO2 and thermal
oxides with and without NO anneal.
81
5.1.4 Elec t r i ca l Mode l ing
Data from the capacitors fabricated to examine the effects of PDA in nitric oxide
was used to model CV behavior. A popular CV modeling program developed by Dr.
Hauser at North Carolina State University was used for modeling the CV data, as discussed
in Chapter 3. Experimental data for several capacitors was modeled following the reviewed
procedures. A table of the parameters extracted from the model is shown in Table 5.2. The
fit of the modeled data is listed in the bottom row and is best for the nitrided ALD sample
and worst for the nitrided thermal oxide sample. The CV modeling programs appeared to
Figure 5.7 Breakdown of an NO annealed ALD SiO2 compared to nitrided thermal
oxide on 4H-SiC.
82
have difficulty accurately modeling the accumulation region of all of the curves. The
difficulty in fitting the nitrided thermal data is also clearly seen in the tabled data as values
for some parameter such as the Debye length, LD, are out of family compared to the
nitrided ALD and thermal extracted data.
Table 5.2 Extracted parameters from capacitance-voltage modeling
Parameter Nitrided Thermal
Thermal Nitrided ALD
600˚C N2 PDA ALD
ALD as deposited
EOT 14.507 18.614 14.961 24.761 18.538
Vfb 0.355 1.723 -0.281 4.276 7.760
Vt -7.899 -2.123 -3.660 -0.948 3.304
VtQm -7.751 -2.104 -3.648 -0.915 3.335
PhiB 1.385 1.385 1.396 1.448 1.386
Q 1.96E+12 7.35E+11 2.37E+12 -5.33E+11 -2.78E+12
NdSurf 5.37E+17 1.28E+16 5.79E+15 3.24E+16 3.15E+16
NdBulk 2.53E+15 2.53E+15 3.88E+15 2.89E+16 2.69E+15
Cfb 137.26 -1901.84 86.33 74.27 6.00E+08
Cox 149.56 116.56 145.02 87.63 182.88
Cdep 9.31 9.16 11.30 23.90 14.70
Ld 5.08 32.90 48.92 20.68 20.97
RMS 65.08 8.69 4.19 3.37 16.94
Fit Error 22.00% 14.70% 5.60% 6.60% 17.40%
5 .2 Materia l s Characterizat ion of the ALD SiO 2/SiC Interface
5.2.1 XPS Resu l t s
Before fabricating MOSFETs with the NO annealed ALD SiO2 process, additional
materials characterization work was completed. XPS was used to investigate the deposited
and annealed SiO2/SiC interface as compared to a thermally grown sample. A survey scan of
the ALD+NO oxide on SiC is shown below in Fig 5.8. The peak positions, full width half
maximum, and atomic percent are all listed in the figure. The atomic percentages reported
are for the entire interaction volume and therefore are representative of the oxide and
83
substrate. As such these values cannot be used to determine atomic percentage in the oxide
or substrate separately. The Si 2p spectrum for ALD SiO2 on SiC is shown in Fig 5.9. Three
deconvoluted peaks located at 100.7, 103.8 and 101.2 have been attributed to Si-C, Si-O and
Si-O-C respectively.6,7 The 101.2 eV electron binding energy is indicative of Si bound to one
oxygen and has been correlated to the presence of Si +1, including Si4C4O4, =Si-O-Si= and
Si4C4-xO2.6 Fig 5.10 illustrates the O1s spectrum which consists of a single peak at 533.4 eV.
This electron binding energy is consistent reported values for SiO2. The deconvoluted C1s
spectrum and peak modeling is shown in Fig 5.11. Three peaks were identified, at 283.0 eV,
284.5 eV and 286.9 eV. The core level binding energy of 283.0 eV falls within the range of
282.4 – 283.4 eV used to describe SiC.6,8 Silicon oxycarbides and other interfacial
carbonaceous species have been attributed to the 284.5 eV, while C-O and C-OH bonding
are supported by the 286.9 eV peak. CO dissolved into the SiO2 as identified by a C1s core
level energy above 290 eV was not seen in any of the samples analyzed. These XPS results
show good agreement with previously published results for SiO2, which suggests a good
quality SiO2 is achievable with the low temperature ALD process.
84
Figure 5.8 Survey spectrum of NO annealed ALD SiO2 on SiC. N 1s peak is
indicative of nitrogen bonding.
300600900
Binding Energy (eV)
0
85
Figure 5.9 Silicon 2p spectrum and peak fitting for unannealed ALD SiO2.
86
Figure 5.10 Oxygen 1s spectrum and peak fitting for unannealed ALD SiO2.
87
Figure 5.11 Carbon 1s spectrum and peak fitting for unannealed ALD SiO2.
88
5.2.2 STEM/EELS Resu l t s
STEM and EELS techniques were also used to investigate the NO annealed ALD
SiO2 on 4H-SiC. Previous studies of thermally grown and annealed oxide on SiC have shown
transition regions on both sides of the interface as discussed in Chapter 2. A small number
of studies have also seen elevated amount of carbon on the SiC side of the interface.9,10 Fig
5.12 shows bright field and high-angle annular dark field STEM images from a fabricated
capacitor sample. The interface structure appears very similar to previously studied thermally
oxidized samples. The darker interface region exhibited in the bright field image likely
denotes interfacial strain between the crystalline 4H-SiC and the amorphous SiO2. Both
images indicate good crystallinity in the bulk of the SiC, with a slight reduction in crystalline
quality near the interface suggested. EELS data from this sample and the complementary Z-
contrast image showing the samples area are shown in Fig 4.23. The EELS data shows a
good Si:C ratio for the SiC bulk. At the interface the carbon begins to drop accordant to the
rising oxygen. A transition region, denoted by the yellow lines in Fig 5.13, of approximately
2.5 – 3 nm was witnessed on both sides of the interface. The carbon rich composition
Figure 5.12 Bright field (left) and HAADF (right) images of an NO anneal ALD SiO2
on 4H-SiC.
89
previously reported on the SiC side of the interface was not seen, with carbon appearing to
linearly decrease across the interface.
Additional EELS relative composition data, intensity profile for the bright field
image and the corresponding bright field image are shown in Fig 5.14. It is more difficult to
interpret the bright field image as it does not show the interface as clearly. As such the
intensity profile for this image is included to clearly show where the sample contrast
changes. These areas correlate well with the relative composition plot and suggest a total
transition region of approximately 5 nm with about 2.5 nms of transition on either side of
the interface. These values show good agreement with the values determined from Fig 5.13.
Figure 5.13 Relative composition across the SiC/SiO2 interface determined through
EELS and the corresponding Z-contrast image showing the sample area.
90
5 .3 Conclusions
Encouraging results on low temperature atomic layer deposited SiO2 on 4H-SiC were
presented in this chapter. Fabrication of capacitors utilizing ALD SiO2 deposited on 4H-SiC
was successfully demonstrated. Electrical characterization of these capacitors revealed good
behavior after anneal of the ALD oxide for 2 hours in nitric oxide at 1175 ˚C. After this NO
anneal, the performance of the ALD oxides was equivalent to thermally grown oxides with
flat band voltages approximately equal to 0V. Dit calculation also revealed equivalence
between these samples with both in the range of 1E+12 to 1E+11 cm-2eV-1 from 0.2 to 0.6
eV from the conduction band. Ellipsometry, XPS and STEM/EELS analysis were all
Figure 5.14 Relative composition across the SiC/SiO2 interface determined through
EELS, the corresponding BF image and intensity profile of the image.
91
employed as materials characterization techniques to evaluate the ALD oxide. All results
indicate a good quality SiO2 with a refractive index of 1.458 and XPS core level binding
energies well correlated to previous published values for SiO2. STEM and EELS results
support a good interface between the SiC and SiO2. Transition regions were discovered on
both sides of the interface with similar thicknesses to those reported on thermally grown,
NO annealed oxides suggesting further investigation into the relationship between transition
region thickness and oxidation. As a result of these encouraging results fabrication of lateral
MOSFETs with an ALD SiO2 gate dielectric commenced.
92
5.4 References
1. S. Dhar, O. Seitz, M. D. Halls,S. Choi, Y. J. Chabal and L.C.Feldman, J. Am. Chem.
Soc., 46, 131 (2009).
2. H. Zhou, G. I. Ng, Z. H. Liu, and S. Arulkumaran, App Phys Exp 4, 104102 (2011).
3. L. Zhang, H.C. Jiang, C. Liu, J.W. Dong and P. Chow, J of App Phys D 40, 12
(2007).
4. Y.C. Cheng, App Surf Sci 258, 1 (2011).
5. J. Harjuoja, A. Kosola, M. Putkonen and L. Niinisto, Thin Solid Films 496 (2006).
6. B. Hornetz, H-J. Michel and J. Halbritter, Journal of Materials Research 9, 12 (1994).
7. Anna Onneby, Ph.D. Thesis, The Pennsylvania State University, 1997.
8. V. Schier, H-J. Michel and J. Halbritter, Fresenius Journal Analytical Chemistry 346
(1993).
9. Trinity Biggerstaff, Ph.D. Thesis, North Carolina State University, 2008.
10. T. Zheleva, A. Lelis, G. Duscher, F. Liu, I. Levin and M. Das, Applied Physics Letters
93,022108 (2008).
93
C H A P T E R 6
STEM/EELS INVESTIGAT IONS OF THE SIC/SIO 2 INTERFACE
6.1 Invest igat ion of Miscut Effects on Thermal Oxidation
The miscut angles of 2, 4, and 8 degrees offcut from the Si-vicinal face were
examined to probe proposed theories relating transition region thickness to peak field effect
mobility. Previous studies have linked oxidation rates on both the Si-face and C-face to
carbon surface concentration.1 As the offcut angle is directly related to the amount of carbon
that is available at the surface during thermal oxidation, than if transition region thickness is
truly related to carbon content one would expect a thicker transition region on a an 8 degree
offcut sample than on the 2 degree offcut. An atomic illustration of the miscut is shown
below in Fig 6.1. The atomic steps are highlighted by arrows pointing to each step. From this
it is clear that the 8 degree offcut surface will supply more carbon during thermal oxidation
Figure 6.1 Offcut angles of 2,4, and 8 degrees illustrated using STEM HAADF images
and Si-C tetrahedrons.
94
than the 4 and 2
degree offcut
surfaces.
Lateral
MOSFETs were
fabricated on the Si-
face of 4H-SiC
using the process
outlined in Chapter
3. All wafers
received the
standard thermal
gate oxidation
process followed by
a 2 hour anneal in
nitric oxide at 1175°C. The only difference was the offcut angle for each wafer.
Electrical data corresponding to the three MOSFET samples can be seen below in
Fig 6.2. The Id vs. Vg of the lateral MOSFETs was tested and the field effect mobility is
shown as a function of field. The field effect mobility is derived from the transconductance
with a drain voltage of 50mV. These results show that the MOSFETs on 4 degree offcut
substrates exhibited the highest mobility values followed by the 2 degree offcut and the 8
degree offcut. If indeed the transition region width is linearly related to the peak field effect
mobility as has been suggested 2-4 then it is expected from these results that the 2 degree
sample will show the thinnest transition region and highest mobility with the 8 degree
sample exhibiting the thickest transition region and lowest mobility. These initial electrical
results do not support this relationship as all samples show comparable mobilities, with the 4
degree offcut sample exhibiting the highest peak mobility of around 30 cm2/Vs.
Figure 6.2 Field effect mobility versus field for the varying offcut
nitrided thermal oxidation samples measured with Vd = 50mV.
95
6.1.1 Materials Characterization of Nitrided Thermal Oxide on 2 Degree Offcut Material
Initial theories indicated that the 2 degree sample would yield the thinnest transition
region due to the lower amount of carbon at the interface due to the offcut. Images and
EELS data were taken on the FEI Titan at Oak Ridge National Labs. Fig 6.3 shows both BF
and HAADF images from the 2 degree sample with the SiO2 at the top of the sample and
SiC at the bottom. The HAADF image on the left shows the silicon sub lattice as white
spots in rows. The bright field image on the right also shows the atomic columns, as well as
the amorphous SiO2. Fig 6.4 shows relative composition plots and another BF image of the
sample. The relative composition plot on the left shows the silicon, carbon and oxygen
amounts, while the right side plot shows only the silicon and carbon. The SiC/SiO2 interface
in Fig 6.4 can be seen at the 5nm mark. The Si, C and O compositions are changing from
ideal for on either side of the interface as shown by the relative composition plots. From the
rightmost plot the 50/50 composition of the silicon and carbon on the SiC side of the
interface is seen to change, as the carbon decreases and silicon increases at the interface and
in the SiO2. The leftmost plot in Fig 6.4 also includes the oxygen data which is near zero in
the bulk of the SiC but begins to rise near the interface and settles in the bulk of the SiO2.
Figure 6.3 STEM Images of the 2 degree offcut thermal + NO anneal sample
left: HAADF image, right: BF image.
2 nm
2 nm
96
Figure 6.4 EELS quantification plots and bright field image of the 2 degree offcut thermal
oxidation + NO anneal sample.
From the composition plots in Fig 6.4 the transition region on both sides of the interface
can be seen. On the SiC side the transition region appears to be 2.7 to 3nm wide. In this
region the carbon can be seen to decrease before the silicon begins to decrease and at a
greater rate. The leftmost plot also indicates that there is oxygen present for approximately
2nm of the SiC side of the interface which seems to steadily increase through both transition
regions.
6.1.2 Materials Characterization of Nitrided Thermal Oxide on 4 Degree Offcut Material
The 4 degree sample was also analyzed on the same FEI Titan at ORNL. Figure 6.5
shows a HAADF image of the interface and the corresponding intensity profile. As in the
97
previous sample the
interface appears to be
abrupt in the HAADF
image with good crystallinity
exhibited from the bulk of
the SiC to the interface.
Figure 6.6 shows both the
EELS relative composition
as the intensity profile from
the HAADF image. From
Fig 6.6 it appears that the
SiC transition region is
about 1.5 to 2nm wide,
while the SiO2 transition
region is slightly over 1nm.
The green dashed lines in
the figures indicate the area
that the intensity profile was taken over and allow for better positioning of the intensity
profile overlay on the sample image. These dashed lines to not correlate to the transition
regions. Both sides of the transition region appear less wide in this sample as compared to
the 2 degree sample. There is approximately 2nm of SiC thickness where the carbon content
decreases before the SiC/SiO2 interface. This region is comparable to the region showing
carbon decrease in the 2 degree sample, but appears to be slightly thinner.
Figure 6.5 HAADF image for the 4 degree offcut sample.
98
Figure 6.6 EELS quantification plots and HAADF image for the 4 degree offcut sample.
6.1.3 Materials Characterization of Nitrided Thermal Oxide on 8 Degree Offcut Material
The final sample in the thermal oxidation on offcut substrate study was the 8 degree
offcut sample. This sample was prepared in the same manner as the previous samples on the
NB-5000 and was also studied using the Titan at ORNL. Figures 6.7 – 6.9 illustrate the
results from this sample. Figure 6.7 shows the HAADF image from the sample. The figure
visually indicates an interface similar to that exhibited by the 2 degree and 4 degree offcut
samples. From this figure is appears that the SiC side transition region is approximately 2.5
to 3nm wide and the oxide side is about 2nm wide. Figure 6.8 illustrates the relative
composition of the carbon and silicon and intensity profile along with a HAADF image. As
in the other samples the carbon content drops in the SiC transition region while the silicon
99
content increases near the
interface. This is also seen
in figure 6.9 which
illustrates the relative
composition for the silicon,
carbon and oxygen. The
carbon content is shown to
decrease as the oxygen
content increases in figure
6.9 even in the transition
region on the SiC side. This
is consistent with the
oxygen-carbon behavior
seen in the 2 degree sample
figure 6.4.
The transition
region on the SiC side of
the interface appears compositionally comparable for all three samples that were initially
studied. All three show that the carbon content begins to decreases at a point farther from
the interface than the silicon increases. The carbon also appears to decrease at a higher rate
than the silicon increases, this the C/Si ratio is decreasing. This conflicts with earlier
published results from Zvetlava2 and Biggerstaff3-4. The reason for the contradictory results is
not clear but possible reasons for the differences are discussed later in this chapter.
Figure 6.7 HAADF image for the 8 degree thermal
oxidation sample
100
Figure 6.8 EELS plots, HAADF image and image intensity profile for the 8 degree offcut
thermal + NO sample.
101
Figure 6.9 EELS quantification plots showing silicon, carbon and oxygen composition, the
HAADF image and the image intensity profile for the 8 degree thermal + NO sample.
As previously discussed if the transition region width is linearly related to the peak
field effect mobility as has been suggested 2-4 then it is expected from these results that the 2
degree sample will show the thinnest transition region and the 8 degree sample the thickest.
While the narrow range of peak mobilities prevents certainty, the data in Table 1 does not
appreciably support this idea. The 4 degree offcut sample appears to exhibit the thinnest
transition region and highest mobility. However, this is difficult to assert with certainty as
the error range in measuring the transition region thicknesses is limited by the scan
resolution for these experiments.
102
Table 6.1 – Comparison of SiC side transition region thickness, SiO2 side thickness
and lateral MOSFET field effect mobility for the three nitrided thermal oxide
samples studied.
Offcut
Angle
SiC Transition
Region Thickness
(nm)
SiO2 Transition
Region Thickness
(nm)
Field Effect
Mobility
(cm2/Vs)
2 deg 2.75 ± 1 2.75 ± 1 28
4 deg 2 ±1 1.75 ± 1 30
8 deg 2.75 ± 1 1.75 ± 1 26
6 .2 Invest igat ion of Miscut Effects on Nitr ided ALD Oxides
Additional lateral MOSFETs were fabricated to investigate the effect of miscut on
the ALD + NO anneal process. These wafers were compared to the thermal + NO anneal
processed wafers described in the previous section, 6.1. The samples were fabricated on 4
degree and 8 degree offcut wafers following the same fabrication process, only make changes
to the gate oxidation.
Electrical data from the ALD + NO annealed wafers is compared to the thermal +
NO anneal wafers in Fig 6.10. The field effect mobility as a function of field is shown for
the 4 samples. Little to no difference in peak mobility was observed between the ALD +
NO and thermal + NO wafers. However differences were observed in the low field regions
where the nitride ALD oxide and thermal oxides samples on 4 degree offcut material exhibit
comparable, improved turn-on characteristics as compared to the samples on 8 degree.
Overall the relationship between material offcut angle and peak mobility appears to stronger
than the relationship between peak mobility and oxidation method, as both the nitrided
ALD and thermal oxides exhibit higher peak mobilities on 4 degree material than the
corresponding 8 degree samples.
103
6.2.1 Materials Characterization of Nitrided ALD Oxide on 4 Degree Offcut Material
Samples for EELS and STEM analysis were prepared from the gate regions of lateral
MOSFETs fabricated with a nitrided ALD gate oxide. Sample fabrication and analysis
techniques were identical to those used for the thermal oxide samples discussed in section
6.1. A high angle annular dark field STEM image of ALD SiO2 deposited on the Si face of 4
degree offcut 4H-SiC is shown in Fig 6.11. The regions of the SiC and SiO2 near the
interface appear to be brighter in this image. This brightness is most likely indicative of beam
damage or sample charging in this region and is not necessarily related to elements of higher
value present in this region of the sample. Fig 6.12 includes an additional HAADF image
Figure 6.10 Field effect mobility versus field for the 4 and 8 degree offcut nitrided
thermal oxidation and nitride ALD oxide samples measured with Vd = 50mV.
104
along with the EELS relative
composition data for this sample. In
these relative composition plots, the
silicon composition is indicated by the
blue line, the carbon by the red line
and the oxygen by the green line.
From the EELS data it is clear that
there is approximately 2nm of
transition region on the SiC side of the
interface and another 3nm on the SiO2
side. Comparing these values to the 4
degree nitrided thermal oxide values
listed in Table 6.1 reveals similar values
for the 2 samples on the SiC side of
the interface, but differing results on the SiO2 side. Both samples exhibited roughly 2nm
regions of non-ideality on the SiC side, however the nitrided ALD oxide sample revealed
SiO2 side region thicker than that of the thermally oxidized sample.
Figure 6.11 STEM HAADF image for the 4
degree nitrided ALD sample.
105
6.2.2 Materials Characterization of Nitrided ALD Oxide on 8 Degree Offcut Material
EELS and STEM results from this sample can be seen below in figures 26 and 27.
Figure 26 shows a HAADF and bright field image from the sample. The dark region near
the interface on the bright field image is again a strong indication of strain in that region near
the interface. The images show a clean looking interface, similar in appearance to the thermal
+ NO samples.
Figure 6.12 Relative composition from EELS and HAADF image for the 4 degree ALD
+ NO anneal sample.
106
The chemical composition data can be seen in figures 6.14 and 6.15. As in the EELS data
shown for the previous sample, the silicon composition is indicated by the blue line, the
carbon by the red line and the oxygen by the green line. The intensity profiles are similar to
all of the others and plot the intensity across the box shown in the images. All EELS scans
resulted in a SiC side transition region width of approximately 1.5nm and a SiO2 side region
of about 2.5nm. This is the only sample studied that consistently revealed a SiO2 side
transition region of greater width than the SiC side. This could be due to the nature of the
deposition of ALD oxide and its densification during subsequent processing. Other results
from this sample are similar to the other samples analyzed. As seen in the other samples, the
carbon relative composition drops off at a rate greater than the silicon, resulting in a carbon
deficient SiC near the interface.
Figure 6.13 HAADF (left) and LAADF (right) images of the 8 degree ALD + NO
anneal lateral MOSFET sample
107
Table 6.2 summarizes the transition region thickness on both sides of the interface
for the nitrided ALD oxide samples. For all nitrided thermal and ALD oxide samples studied
transition regions on the SiC side of the interface were measured between 1.5 to 2.75nm,
with 1.5 to 2.75nm exhibited on the SiO2 side of the interface. These values are consistent
with previously collected thickness data.
Figure 6.14 Relative Composition, HAADF image and Intensity profile for the 8 degree
ALD + NO anneal sample.
108
Table 6.2 – Comparison of SiC side transition region thickness, SiO2 side thickness
and lateral MOSFET field effect mobility for the nitrided ALD oxide samples
studied.
Offcut
Angle
SiC Transition Region
Thickness (nm)
SiO2 Transition Region
Thickness (nm)
Field Effect
Mobility (cm2/Vs)
4 deg 2 ±1 2.75 ± 1 30
8 deg 1.75 ± 1 3 ± 1 25
While transition region thickness values observed in this work correlate, differences
to previous studies have been observed in the relative compositions near the interface.
Figure 6.15 Additional Relative Composition, HAADF image and Intensity profile for
another 8 degree ALD + NO sample shows repeatable EELS results.
109
Instead of a carbon increase in the transition region, samples from this research strongly
suggest a carbon deficiency in the transition region. All samples studied have shown this
characteristic. These differences suggest one of two possibilities: a change in the sample
composition near the interface over time or difference between STEM/EELS tools and
techniques. While a change in sample composition over time seems unlikely, the carbon
deficient characteristic shown in this research has been seen on 2 different STEM/EELS
tools, the VG 501 and the FEI Titan, both located at ONRL. The carbon rich samples
reported by Biggerstaff 3,4 were all measured on a different tool set (Hitachi 2010F located at
NCSU). This difference seems to suggest some problem with the tool or testing
methodology resulting in the conflicting compositional data. Samples tested by Biggerstaff
used a parallel linescan EELS sampling method3 to examine relative composition across the
interface, while the tools at ORNL used a high resolution beam to acquire areascans across
the interface. The superior technique and beam probe resolution available on the tools at
ORNL suggests more accurate data.
While all samples exhibited similar transition region thickness of 2-3nm on either
side of the interface, there were slight differences between the groups studied notably on the
SiO2 side. The thermal oxidation data presents a consistent picture of transition regions on
both the SiC and SiO2 sides of the interface with the SiO2 side being the thinner region.
While the data from the ALD+NO capacitor, shown in Chapter 5, is not conclusive as to
the width of transition region on the SiO2 side, the data from the ALD+NO lateral
MOSFET presents a different picture than the thermal oxidations. The ALD + NO
MOSFET samples show a SiC side transition region with a thickness similar to the thermal
oxidation samples but with a thicker SiO2 side region.
Another critical conclusion from this work is that all samples studied exhibited the
transition region coupled with field effect mobilities around 30 cm2/Vs. This suggests that
the limited mobility, and perhaps the transition region, could be a result of other similar
processing between the ALD and thermal samples. Oxidation steps are still the likely cause
of this region and two oxidation steps still remain in the common processing. First is the
incoming sacrificial oxidation that all wafer undergo when beginning fabrication. This
110
incoming sacrificial oxidation is thought to be important for removal of non-ideal material at
the surface of the SiC due to termination of the epitaxial growth. The second common
oxidation step is the 1175°C, 2 hr NO anneal. Additional secondary oxide growth associated
with this anneal is discussed in Chapter 2. Both thermal and ALD oxide wafers presented
above went through this anneal as well as the sacrificial oxidation, so all data from these
wafers represents at least 2 high temperature oxidation steps.
The fabrication of lateral MOSFETs without incoming sacrificial oxidation and/or
without NO anneal would be of great interest to determining the true cause of the transition
region. Removal of the sacrificial oxidation from all processing is achievable, however
currently the NO anneal is the best treatment for reducing Dit and increasing mobility of
thermal gate oxides on SiC. As such, removing this step would involve developing a new
gate oxidation process and would be a significant undertaking.
6 .3 Sacrif ic ia l Oxidat ion-Free Process MOSFET Comparison
To investigate
the role of the incoming
sacrificial oxidation on
the device mobility and
transition region,
additional capacitors and
lateral MOSFETs were
fabricated. The sacrificial
oxidation-free process
sequence for these runs
removed sacrificial
oxidations from the
process flow. For the
Figure 6.16 Capacitance-voltage measurements of the four
process splits from the sacrificial oxidation-free experiment
111
lateral MOSFET flow, this corresponded to the incoming sacrificial oxidation as well as the
post epitaxial regrowth sacrificial oxidation. These sacrificial oxidations are normally
performed to consume any non-ideal material, caused by termination of the epitaxial growth,
at the surface of the SiC. Several variations on the gate oxidation and anneal were
investigated in this experiment. Two thermal oxidation samples were prepared, one with and
standard NO anneal at 1175 ˚C for 2 hours and one unannealed. Two ALD oxide samples
were also included in the experiment, one with and standard NO anneal at 1175 ˚C for 2
hours and one with a 1 minute 600 ˚C post deposition anneal (PDA) in nitrogen. This
second ALD sample was processed to avoid all high temperature oxidation steps, notably
the sacrificial oxidations and NO anneals. All devices were fabricated on the Si face of 4
degree offcut 4H-SiC wafers. All ALD work was completed at NCSU, as with the previous
samples. The nitrogen PDA was also performed at NCSU before the polysilicon gate
deposition was completed.
Electrical data
from the p-type
capacitors and lateral
MOSFETs is shown in
figures 6.16 and 6.17 for
easy comparison with the
STEM/EELS transition
widths. Complete
presentation of the
electrical data and
discussion is presented in
Chapter 7. Due to the
poor characteristics of
the 600 ˚C PDA ALD
oxide as shown by the
Figure 6.17 Plot field effect mobility (calculated from
transconductance and measured with a drain voltage of 50
mV) of the four process splits from the sacrificial oxidation-
free experiment
112
capacitor in Fig 6.16, mobility data from this sample is not included in Fig 6.17.
STEM and EELS analysis were again used to characterize the reduced oxidation
MOSFET samples. All samples were prepared from the gate areas of the lateral MOSFETs
using FIB sample preparation techniques outlined in Chapter 3. Samples were measured in
the FEI Titan aberration corrected STEM at Oak Ridge National Labs. Fig 6.18 shows the
relative composition from EELS and STEM HAADF image from the unannealed thermal
oxide sample. The EELS data in this figure suggests approximately 2 nm of transition region
on either side of the interface. Similarly Fig 6.19 shows 3 nm of transition region on either
side of the interface for the nitrided thermal oxide sample. This is notable as the mobility of
the nitrided thermal oxide, as shown in Fig 6.17, was higher than the unannealed thermal
oxide, despite the thicker regions at the interface.
Figure 6.18 Relative composition from STEM/EELS and HAADF STEM image from the sacrificial oxidation-free, unanneal thermal oxide process sample.
113
Figure 6.19 Relative composition from STEM/EELS and HAADF STEM image from the sacrificial oxidation-free, nitrided thermal oxide process sample.
Figure 6.20 Relative composition from STEM/EELS and HAADF STEM image from the sacrificial oxidation-free, nitrided ALD oxide process sample.
114
The results from the ALD oxide samples are shown in Fig. 6.20 and 6.21. Both show
transition regions of 2-3 nm on either side of the interface, with a large transition region on
the SiO2 side. This feature is consistent with the previously discussed EELS results for ALD
oxide samples, which also revealed a larger transition region on the SiO2. Of notable interest
is the data from the 600 ˚C N2 annealed ALD oxide. The lower temperature PDA that this
sample received in conjunction with the sacrificial oxidation-free process means that this
sample did not see temperatures high enough to oxidize SiC during device fabrication. This
suggests that the 1.75nm transition region exhibited by this sample on the SiC side of the
interface is not a result of thermal oxidation, but is the expected standard width of the SiC
side of the interfacial region. However, this does not suggest that there are no defects
present on the SiC side of the interface after oxidation, as the STEM/EELS techniques used
here are not optimal for defect quantification. All HAADF images suggest similar interfaces
with brighter regions at the interface indicating bands of lattice distortion and strain.
Figure 6.18, 6.19, 6.20 and 6.21 all illustrate 2-3 nm of transition region on both the
SiC and SiO2 sides of the interface. Table 6.3 summarizes the transition region thickness on
Figure 6.21 Relative composition from STEM/EELS and HAADF STEM image from the sacrificial oxidation-free, low temperature annealed, ALD oxide process sample.
115
both sides of the interface for all samples, as well as the field effect mobility measured for
each samples. These results are consistent with the transition regions widths determine from
the offcut experiment as well as the capacitor results shown in Chapter 5, but represent
mobilities ranging from 0 – 40 cm2/Vs. This data suggests that there is no relationship
between transition region width and device mobility, as was previously suggested. Transition
regions for all samples were seen within 3 nm of the interface with no samples exhibiting
regions extending past 3 nm regardless of oxidation technique or anneal conditions. All
samples showed similar behavior of the with the carbon concentration on the SiC side of the
interface dropping as the oxygen increased neared the interface. No evidence of previously
reported carbon-rich regions on the SiC side of the interface was found.
Table 6.3 – Comparison of SiC side transition region thickness, SiO2 side thickness
and lateral MOSFET field effect mobility for the four process splits investigated with
the sacrificial oxidation-free process.
Oxidation
Process Split
SiC Transition
Region Thickness
(nm)
SiO2 Transition
Region Thickness
(nm)
Field Effect
Mobility
(cm2/Vs)
Unannealed
Thermal Oxide
2 ±1 2 ± 1 0
Nitrided
Thermal Oxide
3 ± 1 3 ± 1 34
600 ˚C N2 PDA
ALD Oxide
1.75 ± 1 2.75 ± 1 0
Nitrided ALD
Oxide
2.25 ±1 3 ± 1 40
116
6.4 Conclusions
This chapter presented and discussed several experiment designed to investigate the
SiC/SiO2 interface using STEM/EELS. All samples studied exhibited transition regions
within 3nm on both sides of the interface. For thermally oxidized samples, both unannealed
and nitrided, the regions on either side of the interface are similar widths. While for all ALD
samples a thicker transition region was observed on the SiO2 side of the interface, regardless
of anneal conditions. No carbon rich regions, as were previously reported, were observed for
any of the samples studied. Finally transition regions widths comparable to all other samples
were witnessed for the lower temperature anneal ALD sample. This suggests a standard
transition region width within 3nm on either side of the SiC/SiO2 interface, regardless of
oxidation technique (deposited or thermally growth) or anneal conditions.
117
6.5 References
1. L. Muehlhoff, W. J. Choyke, M. J. Bozack, and J. T. Yates, J. Appl. Phys. 60, 2842
(1986).
2. T. Zheleva, A. Lelis, G, Duscher, F. Liu, I. Levin and M. Das, App. Phys. Lett. 93,
022108 (2008).
3. T. L. Biggerstaff Electronic Thesis. North Carolina State University, 2008.
4. T. L. Biggerstaff, C. L. Reynolds, Jr., T. Zheleva, A. Lelis, D. Habersat, S. Haney,S.-
H. Ryu, A. Agarwal, and G. Duscher, App. Phys. Lett. 95, 032108 (2009).
118
C H A P T E R 7
MOSFETS ON SIC RESULTS AND DISCUSSION
7.1 Sacrif ic ia l Oxidat ion-Free MOSFET Comparison
To investigate the role of the incoming sacrificial oxidation on the device mobility,
additional capacitors and lateral MOSFETs were fabricated. The “reduced oxidation”
process sequence for these runs removed sacrificial oxidations from the process flow. For
the lateral MOSFET flow, this corresponded to the incoming sacrificial oxidation as well as
the post epitaxial regrowth sacrificial oxidation. These sacrificial oxidations are normally
performed to consume any non-ideal material, caused by termination of the epitaxial growth,
at the surface of the SiC. Several variations on the gate oxidation and anneal were
investigated in this experiment. Two thermal oxidation samples were prepared, one with and
standard NO anneal at 1175 ˚C for 2 hours and one unannealed. Two ALD oxide samples
were also included in the
experiment, one with and
standard NO anneal at
1175 ˚C for 2 hours and
one with a 1 minute 600
˚C post deposition
anneal (PDA) in
nitrogen. All devices
were fabricated on the Si
face of 4 degree offcut
4H-SiC wafers. All ALD
work was completed at
NCSU, as with the Figure 7.1 Capacitance-voltage measurements of the four
process splits from the sacrificial oxidation-free experiment
ν = 100 kHz
119
previous samples. The nitrogen PDA was also performed at NCSU before the polysilicon
gate deposition was completed.
7.1.1 Electrical Characterization
Both the capacitors
and the lateral MOSFETs
from the samples were
electrically characterized. The
capacitance-voltage
measurements from the p-
type capacitors are shown in
figure 7.1. While the behavior
of the thermal oxide
capacitors looks very similar,
the nitrided ALD oxide
capacitor shows significantly
improved behavior as
compared to the ALD oxide
with nitrogen PDA. The
significant stretch out in the
non-nitrided ALD curve
suggests a much higher
density of interface states
throughout the bandgap. The
top plot in figure 7.2 shows
the Id-Vg curves from this
experiment. The ALD oxide sample that received the 600˚ C PDA is not shown in the plots,
Figure 7.2 Plots of Id-Vg (top) and field effect mobility (calculated from transconductance) of the four process splits from the sacrificial oxidation-free experiment.
120
as the gates were leaky at only a few volts. From the Id-Vg data, it is clear that the nitrided
ALD sample exhibits improved behavior as compared to the nitrided thermally oxidized
sample. This is notable when compared to the previous results for the 4 and 8 degree miscut
wafers which showed very similar behavior for the both the nitrided ALD and thermal
oxides. The field effect mobility is shown as function of gate voltage in the bottom plot in
Fig 7.2. The peak mobility exhibited by the nitrided ALD sample is 40 cm2/Vs, an
approximate 15% improvement over the nitrided thermal oxide sample. This result
strengthens the idea that the low achieved mobility is related to defect created by the high
temperature thermal oxidation processes. By reducing the number of high temperature
thermal oxidations, a higher mobility sample was realized.
7.1.2 Electrical Modeling
For these samples modeling was used as a method of additional characterization.
Modeling procedures used were reviewed in Chapter 3. Transconductance and mobility
models developed by Dr. John Hauser were used to model the devices. The capacitance data
was modeled first (as discussed in Chapter 5) and these results were used, along with
experimental Id-Vg measurements to model the transconductance. Figure 7.3 below shows a
Figure 7.3 Experimental data for nitrided ALD oxide compared to calculated data and data modeled with varying interface state densities.
121
plot of the experimental transconductance data compared to the modeled and calculated
data from the nitrided thermal oxide sample. Both samples exhibited best fit of the modeled
data with Dit values of 7.5E12 to 8.5E12. It is notable that these Dit values determined
through modeling were comparable for the ALD+NO and thermal+NO sample and do not
reflect the higher mobility exhibited by the nitrided ALD oxide sample.
7.2 Experimental Ver if icat ion
Repetition of the reduced oxidation experiment was completed to examine the
repeatability of the high mobility results shown by the nitrided ALD sample. Due to the
poor mobility results from the unannealed thermal oxide and the low temperature N2
annealed ALD oxide, only the NO annealed ALD and NO annealed thermal oxide splits
were repeated. The nitrided ALD oxide and nitrided thermal oxide lateral MOSFETs were
again fabricated on 4 degree offcut 4H-SiC wafers following processing procedures outline
in Chapter 3.
7.2.1 Electrical Characterization
Upon completing fabrication, the MOSFET Id-Vg and transconductance curves
were measured. The field effect mobility as calculated from the transconductance for both
reduced oxidation experiment 1 and experiment 2 is shown below in Fig 7.4. The results
from experiment 2 differ from experiment 1, with both the nitrided thermal oxide and
nitrided ALD oxide exhibiting similar peak mobilities of 30 cm2/Vs. This difference could
not be attributed to processing differences as both experiments followed the same
fabrication steps, using the same mask sets and tools.
122
7.2.2 Electrical Modeling
As in reduced oxidation experiment 1, electrical modeling was used to compare the
results and examine the effect of interface state density. For the nitrided thermal oxide, an
interface state density of between 7.5E12 and 1E13 provided the best fit to the experimental
data. This value, approximately 8.5E12, is comparable to the 7.5E12 value modeled from the
nitrided thermal data from reduced oxidation experiment 1.
Modeling was also completed for the corresponding nitrided ALD sample. As with
the thermal oxide sample, the optimum fit appears to be between 7.5E12 and 1E13, or
roughly 8.5E12. All Dit values, determined through modeling, for the reduced oxidation
experiments were between 7.5E12 and 8.5E12. However peak field effect mobilities from 30
– 40 cm2/Vs were recorded for these samples. It is important to note that Dit values
Figure 7.4 Field effect mobility as a function of gate voltage for the nitrided thermal and ALD oxides from both sacrificial oxidation-free experiments.
123
suggested from the modeling are approximately one order of magnitude higher than value
calculated from hilo C-V measurements on corresponding capacitors. This difference
suggests that these Dit values from the model should be used as relative comparisons and
not absolute values.
Table 7.1 Comparison of Hauser Mob2d model results for both sacrificial oxidation-
free experiments.
Sac Oxidation-Free Experiment 1 Sac Oxidation-Free Experiment 2
Nitrided ALD Oxide
Nitrided Thermal Oxide
Nitrided ALD Oxide
Nitrided Thermal Oxide
EOT 13.6400 13.4283 19.2436 15.2161
Vfb -3.6437 -4.2900 -4.2001 -4.0196
Vt -0.0696 6.1937 -1.0859 -0.9145
VtQm -0.0940 5.8575 -1.0980 -0.9294
PhiB 1.4164 1.4178 1.3017 1.3033
Q 4.92E+11 1.03E+12 7.25E+11 7.88E+11
NdSurf 1.07E+16 1.21E+18 2.84E+15 4.27E+15
NdBulk 8.55E+15 9.03E+15 1.02E+14 1.09E+14
Cfb 136.0077 200.6140 -56.2085 106.8431
Cox 212.7845 217.0383 150.8233 190.7460
Cdep 21.7000 22.2500 2.7050 2.7975
Ld 36.0511 3.5401 69.9327 57.1070
RMS 3.2098 92.4215 9.4191 12.6074
Fit Error 5.70% 7.60% 4.40% 7.00%
7.3 Role of the Nitr ic Oxide Anneal
As the mobility differences between successive nitrided ALD oxides were not
explained by processing differences or Dit determined through modeling, nitrogen
concentration at the interface was examined. The relationship between nitrogen
concentration at the interface, resulting from the NO anneals, and enhanced device mobility
has been well documented and was discussed in Chapter 2. Fig 6.28 shows SIMS nitrogen
124
concentration profiles across the SiO2/SiC interface for all of the reduced oxidation
experiments. All SIMS profiles discussed were ordered through Dr. Victor Chia of Balazs
Nanoanalysis. Fig 7.5 shows the nitrogen concentration made from the N+13C trace. The
14N13C trace is best suited for investigation of the SiO2/SiC interface as using the 12N28Si-
molecular species can result interference from 12C30Si- and 13C2- ions. The 12N28Si- profile was
used to monitor the concentration in the top boron-doped polysilicon layer as there is an
interference to the 14N13C- at mass 27 from 11B16O. Only the 14N13C trace in the SiO2 and
into the SiC is illustrated in Fig 7.5, as the profile across the polysilicon is not pertinent.
The out of family mobility results exhibited by the experiment 1 nitrided ALD sample are
mirrored here in the SIMS results with a much higher concentration in this sample. The
Figure 7.5 SIMS nitrogen concentration profiles for the nitrided thermal and nitrided ALD samples from sacrificial oxidation-free experiments 1 and 2.
125
nitrided ALD experiment 1 sample revealed 6E21 atoms/cc at the interface, while the other
samples tested revealed 2-4E20 atoms/cc. The shape of the peaks at the interface is also
significantly different with a broader peak (wider full width at half maximum, FWHM)
evident for the highest concentration profile. This is indicative of a wider region of nitrogen
incorporation than is exhibited by the lower concentration samples.
An additional experiment was completed to further probe the role of NO anneal
time in nitrogen incorporation for ALD oxides. Blanket ALD SiO2 samples were annealed
for 30 minutes or 120 minutes. Ellipsometry was used to measure the oxide thickness before
and after anneal. SIMS results for the nitrogen concentration are shown below in Fig 7.6.
Figure 7.6 SIMS nitrogen concentration profiles for blanket ALD oxides annealed in NO at 950 °C for 30 and 120 minutes.
126
Nitrogen is clearly shown at the interface for both the 30 minute and 2 hour anneal, with the
relative peak positions remaining stable. This suggests that the nitrogen peak moves with the
interface through the anneal process and subsequent secondary oxidation. This same
behavior is exhibited by thermal oxides annealed in NO5 and N2O7,8, which suggests that
dissociation of NO in the bulk of the SiO2 and at the interface is the source of nitrogen
available for passivation. As discussed above, the widths of the peaks at FWHM are constant
for both curves, suggesting the width of the nitrogen incorporated region is the same for
both samples. The ellipsometry data for the pre anneal and post anneal measurements is
shown below in Table 7.2. This data suggests comparable amounts of densification for the
30 minute anneal and the 2 hour anneal. This suggests that the densification rate of the oxide
does not explain the level of nitrogen incorporation.
Table 7.2 Ellipsometry data for ALD oxides before and after Nitric Oxide annealing
Anneal Time Pre Anneal Thickness
Post Anneal Thickness
Difference % Change
30 minutes 227.3 +/-0.107 182.48 +/- 0.114 44.82 19.7% 120 minutes 239.64 +/- 0.104 189.92 +/- 0.111 49.72 20.75%
A possible explanation of the increased nitrogen concentration in the experiment 1
ALD sample can be found in a passivation model derived by Rozen1. It proposes a
passivation rate proportional to the density of available binding sites Dj (in cm-2) of type j
and cross-section sj (in cm2). The rate is also inversely proportional to the sum of sjDj over
all competing locations. It is widely understood that as-deposited ALD oxides often require
post deposition annealing to anneal out defects and improve electrical characteristics.2,3,4,5 It
is possible that the low temperature deposited ALD oxide provides a higher density of
binding sites for the nitrogen, than the high temperature thermal oxide. In addition to
binding at dangling bonds, carbon-related binding sites could be interstitial carbon dimers,
carbon clusters, or complex silicon oxycarbons. The unannealed XPS results shown in
127
Chapter 4 support the presence of excess carbon, showing elevated levels of carbon in the as
deposited ALD SiO2 as compared to annealed samples. Previous work on thermal oxides has
shown that NO anneals lead to the reduction of excess carbon through formation of C-N
and Si-N bonding at the interface and in the oxide.6,7,8,9,10,11 Deak explains the possible
reactions for converting carbon dimmers into mobile carbon interstitials and immobile N=C
dimers as:12
SiC/SiO2 : [(Ci = Ci)0 + 2e-] + SiO2 : NO
→ SiC/SiO2 : [(Ci)C- + Oif
0] + SiO2 : CN- (6.1)
SiC/SiO2 : [(Ci = Ci)0 + e-] + SiO2 : NO
→ SiC/SiO2 : (Ci = Ci)+ + SiO2 : CO2- (6.2)
Atomic nitrogen, produced through the dissociation of the NO in the bulk of the SiO2, can
also result in the removal of the carbon dimers as:12
SiC/SiO2 : [(Ci = Ci)0 + Nif- + e-] + SiO2
→ SiC/SiO2 : (Ci)C- + SiO2 : CN- (6.3)
SiC/SiO2 : (Ci = Ci)0 + SiO2 : Ni-
→ SiC/SiO2 : [(Ni = Ci)+ + e-] + SiO2 (6.4)
This type of nitrogen incorporation resulting from the higher levels of carbon, and thus the
higher density of binding sites in the as deposited ALD oxides offers a practical explanation
of the Fig 7.5 SIMS results. The low density of the as deposited ALD SiO2 also provides for
enhanced diffusion of the NO to the interface, allowing for greater nitrogen incorporation
128
earlier in the anneal process. Optimization of the excess carbon at and near the interface in
the ALD SiO2 combined with the low density, as deposited film would provide an excellent
method for increased nitrogen incorporation.
The previously reported “universal” curve illustrating the relationship between peak
field effect mobility and threshold voltage for nitrided thermal oxide, is shown below in Fig
7.7. Results from this work have been included on the curve. The high mobility results from
the nitrided ALD from experiments 1 and 2 are shown by the green stars in Fig 7.7. The
data point from the nitrided ALD from experiment 1 is clearly above the nitrided thermal
oxide points, possibly suggesting a separate line for the nitride ALD oxides. The use of ALD
is important as it also allows for the use of Al2O3 or other charge control layers as a means
of increasing the threshold voltage of the device. This ability to control Vth combined with
optimized, controllable nitrogen incorporation would result in a significantly improved gate
oxidation process.
Figure 7.7 Curves of the relationship between mobility and onset of conduction for nitrided thermal oxides on 4H-SiC. Peak mobility data from this work is included. (adapted from 13).
129
7.4 Conclusions
This chapter contains several critical results. High mobilities were achieved using
nitrided ALD SiO2 as a gate oxide for lateral MOSFETs. This increased mobility as
compared to nitrided thermal oxides, was shown to be an effect of the amount of nitrogen
incorporated, with high mobility nitrided ALD oxides containing fifteen times more nitrogen
than the nitrided thermal anneal samples. Proposed models for nitrogen incorporation
suggest that the high levels of nitrogen indicate greater binding sites available in the ALD
oxides before undergoing the NO anneal. The high levels of carbon and dangling bonds at
the interface in the unannealed, low temperature deposited ALD oxide make it an ideal
candidate for increased nitrogen incorporation after high temperature NO anneal. The more
ideal nature of the high temperature thermally grown oxide provides fewer binding sites,
such as interface dangling bonds or defects, for the nitrogen compared to the low
temperature deposited ALD. These heavily nitrided ALD oxides were also shown to be
outside of the previously accepted relationship between peak mobility and threshold voltage.
Optimization of the process to achieve repeatable high mobility results is necessary for
success. These results also suggest that low temperature, low density ALD films are excellent
mediums for achieving higher amounts of passivating species at the interface through
annealing and should be further studied to optimize this benefit.
130
7.5 References
1. John Rozen, Ph.D. Thesis, Vanderbilt University, 2008.
2. H. Zhou, G. I. Ng, Z. H. Liu, and S. Arulkumaran, App Phys Exp 4, 104102 (2011).
3. L. Zhang, H.C. Jiang, C. Liu, J.W. Dong and P. Chow, J of App Phys D 40, 12
(2007).
4. Y.C. Cheng, App Surf Sci 258, 1 (2011).
5. J. Harjuoja, A. Kosola, M. Putkonen and L. Niinisto, Thin Solid Films 496 (2006).
6. G. Y. Chung, J.R. Williams, T. Isaacs-Smith, F. Ren, K. McDonald and L.C.
Feldman, App. Phys. Lett. 81, 22 (2002).
7. K. Chatty, V. Khemka, T. P. Chow, and R. J. Gutmann, Journal of Elec. Matls 28,
161 (1999).
8. K. McDonald, M. B. Huang, R. A. Weller, L. C. Feldman, J. R. Williams, F. C.
Stedile, I. J. R. Baumvol, and C. Radtke, Appl. Phys. Lett 76, 568 (2000).
9. H. Li, S. Dimitrijev, D. Sweatman, H. B. Harrison, P. Tanner, and B. Feil, J. of Appl
Phys 86, 4316 (1999).
10. P. Jamet, S. Dimitrijev, and P. Tanner, J. of App Phys 90, 5058 (2001).
11. X. Shen and S. T. Pantelides, Mat Sci Forum 717-720, 445 (2012).
12. P. Deak, J. M. Knaup, T. Hornos, C. Thill, A. Gali and T. Frauenheim, J of Phys D:
Appl Phys 40, 6242 (2007).
13. A. Agarwal and S. Haney, J of Elec. Matls 37, 5 (2008).
131
C H A P T E R 8
CONCLUSION AND FUTURE WORK
8.1 Descript ion of Findings
In this thesis, silicon dioxide formed at low temperature using atomic layer
deposition was explored as a gate oxide for MOS devices on 4H-SiC. The ALD oxide was
compared to thermally grown oxides. The effect of post oxidation anneals in nitrogen,
forming gas and nitric oxide were also examined. Electrical characterization including
capacitance-voltage and current-voltage measurements was conducted. Materials
characterization including ellipsometry, STEM/EELS, XPS and SIMS was also completed.
This final chapter offers a compilation of results and suggestions for future work.
SiO2 was successfully deposited on 4H-SiC at 150 °C using atomic layer
deposition
The conduction band offset for the ALD SiO2 was determined to be 2.43 eV,
which falls within the range of values reported for thermally grown oxides
(see Appendix B).
Capacitors were successfully fabricated in both silicon and 4H-SiC Si-face
substrates using ALD SiO2
MOSFETs were fabricated on 4H-SiC for the first time using ALD SiO2 as
the gate oxide
Post oxidation anneals in nitric oxide were proven to be the most beneficial
POA for ALD SiO2.
132
High peak mobilities of 40 cm2/Vs were recorded for MOSFETs fabricated
with nitrided ALD SiO2. This correlates to a 15% improvement over the
standard nitrided thermal oxide.
The density of interface traps was determined to be equivalent for nitrided
thermally grown oxides and nitrided ALD SiO2 on 4H-SiC.
EELS investigations showed no difference in Si/C ratios between the ALD
oxide and thermally grown gate oxides.
EELS relative composition studies showed transition region widths of 3 nm
or less on both sides of the interface regardless of oxidation technique or
anneal temperature or ambient.
A thicker transition region was noted on the SiO2 side of the interface,
compared to the SiC side for all of the ALD samples studied. Thermally
oxidized samples exhibited transition regions of equal width on either side of
the interface.
High mobility samples were correlated using SIMS to increased nitrogen
concentrations at the SiO2/SiC interface. The highest mobility ALD sample
exhibited a nitrogen concentration of 6E21 atoms/cm2.
Nitrogen concentration at the interface for the nitrided ALD oxides was
shown to be a function of anneal time, similar to the relationship shown for
thermally grown oxides. However, for the same anneal times and
temperatures higher concentrations can be reached for the ALD oxides.
The results listed above summarize the milestones discussed in this work. These
results indicate that SiO2 deposited using low temperature atomic layer deposition is a
133
excellent candidate for improved gate oxides on 4H-SiC MOSFETs given the opportunity
for increased nitrogen concentration. The elevated levels of nitrogen measured in the NO
annealed ALD SiO2 sample are unique and are directly attributed to the low temperature
ALD process. The oxide structure and associated defects of the as deposited ALD SiO2
provide extensive binding site for the nitrogen during the NO anneal. Higher field effect
mobilities were reported and are directly linked to these increased nitrogen concentrations.
The SiO2/SiC interface of the nitrided ALD oxide is comparable to nitrided thermal oxides
in that no evidence of transition region was demonstrated, refuting the previous link
between mobility and transition region width. Repeatable high peak field effect mobilities
are possible with an optimized nitrided ALD process.
8 .2 Future Work
There are a number of areas for interesting work based on this thesis. First, work on
addressing the repeatability of the ALD process as related to the uptake of nitrogen is
critical to further development of an ALD based gate oxidation process. As the work here
supports the hypothesis of additional secondary oxide growth as a result of the NO anneal1,
alternative methods of introducing nitrogen at the interface would be noteworthy for study.
Implantation prior to the oxide deposition, as studied using thermally grown oxides by
Nipoti’s group2, would be an interesting pathway. The use of ALD also allows for nitrogen
incorporation via surface treatments prior to ALD oxide deposition or addition of nitrogen
inclusive precursors in the system to allow for deposition of monolayers of nitrogen at and
near the interface. These alternative pathways for nitrogen introduction would allow for the
exploration of lower temperature anneals to achieve nitrogen passivation without additional
oxidation.
While current processes center around the nitric oxide anneal, there has been
considerable interest in POCL3 annealing in the past few years. The Okamoto group have
published several results on the benefits of annealing in POCl33,4. While this process has
134
been linked to unstable threshold voltages5, recent results present at ECSCRM 2012 by Dr.
Yano suggest that annealing samples in NO following the POCl3 anneal results in stable
threshold combined with enhanced mobility. The high levels of nitrogen at the interface of
the high mobility, nitrided ALD sample suggest that benefits seen from alternative anneal
ambient may also be enhanced with ALD oxides.
135
8.3 References
1 G. Y. Chung, J.R. Williams, T. Isaacs-Smith, F. Ren, K. McDonald and L.C.
Feldman, App. Phys. Lett. 81, 22 (2002).
2 A. Poggi, F. Moscatelli, Y. Hijikata, S. Solmi, and R. Nipoti, Microelectronic Engineering
84, 12 (2007).
3 D. Okamoto, H. Yano, K. Hirata, T. Hatayama, T. Fuyuki, Appl. Phys Lett. 96,
203508 (2010).
4 D. Okamoto, H. Yano, K. Hirata, T. Hatayama, T. Fuyuki, IEEE Electron Device
Lett. 31, 7 (2010).
5 Y.K. Sharma, Y. Xu, E. Garfunkel, A.C. Ahyi, T. Issacs-Smith, X. Shen, S. T.
Pantelides, X. Zhu, J. Rozen, L.C. Feldman, J. R. Williams, Mat Sci Forum 717-720
(2012).
136
A P P E N D I C E S
137
APPENDIX A
EELS QUANITIFICATION METHODS
Analysis of the EELS data is an involved process requiring several steps. First the
background must be removed from the spectra to ensure accurate cure-loss signal intensity for
accurate analysis. Additional corrections for plural scattering, thickness variations, or noise may
be necessary depending on the sample. Background subtraction and subsequent quantification
are performed using Digital Micrograph (DM) software. The power-law background model
was used to fit the background region for all quantification. Using the DM quantification
function, the threshold energies for peaks to be studied are added to a quantification list. As it
is generally not possible to quantify all counts in a peak due to background extraction errors, a
finite integration range is set. This finite integration range results in a partial count integral.
This modification is acceptable for the data analysis as it has already been shown that plural
scattering is negligible in these samples. The edges are then setup by adjusting the background
fitting window to an appropriate area and adjusting the signal integration window as need to
encompass the whole peak signal. It is important that the signal integration window does not
overlap with any other edges or results will be incorrect. Figure A.1 illustrates the background
and signal integration window setup on a single spectra. This setup is then used on all spectra
taken across the interface. The area used for the background determination is shown by the
red box. The calculated background contribution shown by the red line is subtracted from the
spectra. The signal width used is illustrated by the green box. Signal counts outside this box are
not used in the quantification analysis. The resultant signal used for the analysis is shown by
the green line near the bottom of the plot. The core-loss edge is shown by the vertical blue
marker and the computed energy differential cross section is shown by the horizontal blue line.
138
Figure A.1 Example of signal, background and edge set up for quantification.
139
The following steps are automatically performed using the “quantify” function in DM. First
the edge counts are extracted yielding the partial edge counts integral. Next the partial inelastic-
scattering cross-section is calculated for the same edge and integration range. The low-loss
spectrum is then counted so it can be accounted for in the expression for elemental
concentration. Absolute concentration of each edge is then calculated and finally
corresponding relative concentrations for all edges are determined and output. These steps are
all performed within the software. The beam energy, convergence angle and collection angle of
the measurement must be input to the software if the analysis is run offline from the tool. If
these values are not correctly recorded and input, then the resulting calculations and data will
be erroneous. The DM quantification outputs 3 plots: extracted core-loss signal, areal density
and relative composition. The relative composition plots are most often used in this report.
Examples can be seen in Fig. A.2. The topmost plot shows the edge signals from the
140
quantification. These edge signals show the single edge output with the background
subtracted. From these signals one
can see how much signal results
from the present components at
position across the scan. The
middle plot in Fig. 4 shows the
areal density across an interface.
While this plot shows specifically
the silicon and carbon areal
densities, it is possible to quantify
more elements when they present
and display all areal densities on
one plot. Areal density plots show
the density of each atom type per
area unit. In this areal density plot
the density of the silicon is
indicated by the green area and
the density of the carbon is shown
by the red line. For this research
these plots can be useful as they
can show the relative densities of
the atoms. In this plot the right
hand portion from approximately
5 to 10 nm is the epitaxial SiC,
from 2 to 5nm appears to be the
interface region and from 0 to 2
nm is SiO2. From this areal density
plot it is clear that the carbon
Figure A.2 Digital Micrograph quantification output graphs as a function of scan distance. Top: Extracted core-loss signal. Middle: Areal Density. Bottom: Relative composition.
141
density drops near the interface at a higher rate than the silicon density. The final plot in Fig.
A.2 is a relative composition plot. This plot shows the relative composition of elements
present as a function of distance across the scan. The computation used assumes that the
edges analyzed sum to 100% composition over the scan. In the relative composition plot the
green area indicates the amount of silicon in the composition relative to the carbon amount
indicated by the red line. So in this plot it is clear that the right hand side is the bulk silicon
carbide which shows roughly 50% carbon and 50% silicon. The composition begins to vary
around 3.5 – 4nm and the carbon and silicon amount diverge. This is indicative of
the transition region before the SiO2. The oxide region in this plot can be seen by the 100%
composition of silicon and no carbon present. These plots are often used in this research as
they clearly illustrate which elements are present and in what relative amount across the
epitaxial SiC through the interface into the oxide. Finally a computed analysis results window is
output by the quantification function. The results window displays the absolute and relative
concentration, as well as intermediate results and parameters used in the calculations.
Another important aspect of EELS and subsequent quantification is the scan resolution or the
number of scans taken across a set length. From Fig A.2 one can see that the scan was taken
across 10nm of the interface with 1 spectra acquired per nanometer. It is important to try to
achieve the highest scan resolution possible on the equipment. Figure A.3 shows additional
areal density and relative composition plots. The scan for these plots was done over 100
spectra with one spectra taken for every silicon plane or every 2.52Å. The resolution of this
scan is shown in Fig A.3 and is far superior to the scans seen in Fig A.2. Consequently, the
analysis data from Fig A.3 is of much high quality and can be interpreted with greater certainty
than the data from Fig A.2. Again in this relative composition scan the green area indicates the
silicon percentage of composition as compared to the carbon which is given by the red line.
The left side of Fig A.3 shows the 50/50 silicon carbide with the interface around 20nm and
the right side reflecting the oxide bulk.
142
33.526.82013.46.7nm
Re
lati
ve
Co
mp
osi
tio
n
Figure A.3 Relative composition plot with high scan resolution provides more data at the
interface.
143
A P P E N D I X B
ENERGY BAND ALIGNMENT OF ALD SIO 2 ON SIC
Valance Band Offset Measurements
Understanding of the valence band offset at the ALD SiO2/SiC interface is critical
for accurately determining device parameters including Schottky-barrier heights and
interface band bending. As described by Kraut et al. in 19801, XPS can be employed to
precisely determine the valence band edge. This method describes the valence band offset
(ΔEv) as:
(1)
For this analysis the C 1s spectra was used as the reference core level for the SiC substrate
and the O1s was used as the reference core level for the SiO2. The thin dielectric samples
measured received 25Ǻ of ALD SiO2. This thin dielectric minimizes complications related to
the potential spread at an abrupt interface and also is insensitive to band bending at the
interface. The XPS C 1s spectra for the thin SiO2 on SiC sample and bulk SiC sample are
shown below in Fig. B.1.
144
This figure clearly illustrates the peak alignment for the C 1s peaks for the SiC substrate and
the thin SiO2 on SiC. As such for equation 1:
(2)
Similar binding energy peaks are shown in Fig. B.2 for the O 1s spectra of the thin
ALD SiO2 and the thick ALD SiO2. Again the 2 peaks are aligned to the same energy position
such that:
Figure B.1 XPS C 1s spectra for a thin (2.5 nm) ALD SiO2 on SiC sample and bulk SiC sample showing good peak alignment.
145
(3)
A core level peak at 533.3 eV is exhibited by both the thick and thin dielectric samples.
By combining equations 1, 2, and 3, the simplified equation for the valence band offset
is given by:
Figure B.2 XPS O 1s spectra for a thick (16.8 nm) ALD SiO2 and thin (2.5 nm) ALD SiO2 on SiC sample showing good peak alignment.
146
(4)
The valence band maximum (VBM) was determined through linear extrapolation of the edge
of the valence band spectra. The valence band offset for this system was determined to be 2.43
eV through the use of equation 4. Figure B.3 shows the valence band spectra from which the
data was extrapolated. The bulk SiC spectra yielded a VBM of 0.96 eV and the thick SiO2
showed 3.38 eV.
Figure B.3 XPS valence band spectra for a thick (16.8 nm) ALD SiO2 and a bulk SiC sample. The VBM was determined to be 3.39 eV for the SiO2 and 0.96 eV for the 4H-SiC.
147
Energy Band gap Measurements
There are several methods for determining the energy band gap. In recent years, the
zero loss deconvolution method for band gap EEL spectra has been shown to be highly
reliable.2 This method was first described by Rafferty and Brown3 in 1998 as a way to study
direct and indirect transitions across the band gap. This method was used to determine the
band gap of the ALD SiO2 and to verify the band gap of the 4H-SiC substrates. Energy loss
spectra were corrected for
plural scattering using Fourier-
Log deconvolution as described
in Egerton.4 Kramers-Kronig
analysis was then performed to
determine the energy-loss
spectrum. The deconvolved
energy loss spectrum for the
4H-SiC is shown in Fig B.4a.
The band gap determined from
this spectrum is ~3.1eV. The
generally accepted band
structure of 4H-SiC as
determined by Persson and
Lindefelt5 is shown in Fig B.4b
and shows a band gap of 3.23
eV. The 3.1eV band gap
determined from the measured
spectrum is close to the
accepted value, with the
difference most likely due to
error from non-optimized
Figure B.4 a) Deconvolved energy loss spectra for 4H-SiC showing a bandgap onset at 3.1 eV b) Published band structure for 4H-SiC showing a bandgap of 3.23 eV5
Eg = 3.1 eV
148
EELS measurements. The EELS data used was taken to analyze the SiC/SiO2 interface,
similar to the EELS data reported in Chapter 6 and as such was not optimized for band gap
measurement. Accurate determination of a band gap through EELS requires 500 – 1000
spectra acquired using a high dispersion to realize the full resolution of spectrometer. The
smaller band gap materials require more spectra to accurately determine the band gap. An
optimized measurement will allow for more accurate removal of the zero loss peak and better
energy resolution. However the data from Fig B.4a is sufficient to indicate agreement with
accepted values. The deconvolved energy loss spectrum for the ALD SiO2 is shown in Fig
B.5. The measured value of 9.0 eV is in good agreement with published value of 8.9 – 9.0eV
for the SiO2 band gap.
Energy Band Diagrams
Construction of the
energy band diagram further
clarifies the ALD SiO2/SiC MOS
system by illustrating the valence
and conduction band offsets in
relation to the semiconductor
and oxide band gaps. The band
diagram can be determined from
the measured SiO2/SiC valence
band offset and the band gap.
The conduction band offset can
be determined through the expression:
(5)
Eg = 9.0 eV
Figure B.5 Deconvolved energy loss spectra for 4H-SiC showing a bandgap onset at 9 eV
149
As such the conduction band offset for this system is equal to 3.34 eV. A schematic of the
band diagram for ALD SiO2 on 4H-SiC is shown in Fig B.6. This figure was generated using
the Knowlton Energy Band Diagram program.6 Assuming a polysilicon gate metal, the
behavior of the MOS system can be examined under various bias conditions. Examples of this
are shown in Fig B.7.
Figure B.6 Energy band diagram for p-type polysilicon on 16.8nm of ALD SiO2 deposited on n-type 4H-SiC
150
Figure B.7 Energy band diagram for a capacitor fabricated with p-type polysilicon on 16.8nm of ALD SiO2 deposited on n-type 4H-SiC shown biased at 12 V.
151
References
1. E. A. Kraut, R. W. Grant, J. R. Waldrop, and S. P. Kowalczyk, Phys. Rev. Lett. 44, 1620
(1980).
2. B. Rafferty, S. J. Pennycook and L.M. Brown. J. of Electron Microscopy 49, 4 (2000).
3. B. Rafferty and L.M. Brown. Physical Review B 58, 16 (1998).
4. R. F. Egerton, Electron Energy-Loss Spectroscopy in the Electron Microscope
(Spring, New York, 2011).
5. Materials properties taken from
http://www.ioffe.rssi.ru/SVA/NSM/Semicond/index.html (April 2012).
6. R. G. Southwick III and W. B. Knowlton, IEEE Trans. On Device and Matls Rel. 6,2
(2006).
152
A P P E N D I X C
MODELING OPTIONS AND MATERIALS FILES
Capacitance – Voltage Model ing
The following are directions for executing the Hauser CVC program as well as a list
of options that can be used to customize the analysis.
/* File cvc.txt */
Execute file as cvc -options cvinput.file >out.dat
Input data should be in column format with voltage in the
first column. Program can use both HF and LF data in the
next two columns, or can use only a single C-V curve. If
only a single HF curve is used, polysilicon doping can not
be determined. If C-V data from a transistor (grounded source
and drain) is used, the program generates an approximate LF
curve. For transistor data use the options -on or -op to
indicate one curve and the type of device, (-on for n-channel
device and -op for p-channel device).
153
/* -a option scales the LF cap to agree with HF cap in inv */
/* -b use both HF and LF curves to optimize all parameters */
/* -c option for using corrected LF CV for Nss calculation */
/* -cg option for split capacitance Cgc analysis */
/* -d option sets properties of doping level and model */
/* -e option sets points to exclude for cmin evaluation */
/* -f option for including field oxide capacitance */
/* -g option includes gate polysilicon depletion effect */
/* -go option optimizes gate polysilicon doping using LF */
/* -gs option separately optimizes gate polysilicon LF */
/* -hp option deletes model for heavily inverted poly */
/* -i#,# option for specifying tox,wl on input line */
/* -l# option sets low fraction of C to ignore */
/* -lf option calculates the optimum value of poly doping */
/* -m option calculates theoretical CV curves */
/* -on,p option uses only one CV curve from a transistor */
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/* -p option for printing iteration values */
/* -q option for including quantum size effects */
/* -s option for skipping curve fit and outputting input */
/* -sp option for same type of polysilicon for gate */
/* -t option for changing temperature */
/* -u# option sets high fraction of C to ignore */
/* -w option sets gate work function */
/* -wl# option sets capacitor area wl */
/* -x option for experimentation with different models */
/* -z option deletes Ziegler correction on doping density */
/* combinations of options may be selected */
Materials files can also be combined with the CVC program to parameter changes due to
different substrate materials. The following is an example of the SiC materials file use for all
CV modeling in this work.
/* Basic semiconductor and oxide parameters */
/* Lines with '/*' as first entry are ignored */
eoxr = 3.9 /* Relative dielectric constant for insulator */
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esr = 9.66 /* Relative dielectric constant for semiconductor */
ni = 1.52e-8 /* Intrinsic carrier density */
nc = 1.69e19 /* Conduction band density of states */
nv =2.49e19 /* Valence band density of states */
ego = 3.265 /* Extrapolated T=0 semiconductor band gap */
alf1 = 6.5e-4 /* Temperature corfficient of band gap -- form eg =
ego - alf1*T^2/(T + to1) */
to1 = 1300. /* Coefficient for temperature dependancy of band gap
*/
/* Parameters for QM carrier confinement effects -- only used for -q or -
qo options */
/* Adjust values for best delta Vt agreement with experimental data */
/* Best values for materials other than Si are not known */
mon = 0.39 /* effective mass, m3, surface electrons Si */
mop = 0.82 /* effective mass, holes 100 Si */
/* Parameters for oxide penetration of wavefunction -- only used by -qo
option */
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mox = 0.55 /* oxide effective mass */
ebo = 3.15 /* Silicon-to-oxide barrier height */
/* Parameter for majority carrier charge level in Poisson's equation -- only
used by -d or -df option */
/* edor = 0.04 /* Ionization energy in eV from majority carrier band
*/
Mobil i ty Model ing
Similar to the CVC program, the following are directions for executing the Hauser
Mob2d program as well as a list of options that can be used to customize the analysis. The
SiC_Mob2d program used for modeling in this thesis is the same program but uses the
materials parameter for SiC. The SiC_Mob2d program also allows for a “-n” option that
allows for a set value of interface state density to be used in the fitting process.
/* File mob2d.txt */
/**********************************************************************
******* *
Program to evaluate MOS channel mobility, conductance or transconductance.
It will perform a least squares curve fit to experimental data on either
conductance or transconductance and return the best fit device and mobility
parameters.
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Programmer date comments
JRH 03/01/94 initial code
***********************************************************************
******* /
The program is executed from DOS by the line:
mob2d (-options) file1 (file2) (>output)
At least one file should be specified.
If no output is specified, output will be to the screen.
Options are listed below and combinations may be used.
The program will accept standard HP format or standard KI format
from either of the IV systems. It will also accept standard ASCII
two column format for the IV data.
If one has an output file generated by the cvc.exe program, the file
can be used to provide parameters to the mobility program. The
option to use is -i<filename> where <filename> is replaced by the output
file name generated by the cvc.exe program.
For standard execution, no options are needed.
/* -c option optimizes using conductance instead of gm */
/* -e option uses effective surface field for usr term */
/* -f option outputs full set of calculations */
/* -g option includes polysilicon depletion effect */
/* -i option inputs device and mobility parameters */
/* -ifile option inputs parameter file */
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/* -l# option selects optimization levels ( # = 1 to 4) */
/* -m option calculates an ideal mobility using 2D models */
/* -o option forces user to select optimization codes */
/* -p option for printing iteration values */
/* -q option for including quantum band increase effect */
/* -t# option select temperature for analysis */
/* -tr# option for printing transistor characteristics */
/* -k option uses ksr factor for surface roughness */
/* -v# option for specifying drain voltage */
/* -w# option for specifying W/L ratio */
/* -z option for subtraction out offset at vgs = 0.0 */
/* -n# option for interface state density #/cm^2/eV */
/* combinations of options may be selected */
If -i or -m option is selected, user is asked for the following input:
Input oxide thickness(nm) or
Input oxide thickness(nm), W(um) and L(um) or
Input oxide capacitance per unit area(F/cm**2) or
Input oxide capacitance(F), W(um) and L(um):
Input bulk doping((+)#/cm**3):
Input channel threshold (V) or
Input interface fixed charge ((+/-)#/cm**2):
Input channel threshold (V):
Input interface scatt density((+)#/cm**2):
Input bulk mobility(cm**2/V*sec):
Input surface scattering const(6.e14):
if -m option is selected, user is asked for:
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Input initial vgs, final vgs and vgs increment:
if program can not determine drain voltage for data, user is asked:
Enter drain voltage for first file (volts):
Enter drain voltage for second file (volts):
if not -i or -m option, user is asked to input:
Input oxide thickness(nm) or
Input oxide thickness(nm), W(um) and L(um) or
Input oxide capacitance per unit area(F/cm**2) or
Input oxide capacitance(F), W(um) and L(um) :
This is the standard request and the user may respond with any one of
the four formats. If W and L are not specified, the program assumes
values of 100um and 100um. The capacitance must be input in either
Farads for the total capacitance or Farads per unit area. The program
automatically determines which of the four formats you are using.