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ACPL-32JT and ACPL-302JDesign of Isolated Flyback Converter for IGBT Gate Driver

Application Note 5576

Contents

1. Introduction 2

2. Isolated Flyback Converter Block Diagram 2

3. Power Supply Specifications 3

4. Transformer Specifications, Snubber and Output Rectifier Diode 4

5. Input and Output Filter Capacitors 10

6. Loop Compensation 11

7. Soft Start 18

8. Reference Design for Typical Application 21

9. References 22

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ACPL-32JT and ACPL-302J Application Note 5576

1. IntroductionIsolated IGBT gate driver requires isolated power supply for safety isolation and level shifting. Unfortunately design of isolated power supply based on standard power control IC is not trivial. Special knowledge and significant verification efforts are required to customize the solution with discrete components which occupy large board space and increase probability of components failure. It is more desirable to integrate power conversion feature into gate driver for ease of design, small footprint and high reliability.

Broadcom® has released a new generation of isolated IGBT gate driver, ACPL-32JT/302J, with flyback controller integrated. By adding one small transformer designers can quickly build an isolated power supply tailored for gate driver application. A reference circuit for typical power supply and gate driver design is given in the last section.

2. Isolated Flyback Converter Block DiagramThe flyback converter uses direct duty cycle control in discontinuous mode. The output voltage is fed back through integrated optocoupler as shown in Figure 1 (US patent [1]).

Figure 1 IGBT Gate Driver with Integrated Flyback Controller

Vin Vcc2

D1D2

C1

D3

D4

X1

Vcomp

Vcc1SW

R4

R1

R2Vbus+MswRs

Cs

R2

Q1LED1

LED2

Msw

DGND

Vcc2

C3

Vee2ACPL-32JT/302J

C2

C4

Q2

Vbus-

5V

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A few immediate benefits of this topology can be observed.

Output voltage is regulated gate by gate with integrated feedback. Isolation boundary is well aligned with gate driver resulting compact PCB layout. Primary switch Msw is further integrated into the gate driver IC. Less discrete components and easy to design. Bipolar gate bias can be achieved by simple Zener (D4) and resistor (R4).

An example is given in the following section to illustrate detailed design procedure.

3. Power Supply SpecificationsThe following is a typical set of floating power supply specifications for IGBT gate driver in HEV and EV applications.

Vcc1 is designed to handle a large input supply range from 8V to 18V with an internal linear regulator in the primary side of the IC. Vcc2 provides both positive and negative gate bias.

The load current includes both biasing current of gate driver IC (Icc2) and dynamic gate driving current, Igate, where

fPWM is the PWM switching frequency of IGBT, Qg' is gate charge for gate voltage switching from Vee2 to Vcc2. In many cases, it is smaller than Qg specified by the IGBT datasheet, which measures the gate charge from –15V to 15V.

The minimum and maximum power supply’s load current Iomin and Iomax are:

Assuming power conversion efficiency:

The maximum input power and average current are:

For 3 phase inverter with 6 gates total input power and maximum input current are approximately 9W and 1.2A, respectively.

Vinmin = 8V, Vinmax = 18V (3-1)

Vcc2min = 18V, Vcc2max = 22V (3-2)

Igate = fPWM × Qg '(3-3)

For Qg' = 4 mC, fPWM = 10 kHz

Igate = 10 kHz × 4 mC = 40 μC (3-4)

Iomin = Icc2 ≈ 10 m (3-5)

Iomax = Icc2max + Igate = 10 + 40 = 50 mA (3-6)

η =75% (3-7)

Pinmax = (3-8)

(3-9)

Poutmax Vcc2max × Iomax 22 V × 50 mA75%

= 0.18 APinmax

Vinmin

1.47 W8 V

Iinmax =

1.47 W==

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4. Transformer Specifications, Snubber and Output Rectifier DiodeIn this section, we look into transformer specifications related to power conversion, for example, primary and secondary winding inductance as well as the turns ratio. These parameters are determined by maximum input power, minimum input voltage, switching frequency range, maximum duty cycle, and maximum primary current limit.

In Figure 1, switching frequency for primary winding is 60 kHz with min. and max. variation as follows [3]:

Turn-on duty cycle is hard limited to 50% – 60% by the IC. It is recommended that you use a max. duty cycle of 50% for maximum load to ensure good regulation of Vcc2.

In primary IC switch current is limited to 2 A typically to protect the switch from transformer short circuit failure. It is recommended that you design peak primary current up to 1.3 A to avoid a triggering of short circuit protection during normal operation.

Transformer should be designed to support power, Pin, larger than maximum power, Pinmax , required by application.

We can further derive:

A practical design must satisfy Lpmin ≤ Lpmax, for example:

or

We define:

As Pinmax = 1.5W <Pinlim = 1.84W; therefore, equation (4-7) is satisfied. It is practical to proceed with transformer design. Otherwise Vinmin should be raised to increase the input power limit, for example, setting Vinmin = 16V for 3.7W input power.

The limit of output power and current can be obtained as follows.

fsmin = 40 kHz, fstyp = 60 kHz, fsmax = 80 kHz (4-1)

Dmax = 50% (4-2)

Ippk ≤ Iswpk = 1.3 A (4-3)

Poutlim = η × Pinlim = 75% × 1.84W = 1.38W (4-9)

(4-4)Pin = × Dmax2 ≥ Pinmax× Lp × Ip2pk × fs = Vin2

Lp × fs12

12 ×

≤ Lp ≤ (4-5)2 × Pinmax

Iswpk2 × fsmin× Dmax2 = LpmaxLpmin = Vin2min

Pinmax × fsmax

12

×

(4-6)≤ 2 × Pinmax

Iswpk2 × fsmin× Dmax2Vin2min

Pinmax × fsmax

12

×

Pinmax ≤ (4-7)fsmin

fsmax× Vinmin × Iswpk × Dmax ×

12

Pinlim = fsmin

fsmax× Vinmin × Iswpk × Dmax ×1

2= 40 k

80 k× 8 × 1.3 × 50% ×1

2 1.84 W (4-8)

Poutlim

Vcc2max Iolim = = 1.38 W

22 V= 63 mA (4-10)

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4.1. Determine Primary Inductance

From Equation (4-5),

Larger inductance reduces peak primary winding current, hence select:

Based on Equation (4-4), the peak primary current and maximum duty cycle can be estimated as:

4.2. Determine Secondary Inductance

Secondary winding inductance should be selected to store suffi cient output power, Pout, and observe discontinuous operation boundary.

Hence:

Next determine practical turn’s ratio to limit the fl yback voltage and meet absolute max voltage rating of primary switch. Defi ne transformer turns ratio,

The peak voltage at Vsw includes both input voltage, Vin, and snubber voltage, Vsn. The snubber voltage is madeof fl yback voltage, Vfb, and overvoltage due to transformer leakage inductance, Vlk, as shown in Figure 2.

Lp = 60 μH (4-13)

Lpmin =

(4-11)

(4-12) 43.4 H= 2 × 1.471.32 × 40 k

2 × Pinmax

Iswpk2 × fsmin

Lpmax = × 50%2 = 68.2 H82

2 × 1.47 × 80 kVin2min

Pinmax × fsmax×1

2× Dmax2 =

Ippk =

Dmax =

(4-14)

(4-15)= 2 × 1.47 × 60u × 80k8

= 2 × 1.4760u × 40 k

= 46.9%

= 1.11 A

2 × Pinmax × Lp × fsmax

Vinmin

2 × Pinmax

Lp × fsmin

Pout = (4-16)× Ls × Ispk2 × fs = × (1-Dmax)2 ≥ Poutmax12

12 × Vcc22

Ls × fs

(4-17)= 460 H× (1-Dmax)2 =Ls ≤12 × 182 × (1 - 50%)2

2 × 1.1 × 80kVcc22min

Poutmax × fsmax

(4-18)Nt = NpNs = Lp

Ls

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Figure 2 Primary Switch Circuits and Waveform

where Vlk = α × Vfb, α is an arbitrary factor typically ranging between 0.2 and 1, Vswabsmax is specified in ACPL-32JT/302J's datasheet [3].

Substitute Equation (4-21 to (4-20), we have

Assuming α = 0.5, Vfmax = 1V,

Based on Equations (4-17) and (4-25), the secondary inductance should be between the 222 μH and 460 μH. It is shown in the next section that a larger turns ratio or smaller secondary inductance is preferred to reduce the breakdown voltage requirement for the output diode.

Vsw = Vin + Vsn ≤ Vswabsmax (4-19)

Vsn Vswabsmax – Vinmax = 36 – 18 =18V (4-20)

Vsn = Vlk + Vfb = (1 + α) × Vfb = (1 + α) × Nt × (Vcc2 + Vf ) (4-21)

(1 + α) × Nt × (Vcc2 + Vf ) ≤ Vswabsmax – Vinmax (4-22)

Vin“flyback”

–+

Vfb = Nt * (Vcc2 + Vf)

Vsw

Vlk

+

–

k * Lp

Llk = (1-k)* Lp

fsVin

VsnVsw

Co

Ls

Rco

Do

Csn Rsn

Vcc2

+ Vf –

(4-23)Nt ≤ Vswabsmax - Vinmax

(1 + ) × (Vcc2max + Vfmax )= Ntmax

(4-25)

(4-24)Nt ≤ Ntmax = 18(1 + 0.5) × (22 + 1)

= 0.52

Ls = LpNt2 ≥ Lp

Nt2max = 60u

0.522 = 222 H

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4.3. Output Diode

The breakdown voltage of an output diode is determined by:

Choose a larger Nt for a lower VbrDo, for example, Nt = 0.48.

In practice, a 30% margin should be added and a 80-V diode should be selected.

Finally, secondary inductance can be calculated as:

4.4. Transformer Information

Customized transformers designed for Broadcom’s ACPL-32JT/302J are available from Hitachi and Sumida. Table 1 lists the contact information for the companion transformers. HFTR3DA and HA00-14013LFTR are available for sampling. Contact your Broadcom local sales representative for more information.

Table 1 Contact Information for Companion Transformers

Manuafacturer Part #/Photo Isolation Voltage WW Contacts

Hitachi Metals HFTR2DA HFTR3DA

2.5 kVrms (1 min) 3.75 kVrms (1 min)

[email protected] Website: http://www.hfe.co.jp/products.htm

Sumida Corp. AX05-13-048 2.5 kVrms (1 min) [email protected]

VbrDo = (4-26)Vinmax

Nt + Vcc2max

(4-27)VbrDo = 180.48

+ 22 60V

(4-28)Ls =LpNt2 =

60u0.482 = 260 H

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TT Electronics HA00-10043ALFTR (AEC-Q200)HA00-14013LFTR (AEC-Q200)HM210-05K060LFTR

2.5 kVrms (1 min)

2.5 kVrms (1 min)

5.0 kVrms (1 min)

US Mike Graham EUKlaus Zwerschina AP Janson Chuen

[email protected]

[email protected]

[email protected]

Mitsumi TBD-C4C460NX (AEC-Q200)

2.5kVrms (1 min) Global Contact: Mr. Michio OtsukaRegional Contacts:USMr. Kazuhisa HiroseEUMr. Kazuhisa HiroseChinaMr. Shinichi HigakiKoreaMr. Kang Suk JeaJapanMr. Michio OtsukaSouth East AsiaMr. Ryo Nakanosono

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

[email protected]

Pulse Electronics PH0416NL (AEC-Q200)PH9363NL PH9496NL (AEC-Q200)

5.0 kVrms(1 min) 2.5 kVrms(1 min) 2.5 kVrms(1 min)

Omara, M [email protected]

MFS Technology ER11T216321 2.5 kVrms(1 min) Contact:[email protected]

Table 1 Contact Information for Companion Transformers (Continued)


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4.5. Snubber Network

Flux loss in a practical transformer results in leakage inductance as shown in Figure 2. It can be obtained by measuring the primary inductance while shorting the secondary winding. If the coupling effi ciency, k, is known it can be calculated as

Energy stored in leakage inductance during turn-on has to be dissipated. Otherwise drain voltage Vsw of primary switch will rise to break down the switching transistor. Rsn and Csn in Figure 2 form Snubber circuit to clamp the Vsw voltage.

Value of Rsn and Csn can be calculated as follows [2].

Assuming k = 99%

Select:

The power rating of Rsn is:

Csn is selected based on desired voltage ripple. Let Vripple = 1V.

Wurth Elektronik 750343893 (Rev00)750343877 (Rev01)

5.0kVrms(1min)2.5kVrms(1min)

Contact: Stephen Cheung

[email protected]

Llk = (1 – k) × Lp (4-29)

Llk = (1 – 99%) × 60u = 0.6 μH (4-30)

Vfb = Nt × (Vcc2max + Vfbmax ) = 0.48 × (22 + 1) = 11V (4-31)

Vlk = α × Vfb = 0.5 × 11 = 5.5V (4-32)

Rsn = 2k (4-34)

Table 1 Contact Information for Companion Transformers (Continued)


(4-33)2 × Vsn × VlkIp2pk × Llk × fsmax

2 × 18 × 5.51.12 × 0.6u × 80k

= 3.4kRsn ≤ =

(4-35)PRsn =182

2kVsn2

Rsn 162 mW=

(4-36)Csn ≥ 225nVsRsn × fsmin × Vripple = 18

2k × 40k ×1

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5. Input and Output Filter CapacitorsOutput filter capacitor is determined by Qg’ of IGBT and switching ripple voltage tolerance, Vripple.

For Vripple = 0.5V, Qg' = 4uC:

Select:

Similarly input filter capacitor is determined by maximum input current and ripple voltage tolerance.

Select:

Vripple × Co ≥ Qg’ (5-1)

Co = 10 μF (5-4)

Cin = 10 μF (5-7)

Co ≥ (5-2)Qg'

Vripple

Co ≥ (5-3)4u0.5

= 8 F

Vripple × Cin ≥ (5-5)

(5-6)

Iinmax

fs

Cin ≥ Iinmax

Vripple × fsmin= 0.18

0.5 × 40k= 9 F

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6. Loop CompensationIsolated flyback converter is essentially a feedback control loop, whose loop dynamics has to be carefully designed to ensure loop stability. Figure 3 shows a detailed block diagram of Broadcom’s isolated flyback converter architecture.

The feedback loop can be broken at duty cycle control voltage node Vcomp. The forward path includes path from Vcomp to Vcc2. The feedback path includes path from Vcc2 to Vcomp.

Figure 3 Block Diagram of Broadcom’s Isolated Flyback Converter

“flyback”

Vin

Vcc2

RsnCsnCinCo

Ls

Rco

Lp

Vsw

Flyback Controller Block Diagram

Ramp GenVcc1

Vcc2

5V

fS =60kHz

PhotodiodeFeedback

Msw

IcpRsen

U1

Feedback

AmplifierDecoder R1

R2

Vcomp

Rs

Vcc2s

Encoder

Ramp Gen-IcpCsCp

Start

U2

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6.1. Determine Forward Transfer Function from Vcomp to Vcc2

The forward path mainly comprises of a Ramp comparator, U1, primary switch, Msw, and power transformer.

Vcomp is the duty cycle control voltage generating proportional turn-on duty at Vsw. The waveforms of Vcomp, Ramp Generator and Vsw are shown in Figure 4.

Figure 4 Waveforms of the Primary Controller

1.25V

4V

D

Vsw

Vcomp

Vsaw

Maximum duty cycle limited to 50%

dD/dVcomp = 100%/2.75=1/2.75

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It can be seen that the transfer function from Vcomp to switching duty cycle, D, is

In actual IC the maximum duty at Vsw is limited to 50% as shown in the Vsw waveform.

The transfer function from Vsw to secondary output current Io is derived from following basic transformer equations.

The transconductance from Vcomp to secondary output current Io is:

Total forward transfer function from Vcomp to secondary output voltage Vcc2:

For Rco << Ro Gfw can be approximated as:

Pout = Io2 × Ro (6-3)

Pout = η × Pin (6-4)

(6-1)dDdVcomp

= 100%4 - 1.25

= 12.75

(6-2)Pin = × Vin2 × D2 ×1

Lp × fs12

(6-6)

(6-7)

Io2 × Ro = × (6-5)

2 × Lp × fs × Ro

× Vin2 × D2 ×12

1Lp × fs

Io = Vin × D ×

2 × Lp × fs × Ro= Vin ×dIodD

Vcc2IoWhere Ro = , hence

(6-8)η2 × Lp × fs × Ro×Vin

2.75Gtrxm = dIo

dVcomp= =dIo

dDdD

dVcomp×

(6-9)

(6-10)

Gfw = dVcc2dVcomp

= dIodVcomp

×Ro × (Rco +

Ro + Rco +

1s × Co )

1s × Co

Gfw = Gtxfm × Ro × 1+ s × Rco × Co1 + s × (Ro + Rco) × Co

(6-11)Gfw = Gtxfm × Ro × 1 + s × Rco × Co1 + s × Ro × Co

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6.2. Determine Feedback Transfer Function from Vcc2 to Vcomp

Vcc2 voltage is sensed by potential divider R1 and R2 inside the IC as shown in Figure 3. The sensed voltage Vcc2s is converted into PWM signal at fixed frequency of 150 kHz (with ± 5% dithering to spread EMI radiation) and transmitted to the logic IC optically. Based on the received PWM signal primary IC controls the charge pump current and converts the PWM signal back to continuous voltage inverse proportional to Vcc2.

Figure 5 illustrates the detailed Vcc2s to Icomp conversion process.

Figure 5 Waveforms from Vcc2s to Icomp

1.25V

4V

D

Icp

Vcc2s

Vsaw

-Icp

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Transconductance from Vcc2s to Icomp can be derived as follows.

During normal operation Icp = 10 μA. A negative sign indicates current sinking into Vcomp pin.

Total feedback transfer function from Vcc2 to Vcomp is:

For Cs >> Cp Gfb can be approximated as:

Combining Gfw and Gfb, we have the loop gain as:

(6-12)

(6-14)

(6-13)

dDdVcc2s

100%4 - 1.25

12.75

= =

dIcompdD

-Icp - Icp100%

-2 × 10u100%

= = = -20u

dIcompdVcc2s

dIcompdD

12.75

= = -7.27uGcomp = dDdVcc2s

× = -20u ×

(6-15)R2R1 + R2

1s × (Cp + Cs) Cp × Cs

Cp + Cs

× Gcomp × Gfb = 1 + s × Rs × Cs×1 + s × Rs ×

(6-16)R2R1 + R2

1s × Cs

× Gcomp × Gfb = 1 + s × Rs × Cs1 + s × Rs × Cp

×

(6-17)R2R1 + R2

1s × Cs

× Gcomp × Gloop = Gtxfm × Ro × 1+ s × Rs × Cs1 + s × Ro × Co

× 1 + s × Rco × Co1 + s × Rs × Cp

×

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As Rco × Co, Rs × Cp are very high frequency zero and pole they can be ignored for frequency compensation analysis. Rs × Cs should be designed to cancel the output pole Ro × Co for loop stability.

As Ro changes during application Rs and Cs can be placed between minimum and maximum output poles.

where:

A typical placement of Rs × Cs can be the geometric mean of Romin × Co and Romax × Co.

Choose Cs = 22 nF (to be explained in Section 7. Soft Start).

Choose slightly larger Rs for faster large signal response.

Close loop gain equation Gloop can be used to construct a small signal model in Figure 6.

Figure 6 Small Signal Model of Flyback Converter Loop

Romin × Co < Rs × Cs < Romax × Co (6-18)

Rs = 470k (6-23)

(6-19)Vcc2Icc2 + Igate

2010m + 40m

Romin = = 0.4k=

(6-20)Vcc2Icc2

2010m

Romax = = 2k=

Rs × Cs = √ Romin × Romax × Co (6-21)

(6-22)Rs = √ Romin × RomaxCoCs

= √ 0.4k × 2k 10u22n

×× = 406k

Vcomp Vcc2 Vcc2s Vcomp’

Vac = 1Phase = 0

Ro0.4k ~ 2k

Co10u

Rco10m

R1

R235k

Rs

Cs

Cp

Gcomp= -7.27u

232k

Gtrxm (Vin,Ro)

IoIcomp

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Close loop bandwidth and phase margin can be easily found out by running AC simulation on this circuit.

Table 2 shows an example of AC simulation result. Minimum phase margin should be greater than 45 degrees.

Table 2 Close Loop Bandwidth and Phase Margin Simulation (Condition = 75%, Lp = 60 μH, fs = 60 kHz)

Vin (V) Ro (kOhm) Gtrxm Rs (kOhm) Cs (nF) Co (uF) fc (Hz) Phase Margin (Degree)

8 2.00 0.021 470 22 10 152 78

8 0.40 0.047 470 22 10 314 73

12 2.00 0.031 470 22 10 215 76

12 0.40 0.070 470 22 10 427 71

18 2.00 0.047 470 22 10 291 69

18 0.40 0.106 470 22 10 625 53

8 2.00 0.021 85 105 10 28 74

8 0.40 0.047 85 105 10 54 107

12 2.00 0.031 85 105 10 44 78

12 0.40 0.070 85 105 10 86 102

18 2.00 0.047 85 105 10 61 80

18 0.40 0.106 85 105 10 131 96

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7. Soft StartBoth primary and secondary control ICs are implemented with under voltage lockout (UVLO) circuits to prevent unwanted logic state during power startup.

The UVLO threshold of primary IC (UVLO1) is set to 2.5V typically. When Vcc1 is lower than UVLO1 threshold Vcomp is pulled low to disable primary switch. Above UVLO1 the charge pump current starts to charge the compensation network, Cs, Rs, and Cp. The charge pump current starts at 3 μA for 6.6ms, steps up to 6 μA for 3.3 ms, and increases to 10 μA at final step as shown in Figure 7.

Figure 7 ACPL-32JT/302J Startup Waveforms

Vcomp voltage exhibits a step jump at transition of each current step. The amount is equal to current step multiplied by Rs. During each step Vcomp ramps up due to charging of Cs.

When Vcomp rises to 1.25V at time T1 primary switch Msw is turned on with increasing duty cycle proportional to Vcomp voltage. As a result secondary output voltage Vcc2 ramps up.

Before Vcc2 is raised to UVLO2 (typical 12V) at time T2 Vcomp is 100% charged by sourcing current Icp. After T2 Vcc2 feedback loop is closed and charge pump starts to respond to PWM feedback of Vcc2. As a result the net Icomp current drops causing voltage at Vcomp dropping. The normal load regulation begins and Vcc2 will eventually rise to its final value of 20V.

The design consideration for proper start-up is to ensure power conversion only starts when Vcc1 is above its turn-on threshold at time T1. This can be achieved by designing Vcomp voltage lower than 1.25V before T1 by sizing Rs and Cs following the design guidelines that follow.

Icp1=3uA

6.6ms

Icp

Vin/Vcc112V

Soft Start Normal regulation

Icp2=6uA

3.4ms

Icp3=10uA

Vcomp

Vcc2 UVLO2

1.25V

0 6.6ms 10ms

T1 T2

Vcc1_th <= 6V

Tr6

T0

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7.1. Estimating Vcomp Voltage During Start-up

From 0 to 6.6 ms:

From 6.6 ms to 10 ms:

For t > 10 ms:

where Icp1 = 3 μA, Icp2 = 6 μA, Icp3 = 10 μA.

7.2. Rs and Cs Are Related by Equation (6-22), hence Rs can beSelected By

7.3. Determine Cs Based on Rise Time of Vcc1 from 0 to 6V, Tr6

If Tr6 ≤ 66 ms:

For 6.6 ms < Tr6 ≤10 ms:

For Tr6 > 10 ms:

(7-1)Vcomp(t) = × t + Icp1 × RsIcp1Cs

(7-2)Vcomp(t) = × (t - 6.6m) +Icp2Cs

× 3.3m + Icp2 × RsIcp1Cs

(7-3)Vcomp(t) = × (t - 10m) +Icp3Cs

× 6.6m + Icp3 × RsIcp1Cs

× 3.3m +Icp2Cs

(7-4)Rs = √ Romin × Romax × CoCs

× Tr6 + Icp1 × Rs ≤ 1.25Icp1Cs

(7-5)

Cs ≥ Icp1 × Tr6 + Icp1× √ (Romin × Romax) × Co1.25

(7-6)

(7-7)× (Tr6 - 6.6 m) +Icp2Cs

× 6.6 m + Icp2 × Rs ≤ 1.25Icp1Cs

(7-8)Cs ≥ Icp2 × (Tr6 - 6.6 m) + Icp1 × 6.6 m + Icp2 × √Romin × Romax × Co1.25

(7-9)× (Tr6 - 10m) + Icp2Cs

Icp1Cs

× 3.3m + × 6.6m + Icp3 × Rs ≤ 1.25

(7-10)Cs ≥ Icp3 × (Tr6 - 10m) + Icp2 × 3.3m + Icp1 × 6.6m + Icp3 × √Romin × Romax × Co1.25

Icp3Cs

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Example 7-1—Tr6 = 0.2 ms

Example 7-2—Tr6 - 1.2 ms

Smaller Rs and bigger Cs will reduce bandwidth substantially as shown earlier in Table 2. Transient response to load change can be sluggish. It is preferred to select lower Cs and high Rs for larger close loop bandwidth and fast load change response. If this condition cannot be met due to slow rise time of Vcc1 simple circuit in Figure 8 helps speeding up the rise time of Vcc1.

Figure 8 External UVLO1 Circuits

(7-14)Cs ≥ 3u × 0.2m + 3u × √ (0.4k × 2k) × 10u1.25

= 22n

(7-15)Rs = √ (0.4k × 2k) ×10u23n

= 407k

(7-17)

(7-16)Cs ≥ 10u × (10.2m - 10m) + 6u × 3.3m + 3u × 6.6m + 10u × √ (0.4k × 2k) × 10u1.25

= 105n

Rs = √ (0.4k × 2k) × 10u105n

= 85k

To transformer

Vin Vcc1

Rb 1k

Output current ≥ 100mA

ACPL-32JT/302J

Rb

6V

1k

Broadcom- 20 -


8. Reference Design for Typical ApplicationFigure 9 provides a reference design for a typical IGBT gate driver application.

Figure 9 Reference Design of Typical IGBT Gate Driver for HEV/EV Powertrain Inverter

Broadcom has developed an evaluation board based on the reference design for customer’s quick prototyping and design verification.

The circuit shown above demonstrates the following performance at typical condition.

The reference circuit has been tested with Fuji IGBT module M652/M651 and Infineon Hybrid Pack 2 (FS800R07A2E3). Evaluation results for both Fuji and Infineon IGBT modules are available upon request.

SPICE models for both DC-DC converter and gate driver are available for circuit simulation verification.

Visit the Broadcom website (www.broadcom.com) or contact a Broadcom local sales representative for more technical support.

Table 3 Electrical Performance of Reference Design

Description Performances

Input Voltage Range 8V–1 V

Average Input Current 200 mA

Positive Gate Bias Voltage 15V

Negative Gate Bias Voltage –5V

Power Supply Output Current @Vin = 8V 60 mA

Power Supply Output Current @Vin = 12V 100mA

4.7k

330p

8 - 18V/0.18A 20V / 60mA

LED2+

VCC2

VEE2

VEE2

VO

VE

SW

VEE1

AN

CA

FAULT

UVLO

DESATVCC1

COMP

+ 5V

Co=10u

Ls=260uCsn =220n

Rsn =2k

Lp =60u

Rs=470k

4.7k

Cp=330p

Cs=22n

0.1u

330p

1k

330p

BROADCOM: ACPL-32JT/302J

CLAMP_SS

20u

20u

15V

2k

HV Diode

Cin =10uF

150

150

PWM MCU

DiagnosticMCU

0.1u

5

20

Hitachi Metals: HFTR2DASumida: AX05-13-048

TT Electronics: HA00-10043(A) LFTR/14013LFTRMitsumi: TBD-C4C460NX

Pulse Electronics : PH0416NL

+ 5V

Broadcom- 21 -


9. References1. US Patent No: US 8462003 B2, Jun.11, 2013, “Transmitting and Receiving Digital and Analog Signals across Isolator”, by Gek

Yong Ng and Richard Lum.

2. LT1070 Design Manual, Application Note 19, Carl Nelson, June 1986.

3. ACPL-32JT/302J Datasheet, Broadcom.

IMPORTANT NOTICE!

Information presented in this document is intended to assist circuit and system design with Broadcom optocouplers. It shall not be regarded as warranty of any specifi cation and functionality. The recipient of this document owns the responsibility of verifying the description of information. Broadcom hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all information given in this document.

DISCLAIMER: Broadcom’s products and software are not specifi cally designed, manufactured, or authorized for sale as parts, components, or assemblies for the planning, construction, maintenenace, or direct operation of a nuclear facility or for use in medical devices or applications. The customer is solely responsible, and waives all rights to make claims against Broadcom or its suppliers, for all loss, damage, expense, or liability in connection with such use.

Broadcom- 22 -

For product information and a complete list of distributors, please go to our web site: www.broadcom.com.

Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU.

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Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

AV02-4412EN – April 13, 2018

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