active-hdl 8.3sp1 release notes

R e l e a s e N o t e s

Active-HDL 8.3sp1

Release Notes

w w w . a l d e c . c o m

http://www.aldec.com/

This page is intentionally left blank.

T A B L E O F C O N T E N T S

Table of ContentsWhat's New in Version 8.3? .......................................................................................................................... 4

Licensing ................................................................................................................................................. 4 Compiler and Simulator ........................................................................................................................... 4 Simulation Database ............................................................................................................................. 12 LINT/ALINT Support .............................................................................................................................. 13 Libraries ................................................................................................................................................. 13 Design Flow Manager ............................................................................................................................ 14 Statement/Branch Coverage ................................................................................................................. 15 Path Coverage ....................................................................................................................................... 16 Expression Coverage ............................................................................................................................ 16 Scripts .................................................................................................................................................... 17 Block Diagram Editor ............................................................................................................................. 19 HDL Editor ............................................................................................................................................. 20 Waveform Viewer .................................................................................................................................. 20 Active-HDL Interfaces and Wizards ....................................................................................................... 22 Documentation ...................................................................................................................................... 23 Others .................................................................................................................................................... 23 Problems Corrected in Version 8.3 ........................................................................................................ 24

Active-HDL™ 8.3 provides many new features and enhancements that simplify team-based design, increase design productivity and the speed of behavioral, RTL, and timing simulation of VHDL, Verilog®, SystemC™, SystemVerilog and EDIF projects.

Active-HDL 8.3 is offered in an FPGA vendor-independent edition and supports all leading C/HDL synthesis and implementation tools which can be started directly from the Active-HDL environment. The installation program automatically installs all system libraries and allows selecting both target FPGA technology and vendor-specific libraries required for running HDL simulation.

The release notes describe new options and updates available in Active-HDL 8.3. Not all features and enhancement described are available in every product configuration or OEM edition. The product license file provides configuration information for the features to which you have access. Please, refer to Active-HDL Configurations for more information about available product configurations.

What's New in Service Pack 1 for Version 8.3?The following is a brief overview of new features and changes introduced to Service Pack 1 for Active-HDL 8.3 (BUILD 2120.SP1.14, 10/5/2010)

Licensing Active-HDL 8.3 may require validation of your existing maintenance contract. The latest version

requires a valid maintenance contract as of 9/1/2010. For more information refer to the License Maintenance section of the Licensing chapter.

LibrariesThe following changes have been introduced to the system and vendor-specific libraries delivered with Service Pack 1 for Active-HDL 8.3:

Updated Libraries

HDL Synthesis1. Synopsys® FPGA Synthesis D-2010.09

Implementation1. Actel® Designer 9.0 SP22. Altera Quartus® II 10.0 SP13. Xilinx ISE™ 12.2

NOTES: 1. For the complete list of all the pre-compiled vendor libraries delivered with Active-HDL 8.3, refer to the Vendor-Specific Libraries chapter.2. For additional information about availability of discontinued libraries, please contact Aldec Technical Support at [email protected].

4 of 28 Active-HDL 8.3sp1

mailto:[email protected]

http://www.aldec.com/products/active-hdl/configurations

http://www.aldec.com/products/active-hdl/configurations

Design Flow Manager New Flowcharts

HDL Synthesis1. Xilinx ISE/WebPack 12.2 XST™ VHDL/Verilog

Physical Synthesis1. Xilinx PlanAhead 12.2

Implementation1. Xilinx ISE/WebPack 12.2

Updated Flowcharts

HDL Synthesis1. Synopsys® Synplify Premier/Premier with Design Planner D-2010.03 (supports FPGA Synthesis D-2010.03-SP1-1)

NOTE: For additional information about availability of discontinued flowcharts, please contact Aldec Technical Support at [email protected].

ScriptsThe following changes have been introduced to internal macro commands:

The -ignore_pragma argument has been added to the syntax of the acom command. The new argument specifies that the compiler should ignore pragmas of a label defined in the command line. (SPT48050)

The nowhen command is now supported in the Tcl and Compatibility mode.

The -generates argument has been added to the syntax of the bdeinfo command. The new argument adds to the report, the information about the VHDL generate statements used on a block diagram.

Block Diagram Editor The preliminary support for the generate statement has been added. The statement allowing

iterative or conditional elaboration of a portion of a block diagram (i.e. enclosed block diagram items such as fubs, symbols, wires, buses, signal assignments) is represented by the new Generate text blocks. The Generate If block uses the if <condition> generate scheme compliant with VHDL 2002 (IEEE Std 1076™-2002). The Generate For block uses the for <parameter> in <range> generate generation scheme. (The case <expression> generate statement is not yet supported.) The special HDL text blocks are available in the Diagram | VHDL menu. (SPT14419, SPT19500, SPT22514, SPT22916)

The wires, buses, terminals, and pins of fubs and symbols on Verilog block diagrams can now be declared as objects of the signed type. To change the defaults, open an object properties dialog box and select a type from the Type name list box. (SPT46195)

Active-HDL 8.3sp1 5 of 28


Active-HDL Interfaces and WizardsThe following changes and improvements have been made to the built-in simulation interfaces to third-party tools:

The mechanism of starting simulation from the Xilinx ISE environment and executing simulation tasks in Active-HDL has been improved in Service Pack 1 for version 8.3. Now, instead of downloading a macro file, you can use a ready-to-use script. The installation program delivers all files required to run Active-HDL as the default simulator in the Xilinx environment and, in the comparison to a previous script, no additional configuration steps are needed. After a simulation netlist is generated, Active-HDL is launched from ISE Project Navigator by using the xilinx_ise.bat file stored in the $aldec\bin subdirectory. The file contains necessary commands needed to run Active-HDL, create a workspace/design, and add all files required for compilation and simulation. For the detailed information on how to launch Active-HDL from Xilinx ISE Project Navigator and run behavioral or timing VHDL, Verilog, or SystemVerilog simulation within the Active-HDL environment, refer to the Starting Active-HDL as Default Simulator in Xilinx® ISE Design Suite topic (Active-HDL Help | Appendices).

Problems Corrected in Service Pack 1 for Version 8.3VHDL Compilation and Simulation

The following defects resulting in occurrence of application error, internal compiler or simulator errors were fixed: SPT48826, SPT48863, SPT48945.

Verilog/SystemVerilog Compilation and Simulation

The following defects resulting in occurrence of application error, internal compiler or simulator errors were fixed: SPT48819.

Coverage Analysis

In the previous version of Active-HDL, merging more than two databases with the use of the multiple -path arguments did not work correctly. Service Pack 1 resolves this issue. (SPT48645)

Design Flow Manager

Previously, if the Altera Quartus II Synthesis & Implementation flowchart was selected, a synthesis process failed at analysis stage when additional design files were added to the Files tab of the Synthesis Options dialog box and then incorrectly passed to Quartus II. An issue with passing files to synthesis is now revised. (SPT48602)

Active-HDL Interfaces and Wizards

Previously, reading a cell from a MATLAB array and writing it to an HDL variable was impossible. Now, this issue is revised. (SPT48944)

The issue with the IP CORE Generator returning an error while generating cores was revised. (SPT48794)

Block Diagram Editor

Previously, the use of ports of the composite types might cause issues while reopening *.bde source files. Now, the issue is fixed. (SPT47816, SPT48040)

The Add Stubs and Add Terminals options added objects with hidden names. Now, generated signals and terminals have their names visible by default. (SPT47830)

In the previous version of Active-HDL, the Block diagram Editor incorrectly handled the case in


names of VHDL instances, which might result in parse errors of *.bde source files. Now, the issue is fixed. (SPT46197)

Previously, if components with ports of the composite type (array or record) were used on a block diagram, the manually placed buses connecting such ports were automatically named as NETxxx. Now, the names correspond to a port type, i.e. RECORDxxx or ARRAYxxx is assigned to a bus. (SPT47831)

An issue with the Update Composite Types option was revised. (SPT48362)

An issue with changing an actual value of a module parameter with the use of the Compare Symbol with Contents option in case when the Verilog Standard option in the Generation category of the Preferences dialog box was set to 1364-2001 (ANSI) was corrected. (SPT48006)

Accelerated Waveform Viewer

Previously, an attempt to open a corrupted simulation database resulted in an application error. Now, this issue is fixed. (SPT49050)

Scripts

Previously, simulation was not terminated by the stop command used inside when, if a Tcl script had been executed by using the do -tcl command. The issue is now revised. (SPT48782)

An issue with terminating an execution of Tcl scripts by using the Break button causing an application error was revised. (SPT48864, SPT48980)

Graphical User Interface

Previously, the use of the Version Info button in the About window caused an application error. Now, this issue is revised. (SPT48910)

Licensing

In the previous version of Active-HDL, the Diagnose License utility (Help | License Information) displayed incorrectly the number of available licenses if product features included in a license file were defined by using the FEATURE and INCREMENT entries of different maintenance dates. Service Pack 1 corrects this issue. (SPT48719)

Documentation

The Configuring and Registering SCC Interface in Active-HDL topic describing configuration of the Subversion (SVN) interface was updated. Refer to the ... | Active-HDL Tools | Source Revision Control chapter for details. (SPT48697)

The description of the VCP2515 warning has been added. The msginfo command also provides the explanation for the warning. (SPT48936)

Others

The Add file to folder option (in the Add Files dialog box) did not create local copies of original files but referenced them by shortcuts in the Files tab of the Design Browser window. This issue is now resolved. (SPT48801)

What's New in Version 8.3?The following is a brief overview of new features and changes introduced to Active-HDL 8.3 (BUILD 2118, 7/23/2010)


Licensing Active-HDL 8.3 may require validation of your existing maintenance contract. The latest version

requires a valid maintenance contract as of 7/1/2010. For more information refer to the License Maintenance section of the Licensing chapter.

Compiler and SimulatorNOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries, all user-defined libraries should be re-compiled after the installation of Active-HDL 8.3. The installation program of version 8.3 delivers and installs only the updated system and vendor-specific libraries that do not require re-compilation after Active-HDL is installed.All existing designs will not have any problems associated with re-compiling the libraries. If you update Active-HDL to version 8.3 and do not re-compile your design libraries, the following error message will be displayed in the Console window:

# ELBREAD: Warning: Files created by the old version of the compiler found.# ELBREAD: Error: Library '<library_name>' has incompatible format. Recompile all library units.

VHDL Compilation and Simulation

Support for VHDL 2008 (IEEE Std 1076™-2008) has been extended. The IEEE library delivered with Active-HDL now contains all packages required by the standard. The following new language features are supported in this version of Active-HDL:

The if generate construct can now contain optional elsif and else branches, for example:

genif: if( g = 0 ) generate U1: behav port map( A, B, D, OVF, CLK );elsif( g <= 32 ) generate gates: for i in 1 to g generate --.. end generate;else generate assert( FALSE ) report "Component not implemented yet." severity failure;end generate;

The case generate statement is now supported. It allows instantiating different components based on the value of the case expression, for example:

gencase: case g generate when 1 => U1: bhv_v1 port map( A, B, D, OVF, CLK ); when 2 => U1: bhv_v2 port map( A, B, D, OVF, CLK ); when others => assert( FALSE ) report "Incorrect version number." severity failure;end generate;

The following changes in the names of the packages and the source files of the


IEEE_PROPOSED library have been introduced:

The math_utility_pkg package has been renamed to fixed_float_types. The fixed_float_types package is now delivered along with the precompiled library.

The math_utility_pkg.vhdl source file has been renamed to fixed_float_types.vhdl.

The to_suv() function in the fixed_pkg package has been renamed to to_sulv().

The order of the parameters in the following conversion functions of the float_pkg package has been changed:

to_integer()

to_unsigned()

to_signed()

to_ufixed()

to_sfixed()

to_real()

In order to check the current order of the parameters, you can open the float_pkg_c.vhdl source file in the HDL Editor by using the View Source: Text context menu option in the Library Manager window.

Interface packages are now supported and can be declared in uninstantiated packages (i.e. in packages that contain a generic clause). When the uninstantiated package is instantiated, the actual for the interface package is specified as one of the generics.The support of interface packages allows for example, writing algorithms at a high level using types and subprograms that are not yet known and will be specified later, at package instantiation. This new functionality is used in the IEEE library, where the fixed_pkg interface package is used in the float_pkg package. The interface package is declared in the float_generic_pkg package.

package fixed_pkg is new IEEE.fixed_generic_pkg generic map (<>);

The interface package declaration specifies that fixed_pkg must be an instance of the IEEE.fixed_generic_pkg package. The box symbol indicates that arbitrary generics can be used. When the fixed_generic_pkg package is instantiated, IEEE.fixed_pkg is specified as the actual for fixed_pkg.

package float_pkg is new IEEE.float_generic_pkg ( -- ... fixed_pkg => IEEE.fixed_pkg)


Note that IEEE.fixed_pkg itself is the instance of fixed_generic_pkg. The addition of the two packages completes the transition of the IEEE library to VHDL 2008. All source files required by the standard are compiled into the library.For more information about VHDL 2008 features related to packages, see the VHDL Reference Guide available from the References | VHDL Language Reference Guide section in the main TOC or from the References | Active-HDL Reference Guides | VHDL Language Reference Guide page of the Graphical View of Contents main window.

Aggregates can now be formed not only from array elements but also from array slices. For example, the following declaration is now valid:

variable a5: bit_vector (4 downto 0) := ('0', "1111");

The aggregates can also use object names. For example, assuming that the a4 variable is declared as bit_vector (3 downto 0), the following assignment could be made:

a5 := (a4, '1');

The 'SUBTYPE attribute is supported. The prefix of the attribute is an object or an alias for an object. The returned value is the fully constrained subtype of the object in the prefix.

The 'ELEMENT attribute is supported. The prefix of the attribute is an array object or an alias for an array. The returned value is the fully constrained subtype of the array element.

Character literals can now be used as simple names. This simplifies defining aliases for values. For example, an alias for value '0' of the bit type can now be defined as:

alias low is '0'[return bit];

Note that the above code is incorrect according to VHDL 2002 and earlier language version. Because a character literal could not be used a simple name, an expanded name had to be used instead, for example:

alias low is STANDARD.'0'[return bit];

VHDL 2008 external names are now supported. External names can be used to access design objects declared elsewhere in the design hierarchy. For example, the testbench code can access the value of a signal declared anywhere in the design and write that value to a line variable, for example:

write(l_out, <<signal .testbench.UUT.I11.OFF : std_logic>>, right, 2);An extended name consists of angled brackets followed by object class (signal, variable, or const), an external pathname (e.g. testbench.UUT.I11.OFF), a colon, a subtype indication, and a pair of closing brackets. An external pathname can be a package pathname, an absolute pathname, or a relative pathname. Package pathnames start with the at sign @ and may denote only objects declared in packages. Absolute paths start with a dot .. Relative paths may start with a circumflex accent ^ (indicating a region declared one level above), or without any additional characters, for example:

signal pckg : std_logic := <<constant @my_library.my_package.CONST_1 : std_logic>>;

signal rltve_1 : std_logic := <<signal ^.^.OFF : std_logic>>;


signal rltve_2 : std_logic := <<signal UUT.I11.OFF : std_logic>>;

signal abslt : std_logic := <<signal .testbench.UUT.I11.OFF : std_logic>>;

(SPT45319) For additional information about the new VHDL constructs supported in this release, refer to the Compilation | VHDL Compilation | VHDL 2008 section in the on-line documentation.

The following changes and improvements not related to VHDL 2008 simulation are also available:

Simulation of RTL designs has been accelerated by 10% on average.

Simulations of VHDL units compiled without debugging information consume less memory due to a number of new optimizations. Internal benchmarks have shown an average reduction of 10%, however, the results vary significantly depending on a design.

Clicking on a message generated by the assert statement in a package from the IEEE library (e.g. STD_LOGIC_ARITH ) now opens the HDL Editor and places the insertion point in a line where a statement that triggered the message is located. A sample message is shown below:

# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# KERNEL: Time: 0 ps, Iteration: 1, Instance: /UUT/I14, Process: line__36.s;

Note that you do not have to compile source files with debugging information (-dbg) for this new feature to work. (SPT45514)

The compiler generates a new error message (COMP96_0661) when multiple logical expressions are chained and not parenthesized. In the previous version, a generic syntax error message (COMP96_0049) was reported. For details on both error messages, see the Message Reference Guide. The Message Reference Guide is available from the References | Message Reference Guide section in the main TOC or from the References | Active-HDL Reference Guides | Message Reference Guide page of the Graphical View of Contents window. (SPT48163)

Verilog Compilation and Simulation

The output of the $write task is now flushed to the standard output whenever the simulator enters the interactive mode (e.g. after executing the $stop task). In the previous version, the output could be buffered until a new line character was added to the buffer, the simulation was interrupted by the GUI or a breakpoint, or the simulation terminated. (SPT18891)

The ports of the time and realtime type are now allowed as module outputs. (SPT45465)

It is now possible to prevent the simulator from splitting net vectors in VCD files. To do so, use the new -solid_vcd argument of the asim command. The option affects both VCD files created from source code (with Verilog $dump* tasks) and from the command line (with vcd* commands).

The utility for encrypting source files (protectip) can now skip processing of the `include directives and included files when invoked with the new -ni or --noinclude option. Now more than one input file can be specified for the protectip utility. (SPT45812, SPT47850, SPT47866)

Unrecognized arguments passed to the compiler and prefixed with the + sign are now ignored. In the previous version, they triggered an error. (SPT45090)

The messages produced on the console by the $display, $monitor, and $strobe families of tasks can now be prefixed by the file location (i.e. the file name and the line number) where the task was called. For example, the output of $display("hello") can be changed from KERNEL: hello to the more verbose KERNEL: hello.v (5): hello. To enable such output, set variable printdisplaytasksource to 1.


This maybe useful when creating logs for further analysis or when working in the text console. (The graphical Console allows you to navigate to the task by double-clicking its output, even if it is not prefixed by the file location.)

When a source library is specified on the command line (alog -v <filename>) the compiler will scan it not only for missing modules definitions but also for macros. The compiler will read macros even if the source library does not contain any module definitions. (SPT45084)

SystemVerilog Compilation and Simulation

The fork-join_any and fork-join_none constructs are supported within automatic tasks and functions. (SPT47221)

Statements that do not block, specifically, non-blocking assignments, event triggers, procedural assignments, clocking drives, and the fork-join_none construct can now be used inside functions. This is an extension introduced by SystemVerilog 2009 (IEEE Std 1800™-2009). It will not be available, if the compiler runs in the SystemVerilog 2005 mode (alog -v2k5). The support for the latest SystemVerilog standard has been also added to the GUI settings (i.e. to the Standard version list boxes in the Preferences, Design Settings, and File Properties dialog boxes).

Arguments to automatic tasks and functions can now be passed by reference. Passing by reference requires preceding the argument declaration with the ref keyword, for example:

task automatic datadump ( ref integer arr[1024] );

The task will not receive a copy of the actual argument; instead it will access the actual argument data via the reference handle.

Event merging and event comparison is now supported for automatic events declared in classes.

Queues of class handles are now supported. It is now possible to clear the queue by assigning the {} literal to it. (SPT46243, SPT46132)

Properties and fields of classes and structures stored in dynamic arrays, associative arrays, and queues can now be accessed by appending the dot and the property/field name to an indexed name (i.e. an array/queue element). (SPT46737, SPT46756)

Specification of the seed value for the random number generator at the initialization of simulation is now possible. To set the seed, use the -sv_seed option of the asim command followed either by an integer value (sets the seed to the specified integer) or the random string (sets the seed to a random value selected by the simulator). (SPT48408)

The srandom() method is supported. This method sets the seed for the random number generator. It is built into each SystemVerilog object and can be called against an object handle.

Non-static class properties declared with the rand modifier can be randomized by calling the randomize method against the class handle, for example:

module top; class C; rand int data; int min, max; constraint cnstr { data > min; data < max; } endclass

C hnd; initial begin hnd = new; hnd.min = 5; hnd.max = 10; hnd.randomize(); end


endmodule

Constraints guards have been implemented. This is a mechanism that prevents null pointer access errors during calls to the randomize method against a class handle. When the randomization mechanism detects that a class handle is null, the it excludes that handle from randomization.

The set membership operator is supported both in the constraint block and in the with clause. For detailed information on randomization and expressions supported by the solver, see Constrained Random Value Generation in the SystemVerilog Reference Guide. The guide is available from the References | SystemVerilog Reference Guide section in the main TOC or from the References | Active-HDL Reference Guides | SystemVerilog Reference Guide page of the Graphical View of Contents window. (SPT45154)

Constraints blocks within class objects can now be controlled with the constraint_mode method. This method disables or enables selected constraints. For further details and code examples, see the SystemVerilog Reference Guide. (SPT45155)

Class process built into the std package is supported. Users can declare variables of type process that allows one process to access and control another process once it has started. For more information on the process class, see the SystemVerilog Reference Guide.

Dynamic class variables are supported as arguments for probabilistic system functions such as $dist_exponential. (SPT45157)

Support for the compilation unit scope has been improved. Several language constructs that previously were not allowed in the compilation unit scope, now compile and simulate correctly. For example, all string methods are supported; vector ranges can be specified with constant functions declared in the compilation unit scope, etc.

Arrays are now allowed as modports in interfaces. (SPT46427)

A dynamic array of multidimensional packed arrays can be used as the actual argument of a task or a function. (SPT45160)

A packed array of registers can now be assigned to an unpacked array of nets. (SPT47613)

Unpacked two dimensional arrays can be used as arguments of tasks and functions. (SPT46694)

Associative arrays, dynamic arrays, and queues can be used on the right-hand side of continuous assignments. This is an extension to the SystemVerilog standard. (SPT46054)

Parameters in classes can now be declared by using the parameter and localparam keyword, for example:

class C; parameter int p = 1; localparam int l = 2;endclass

Parameters declared in this way are local to the class and cannot be overridden when instantiating the class (unlike parameters declared with the parameter port list syntax #(<type> <name>=<value>) ). This feature is not available when the compiler runs in the SystemVerilog 2005 mode (alog -v2k5) because SystemVerilog 2005 allows declaring class parameters only in the parameter port list. (SPT46236)

Class objects can be declared const. Such objects must be initialized at declaration. Declaring the const object does not preclude an assignment to object properties. However, an assignment to an object handle declared const is forbidden.

Classes can now be declared in packages. (SPT45242)

The foreach loop can now iterate over associative arrays indexed by the string type. For example,


given a declaration of associative array dict:

typedef class C;C dict[ string ];

the following loop will print all keys placed inside dict:

foreach( dict [s] ) $display( "%s", s );

The step assignment in the for loops can now contain multiple comma-separated assignment statements, for example:

for( int i = 0, int j = MIN; i < 10 && j < MAX; ++i, ++j ) begin //..end

Arguments of the string type can be passed by reference.

The if-else style constraints are now supported. (SPT45153)

The width of the data field in the $display and $fdisplay tasks output can now be set to an arbitrary number. For example, to output a four character wide integer field, use %4d:

$display( "%4d", i );

This works for the following format specifiers: %d, %h, %h, %o, %b, %s, %t, %e, %f, and %g. For %h, %o and %b specifiers, the output is zero padded if the number contains fewer digits than the specified width of the output field. The numbers are by default right-aligned. To make them left-aligned, use a hyphen after the % sign, for example:

$display( "%-4d", i );

The width and the alignment specification is ignored for the following specifiers: %v, %m, %l, %c, %u, %z.(SPT45588, SPT46126)

Support for virtual interfaces has been improved.

Virtual interfaces can now include modport declarations.

Virtual interfaces can be declared in packages.

Virtual interfaces can be declared as static class properties.

Clocking blocks can be referenced via virtual interfaces.

Local variables can now be declared inside SystemVerilog named sequences and properties. (SPT17386, SPT19100)

The simulator can now call functions, tasks, and system tasks upon a successful, non-empty sequence match. This is demonstrated in the example below, where the $display task is called whenever the s sequence matches.

sequence s; @(posedge CLK) (REQ ##[4:16] GNT, $display( "Sequence s matched at time %0t.", $time ));endsequence

(SPT47051)

The $psprintf function is now supported. The $psprintf function behaves similarly $sformat except that the string result is passed back as the function result, not placed in the first argument as for $sformat. Thus $psprintf can be used where a string value would be valid.


The $shortrealtobits and $bitstoshortreal tasks are supported.

DPI export declarations are now supported. An exported SystemVerilog function or a task can be called from a foreign language (i.e. a C or C++ application). The sample foreign declarations are shown below:

export "DPI-C" function f1;export "DPI-C" task t1;

When compiling SystemVerilog code containing foreign declarations, the Verilog compiler (alog) automatically generates a C file (dpi_header.h) containing definitions of foreign functions. After including the generated file in your C/C++ application, you can call exported SystemVerilog tasks and functions from C/C++.

DPI libraries loaded by the simulator are now searched in the order they are specified on the command line. If identically named functions exist in more than one DPI library, then the function from the library specified earlier on the command line is used. In the previous version, libraries were searched in the alphabetical order.

Complex types such as structures or arrays are now supported by the DPI interface. This enhancement applies both to imported and exported functions.

Unpacked structures can now be used as arguments of imported DPI functions. (SPT46695)

Unpacked arrays can now be used in the program port list. (SPT46536)

The wildcard modifier for value bins declaration within the coverpoint construct is now supported.

Casting is allowed in the property declaration. The cast (') operator used before an expression converts the result of this expression of one type to another type. (SPT47091)

The performance of SystemVerilog cross coverage has been significantly improved. Now, designs that produce a large amount of coverage data allocate less memory.

Source code for the SystemVerilog list container is now available in the list.vh file in the vlib/sv subdirectory of the Active-HDL installation directory. The prototype for the list class, list methods, and list iterator methods were specified in Annex D of IEEE Std 1800™-2005. The actual implementation is provided by Aldec. This annex is not available in the newest revision of the standard (IEEE Std 1800™-2009).

The -sv30, -sv31, and -sv31a arguments of the compiler (alog) are no longer supported. The arguments were used to force compatibility with older revisions of SystemVerilog standard (3.0 and 3.1, respectively).

The messages produced on the console by the severity tasks ($info, $warning, $error, and $fatal) are now prefixed by the file location (i.e. the file name and the line number) where the task was called. The old behavior (i.e. not printing the file location) can be restored by setting variable printseveritytasksource to 0.

Automatic variables can now be used in wait statements. (SPT47663)

The %p format for the display and write families of tasks is now supported. This format can be used to print aggregate values, such as unpacked structures or arrays. (SPT46264)

An array of interfaces can now be used as a module port. (SPT47927)

Local variables of type enum and packed struct are now supported.

Covergroup declarations within packages are supported.

Covergroup triggering event expressions are now sensitive to non-static properties of the enclosing class.


Mixed-Language Compilation and Simulation

It is now possible to map Verilog scalar ports to VHDL bit type when instantiating Verilog in VHDL, that is the component declaration for a Verilog module can use ports of type bit. (SPT46240)

C/C++/SystemC Compilation and Simulation

Mixed SystemC-HDL designs simulate up to two times faster. The most significant speedups can be observed in designs with intensive communication between SystemC and HDL modules.

Active-HDL 8.3 supports the latest version of Microsoft Visual Studio 10.0. Now, Microsoft Visual Studio 10.0 can be also used to compile DPI and PLI/VPI applications. The systemc100.lib file required for building SystemC applications with Visual Studio 10.0 is included in the installation.

When generating a SystemC module wrapper for an HDL unit to be instantiated in SystemC, you can now specify that VHDL ports of the boolean type should be mapped to SystemC ports of the bool type (rather than sc_logic or sc_bit). To force the bool type, use the new -boolasbool argument of the scgenmod command. Note that if you use the Copy SystemC Class Declaration option available in the context menu of the Design Browser and the Library Manager, the boolean type will be converted to the sc_logic type. (SPT18081)

Simulation Database The amount of system memory the simulator allocates when recording signals to the simulation

database has been reduced.

The format of the ASDB files (i.e. files used for recording signal history during simulation) has been enhanced. The following improvements have been implemented:

Compression algorithms have been enhanced, which results in faster operation and better compression ratios.

Signal compression runs in a separate thread, possibly on a different CPU core. This enlarges the address space available to the simulator and improves run times for simulations that record signal history.

The size limit for the ASDB file has been enlarged to 16TB.

Note however that the ASDB file generated by version 8.3 cannot be used in earlier editions of Active-HDL. For more information, refer to Known Problems.

LINT/ALINT Support The functionality of the basic LINT tool previously built into the Active-HDL GUI and the HDL

compilers (acom, alog) has been moved from Active-HDL to ALINT which is a stand-alone product offered at no cost. (SPT47149)

The command line version of Aldec's ALINT tool, a programmable design and coding guideline checker, has been moved from VSimSA to ALINT.

LibrariesThe following changes have been introduced to the system and vendor-specific libraries delivered with


Active-HDL 8.3:

New Libraries

Implementation1. Actel® Designer 9.0 SP1 (AXCELERATOR_GCLR, AXCELERATOR_GPSET, SMARTFUSION, OVI_AXCELERATOR_GCLR, OVI_AXCELERATOR_GPSET, OVI_SMARTFUSION)2. Altera Quartus® II 10.0 (CYCLONEIVE, STRATIXV, STRATIXV_HSSI, STRATIXV_PCIE_HIP, OVI_CYCLONEIVE, OVI_STRATIXV, OVI_STRATIXV_HSSI, OVI_STRATIXV_PCIE_HIP)

Updated Libraries

HDL Synthesis1. Synopsys® FPGA Synthesis D-2010.03 SP1

Implementation1. QuickLogic® QuickWorks™ 2010.1.12. Xilinx ISE™ 12.1 (SPT47907)

Removed Libraries

Simulation1. Celoxica DK Design Suite 5.0 SP2 (CELOXICA, OVI_CELOXICA)2. Chip Express (SPT47471)

NOTES: 1. For the complete list of all the pre-compiled vendor libraries delivered with Active-HDL 8.3, refer to the Vendor-Specific Libraries chapter.2. For additional information about availability of discontinued libraries, please contact Aldec Technical Support at [email protected].

Design Flow Manager New Flowcharts

HDL Synthesis1. Altera Quartus II Synthesis & Implementation 10.02. Mentor Graphics® Precision RTL 2010 Synthesis (supports Precision RTL 2010a.218 and Precision RTL 2010a.218 OEM edition for Actel)3. Lattice® Synthesis & Implementation in ispLEVER 8.0 (SPT45920)4. Synopsys® Synplify®/Synplify Pro/Synplify Premier/Premier with Design Planner D-2010.03 (supports Service Pack 1 for FPGA Synthesis D-2010.03)5. Synopsys Synplify Pro 2009.12 for Actel (supports Synplify Pro 2009.12A OEM edition for Actel)6. Xilinx ISE/WebPack 11.5 XST™ VHDL/Verilog7. Xilinx ISE/WebPack 12.1 XST™ VHDL/Verilog

Physical Synthesis1. Xilinx PlanAhead 11.52. Xilinx PlanAhead 12.1

Implementation



1. Actel Designer 9.0 (supports Actel Designer 9.0 SPA, Actel Designer 9.0 SPB, Actel Designer 9.0 SPC, and Actel Designer 9.0 SP1)2. Altera Quartus II 10.03. QuickLogic QuickWorks 2010.x (supports QuickWorks 2010.1.1)4. Xilinx ISE/WebPack 11.55. Xilinx ISE/WebPack 12.1

Updated Flowcharts

HDL Synthesis1. Mentor Graphics Precision RTL 2009 Synthesis (supports Precision RTL 2009a.95 OEM edition for Actel)

Implementation1. Altera Quartus II 9.1 (supports Service Pack 2 for Quartus II 9.1) (SPT47304)2. QuickLogic QuickWorks 2009.x (supports QuickWorks 2009.4.1)

Discontinued Flowcharts

C Synthesis1. Celoxica DK Design Suite

HDL Synthesis1. Mentor Graphics LeonardoSpectrum (Chip Express)

Flowchart Changes and Improvements

Synopsys flowchart1. The Additional options on startup option has been added to the Synplify flowcharts. It allows specifying additional arguments (e.g. -licensetype, -batch, etc.) that will be passed to the syntax of the executable files starting up the synthesis tool from the Design Flow Manager window. The new option is available in the following Synplify flowcharts: Synplify, Synplify Pro, Synplify Premier, and Synplify Premier with Design Planner ver. 9.6 or newer. (SPT46866)

Altera flowchart1. The set of auxiliary tools available in the Design Entry Tools window has been supplemented with Altera SOPC Builder. (SPT48348)

Lattice flowchart1.The Macro Search Path option has been added to the Translate tab of the Implementation Options dialog box in the Lattice ispLEVER 8.0 flowchart. The new option allows specifying the location of a macro/core netlist file (*.ngo) that will be merged with a top-level netlist during implementation. (SPT47600)

Xilinx flowchart1. The Preferred Implementation File option has been removed from the General tab of the Xilinx CORE Generator and Architecture Wizard Interface dialog box in the Xilinx ISE/WebPack 11.1 flowchart. (SPT47209)

NOTE: For additional information about availability of discontinued flowcharts, please contact Aldec Technical Support at [email protected].



Statement/Branch Coverage Branch Coverage show overflow value instead "?". (SPT46745)

The Statement and/or Branch Coverage functionality has been enhanced. Now, it is possible to include or exclude from overall statistics coverage data for selected source files or user-defined file sections. Note that previously, only a design region could be include or excluded from overall statistics. For additional information, refer to the Scripts section. (SPT46319)

The new options that allow specifying design regions or source files to include or exclude from coverage statistics have been added to the Code Coverage category in the Design Settings dialog box. The Show entries for list box along with the list of included/excluded items (specified by the options: Hierarchy, Recursive, Files, and Lines) are equivalent to the corresponding -cc_include and -cc_exclude arguments of the asim command. For additional information, refer to the Scripts section. (SPT47731, SPT46681, SPT47187)

The Output directory edit box in the Simulation | Code Coverage/Profiler category of the Preferences dialog box allows now entering user-defined paths (absolute or relative) for coverage/profiler data. (SPT45269)

Branch Coverage for the ternary operator can be limited to two branches only (0 and 1) with X and Z values excluded. To enable this behavior, pass the new -bc_ternary_01 argument to the asim command or enable the matching option in simulation preferences. (SPT46259)

Shortcuts for navigating in the Hierarchy tab of the Code Coverage Viewer have been implemented. The right, left, up, and down arrows allow you to traverse the hierarchy tree. Additionally, new shortcuts for navigation between executable statements in the Source Code tab have been added. Shortcuts allow to move the focus to the previous uncovered (Ctrl+Up), next uncovered (Ctrl+Down), previous covered (Ctrl+Shift+Up) and next covered (Ctrl+Shift+Down) statements. (SPT46658)

The Source Code tab in the Code Coverage Viewer can be browsed by different objects (blocks, branches, expressions and statements) specified in the new Browse By list box available on the toolbar.

Path Coverage A new tool dedicated to Code Coverage analysis is delivered with Active-HDL 8.3. Path Coverage

is a debugging tool that collects information about the program execution and analyzes whether all combinations of program sequences (program paths) are verified by a testbench. A program path is a sequence of statement executions performed in a particular order. In this type of analysis, except checking whether a logical condition was met and in consequence a particular statement was executed, the tool also collects information about the order the consecutive statements are executed, the branches that are examined, and how logical conditions evaluated during simulation.To enable Path Coverage, compile VHDL source files by using the -pac argument of the VHDL compiler (acom) or check the Path Coverage option in the Coverage/Profiler category of the Design Settings dialog box. When you initialize simulation, pass the -pac argument (simultaneously specifying the operating mode for Path Coverage) to the asim command. The database with coverage statistics is automatically saved to a binary file when simulation terminates or you can generate a coverage report manually.The Path Coverage session and its settings can be controlled from the command line with the use of the pathcoverage command. (Refer to the Scripts section for additional information.) The GUI preferences can be customized in the Path Coverage subcategory of the Design Settings dialog box. Path Coverage is not available in Verilog.


(SPT21168, SPT47727)

Expression Coverage Coverage pragmas can now be used not only for Statement Coverage but also for Expression

Coverage. Those pragmas selectively disable blocks of source code analyzed by Expression Coverage. For VHDL, use vhdl_cover_off and vhdl_cover_on, for example:

--vhdl_cover_offwhen others => null;--vhdl_cover_on

For Verilog, use verilog_cover_off and verilog_cover_off, for example:

// verilog_cover_offdefault: $display( "Error in input data" );// verilog_cover_on

Statements surrounded by coverage pragmas never show up in Expression Coverage reports.

The Expression Coverage engine can now generate Decision Coverage reports. To select the type of a report that should be generated (Expression or Decision Coverage), use the new -exc (Expression Coverage ) and -dc (Decision Coverage) arguments available both for the excoverage report and excoverage write commands.

The functionality of Expression Coverage has been enhanced. Now, it is possible both in the GUI and the command line to include or exclude from overall statistics coverage data for user-defined design regions. The GUI options that allow specifying design regions to include or exclude are available in the Expression Coverage category in the Design Settings dialog box. The Show entries for list box along with the list of included/excluded items (specified by the options: Hierarchy and Recursive) are equivalent to the corresponding -exc_include and -exc_exclude arguments of the asim command. For additional information, refer to the Scripts section. (SPT47187, SPT47731)

The Enable atomic expressions option has been added to the Expression Coverage subcategory of the Design Settings dialog box. The new option is the equivalent of the -exci argument of the acom command. (SPT46853)

ScriptsThe following changes have been introduced to internal macro commands:

The adir command has been enhanced to show VHDL packages in a more detailed way. The output of the command will now include types, subtypes, and shared variables defined in packages. If the -l argument is passed, the command returns additional information about parameters specified during compilation. Additionally package constants, shared variables, signals, and VHDL 2008 generics will have their type (or subtype) listed. Previously, the command showed only object names, without the type information. (SPT17147)

The -check_sensitivity_list argument has been added to the syntax of the acom command. The new argument reports missing, duplicated, or redundant signals on a sensitivity list of a process. (SPT47274)

The -force_celldefine argument of the acom command has been implemented. The new argument prevents signals of a unit compiled with this argument from forcing during simulation.


The acom command has been supplemented with the -delaybinderr argument. The new argument prevents the compiler from reporting an error when component binding at compile time has failed. Refer to the description of the command for more information. (SPT47973, SPT47974)

The -sv2k9 argument has been added to the alog, verilogstandard, and fileveroptions commands. The new argument specifies the IEEE Std 1800™-2009 SystemVerilog standard.

The name of the automatically generated DPI header file can be changed with the new -dpiheader argument of the alog command. If the argument is omitted, the default name dpi_header.h is used for the header. For additional information on improved DPI support, refer to the SystemVerilog Compilation and Simulation section.

The -vc10 argument has been added to the syntax of the ccomp command. The new argument allows changing the default C/C++ compiler (gcc) used in Active-HDL and compiling C/C++/SystemC source files with the use of Microsoft Visual Studio ver.10.0.

The -solid_vcd argument has been added to the syntax of the asim command. The new argument prevents splitting net vectors in VCD files and it is the alternative to the -split_vcd argument.

The asim command has been supplemented with the new -asdbserialprocessing argument. The argument forces both the ASDB engine and the simulation kernel to run on the same core of the CPU regardless of the number of available cores. By default, the ASDB engine and the simulation kernel use separate cores (if Active-HDL is run on a machine with a multi-core processor).

The -asdbrefresh and -asdbsizelimit arguments of the asim command are ignored in this version of Active-HDL.

The values of Verilog parameters assigned on the command line with the -g and -G arguments of the asim command can now use Verilog size constant number notation, for example 6'h0_a.

Recording signals to the ASDB file can be controlled with the new asdbdump command. The command can be used to temporarily disable logging (asdbdump -off), re-enable it after it has been disabled (asdbdump -on), or to flush any buffered data to the database (asdbdump -flush). The command is the equivalent of the asdbdump procedure in VHDL and the $asdbDump and $asdbFlush tasks in Verilog. (SPT45031, SPT45338)

The functionality of the -cc_include and -cc_exclude arguments of the asim command has been enhanced and now the arguments allow including and excluding from Statement and/or Branch Coverage statistics not only design regions but also individual files or file sections. For example, to prevent the top.v file from collecting coverage data, you can use the following syntax:

-cc_exclude top.v

To disable lines 100 through 200 in the top.v file, use the following syntax:

-cc_exclude top.v:100-200

Note that previously, the arguments could only be followed by a region name, not a source file or line number(s). (SPT46319)

The -exc_exclude and -exc_include arguments have been added to the syntax of the asim command. The new arguments allows preventing Expression or Path Coverage statistics from being collected for user-defined design regions. (SPT47187)

The -cell and -vital arguments have been added to the syntax of the list, trace, watch, and wave commands. If wildcards are used in name specification while adding objects to some debugging windows, passing this argument allows inserting and observing signals of:

Verilog cell modules, i.e. modules tagged with the `celldefine and `endcelldefine directives

Verilog modules compiled with the use of the +force_celldefine argument


VHDL units compiled with the use of the -force_celldefine argument

If these arguments are omitted, such signals do not match specification and cannot be presented in the debugging windows. -cell and -vital are not required when signal names are specified explicitly, i.e. without wildcards.

The msginfo command is supported. The command returns a verbose description of a compiler error or warning message. The description of a warning or an error can be displayed in the HDL Editor window or in the Console window.

The list, trace, watch, and wave Active-HDL commands and the log command in VSimSA (in the Tcl and Compatibility mode) have been supplemented with the -lib <library> argument. When wildcards are used in specification of an object name, passing the new argument to the command allows adding signals from the specified library to the Watch window and the Waveform or List Viewer or tracing those signals during simulation. (SPT47539)

The -color argument of the wave command allows now specifying the color of a waveform object not only as the RGB value but it can be also specified as a symbolic color name. Refer to the command description for additional information. (SPT45441)

The new pathcoverage command has been added. The command allows saving Path Coverage statistics to a text or binary report file during simulation (pathcoverage write), converting a binary database to a textual report file (pathcoverage report), or merging results collected in multiple simulations into a single database (pathcoverage merge). The command also allows clearing Path Coverage data (pathcoverage clear) and enables (pathcoverage enable) or disables (pathcoverage disable) collecting coverage statistics.

The excoverage report and excoverage write commands have been supplemented with the -dc, -exc, and -path arguments. The new arguments define the type of statistics that will be included in the report generated by the command, i.e. simplified Expression Coverage report, the regular Expression Coverage report, and the Path Coverage report.

The -locked argument of the cursor command has been added. The new argument allows locking a timing cursor added to the Accelerated Waveform Viewer window. Similarly, the <lock_cursor> argument of the waverestorecursors command is now supported in the DO mode. (SPT48268)

The bookmark command has been implemented. The new command allows adding and removing bookmarks from the Accelerated Waveform Viewer window. (SPT48267)

The wavecompare command allows comparing simulation results saved to the ASDB simulation databases. (SPT47480)

The waveautoreload command has been renamed and replaced by the wavereload command.

The -t argument of the expwave command supports additional values. The bin_txt, dec_txt, and hex_txt values allow specifying the radix (binary, decimal, or hexadecimal) while exporting signals saved in the Standard Waveform Viewer file (.awf) to a text file. Note that the exported text files cannot be read by the Standard List Viewer. (SPT46877)

The functionality of the removefolder command has been extended. Now, Active-HDL displays the confirmation message box prior to executing the command and allows detaching or deleting folders and specifying if a directory will be deleted only from the \src folder or from all its subfolders. (SPT45941)

The pwd command is now supported in the Tcl and Compatibility mode. (SPT46635)

The addfile, open, close, view, and set commands support arguments specifying neither Handel-C source files, environment settings, nor Handel-C-related debug windows.

The hcdebug command is no longer supported.


Block Diagram Editor Double-clicking on a text block or the use of the Edit using HDE option available in the context

menu of the text block opens now HDL code in a separate and fully functional HDL Editor document window. (Previously, a small HDL Editor window blocking access to remaining Active-HDL documents was opened in the foreground.) Note however that if HDL code of a text block is edited in the HDL Editor then the Save As command in the File menu is unavailable. (SPT45374, SPT46401, SPT47507, SPT47720)

The Edit in External Editor option has been added to the context menu of the text blocks. The new option allows editing source code specified in the text blocks in an external tool instead of the built-in Active-HDL text editor (HDL Editor). This option is unavailable for generics and parameters.

If an HDL source file describes an implementation of a fub or a symbol and the use of an external editor is enabled (the Use external text editor option in the External HDL Editors category of the Preferences dialog box is enabled), the Push option opens HDL source code in an external text editor. (SPT46567)

Hiding objects is allowed on block diagrams. The Hide option available in the context menu of a block diagram object (e.g. a symbol, fub, wire, bus, HDL text block, global signal, terminal, etc.) makes an object invisible. In order to see it on a block diagram again, you can use the Show hidden items option from the Diagram menu. Note however that this option just allows displaying invisible items until it is enabled. Otherwise, all hidden objects are not presented on a diagram. In order to permanently restore visibility of all hidden objects on a diagram, the Unhide all items option should be used.

Some tabs of the Objects View window have been equipped with an additional column (Hidden) presenting if an object is visible on a block diagram or it was hidden.

Showing or hiding the names of diagram objects (e.g. symbols, terminals, wires, etc.) has been improved. For example, the Ctrl+N shortcut sequentially enables or disables the display of the object name. The default assignment for the shortcut can be changed in the Shortcuts tab of the Customize dialog box. The Block Diagram Editor category in this tab has been supplemented with several new command types, i.e. Toggle Text: <property_name> which allow displaying or hiding other object properties, e.g. a comment, value, attributes, type, and many more. Note that properties that can be shown or hidden with the use of this new feature are equivalent to checking respective property in the View Texts tab of the object Properties dialog box. (SPT45212)

Enabling or disabling a property in the View Texts tab of the object Properties dialog box has been improved and now an attribute can be checked or unchecked by pressing the space bar.

HDL Editor Setting a code breakpoint is now possible with the use of a mouse. To toggle the breakpoint, just

click with the left-mouse button in the breakpoint status column (i.e. in a column separating the margin presenting the line numbers from the source code editing area). After the mouse-click, the symbol of a white hand is displayed in this column. Note that enabling or disabling a code breakpoint is still possible by using the F9 key or the bp and bd macro commands. (SPT45854)

The Auto Complete feature has been enhanced. Now, instead of a suggested reserved word showing up while writing source code, the HDL Editor displays the pop-up with a list of all keywords or construct templates that can be manually selected and then inserted into source


code. Additionally, the interactive templates (i.e. the templates filled with user-defined names, arguments, or parameter values) can also shows up in the HDL Editor when you start typing the first letters of a reserved word. The Auto Complete feature, and automatic appearance of the list with templates in particular, can be controlled by using the options of the Auto Complete section in the HDL Editor | Language subcategory of the Preferences dialog box. Note however, that the template list can be activated not only automatically (while typing) but it can be also invoked manually by pressing the Ctrl+Space key. (SPT47505, SPT47705, SPT47994)

Active-HDL allows now not only using external text editors to optionally open source files, but now you can also set an external tool as the default source code editor and act in the same way that was previously reserved for the built-in HDL Editor. For example, it is possible to push into a fub or a symbol used on a block diagram, edit text blocks used on block diagrams, and open source files attached to the design tree in the Design Browser by pressing the Enter key or double-clicking on a file. The preferences for the default external HDL editor can be specified in the External HDL Editors category of the Preferences dialog box. (SPT16274, SPT46056, SPT46642, SPT46731)

A new word completion feature is available. Pressing the Alt+Num / keys searches the current file backwards for the first word matching the string at the cursor and inserts the match. Pressing the keys again cycles through possible completions. The editor finds one match at a time, searching the file backwards and then forward. The new feature and functionality is very handy when typing in identifiers. Note that the identifiers are not shown in the autocomplete pop-up list that contains only keywords.

Waveform ViewerAccelerated Waveform Viewer

Waveform comparison is substantially faster.

Basic waveform viewer operations such as redrawing signal waveforms or scrolling window contents are up to three times faster.

The contents of the waveform viewer window can be refreshed during simulation. Previously, simulation results were reloaded in the waveform window when simulation was finished, i.e. after all test-vectors passed, when a breakpoint stopped the simulation session, or when simulation reached the specified time in the last simulation step. Now, you can update the view and see the recent simulation results at any time while the simulator is running. The Waveform View pane is updated once you click on the Auto Reload Waveform icon located on the waveform toolbar.

Dynamically allocated VHDL objects, including record fields and protected type variables can now be logged to the simulation database and displayed in the waveform viewer. The waveform viewer will show not only the address but also the designated value. The following limitations apply:- the value must be logged after it is allocated with the VHDL new allocator- logging stops after the value is deallocated and cannot be resumed.

The Remove All Cursors option has been added to the pop-up menu of the active cursor and the Cursors View pane. The new option allows deleting all inactive timing cursors at once. Previously, it was possible to remove only the selected timing cursor. (SPT48266)

The Save To Macro option allows saving bookmarks defined in the waveform window by using the Toggle bookmark (Ctrl+F2) option in the GUI. Now, the bookmarks can be also set or cleared from the command line. Refer to the Scripts section for additional information. (SPT48267)

The timing cursors can be locked. You can lock/unlock the active timing cursor by using the Lock Cursor or Unlock Cursor option available in the pop-up menu of the active cursor or the Cursors View pane. Note that the timing cursors can be also locked from the command line. Refer to the


Scripts section for additional information. (SPT48268)

The Add Signal Breakpoint option has been added to the context menu of the Signal Grid pane in the Accelerated Waveform Viewer window. It allows setting a signal breakpoint on the selected waveform object. (SPT46055)

The preferences of the waveform viewer have been supplemented with the Use one CPU core for simulation kernel and ASDB processing option. The new option forces the ASDB engine and the simulation kernel to use only one core of the CPU during simulation. This setting allows decreasing allocation of system resources and simulation performance. By default, the ASDB engine and the simulation kernel use separate cores (if Active-HDL is run on a machine with a multi-core processor).

Displaying HDL vector objects of the integer and real type in the Analog mode has been improved. Now, calculating values of signals displayed in the Analog mode is faster and more accurate. Additionally, in previous versions, analog waves were presented by using the full value range resulting from the object declaration in source code or it had to be defined manually. Now, the full range presented in the From .. To fields of the Signal Properties dialog box is used only initially and it can be adjusted to the current range of object values calculated by the simulator and displayed in the current zoom of the Waveform View pane. Whenever you scroll the waveform or change the zoom, the Auto-calculate Range option available in the Display tab can be used to re-calculate the range of displayed values. (SPT21636)

The Load ASDB to memory option available in the Behavior tab of the Waveform Preferences dialog box has been replaced by the Memory for caching ASDB option. The new option allows specifying the size of the memory that will be used to cache the ASDB file. The default value is 128MB. (SPT22415)

The Stimulators column can now be enabled and displayed in the Signal Grid pane of the waveform window. The column shows the type of the stimulator for the selected signal.

The Hotkey stimulator is supported. (SPT21220)

Filtering waveform objects in the Signal Browser window has been improved. Now, the Mode Filter window allows you to select whether the Object View pane will show all types of waveform objects or the view will present only the user-selected types of objects, e.g. input and output ports. (SPT47674)

Renaming row separators while inserting them to the waveform window has been improved. Now, when a new named row is being added, the field with the name of the virtual object remains in the edit mode, which allows you to immediately rename the row without invoking additional options. Previously, a new virtual object was inserted with a default name and to change it, the Rename Signal option from the context menu had to be used. (SPT21992, SPT46072)

Active-HDL Interfaces and WizardsThe following changes have been made to the built-in co-simulation interfaces:

Co-simulation Interface to Celoxica1. Active-HDL 8.3 discontinues the support for the co-simulation interface to the Celoxica DK Design Suite software. The interface allowed co-simulation of HDL units with blocks described in the Handel-C language.2. The Handel-C language is no longer supported by the design entry tools (HDL Editor, Language Assistant), debugging tools (Watch and Handel-C Code Debug windows, Waveform Viewer), and the Design Flow Manager.3. The Handel-C-specific GUI options, design settings, and macro commands are not supported in


Active-HDL 8.3.

The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:

Interface to Simulink®/MATLAB®1. The MATLAB and Simulink interfaces support now 64-bit versions of MATLAB. (SPT47839)2. The eval_string routine prints the output on the Console or not depending on whether it is terminated with the semicolon. This follows the established M-language convention.

The following changes and improvements have been made to the built-in interfaces and import/export of third-party projects:

Import of Altera Quartus II Project1. Active-HDL 8.3 allows importing Altera Quartus II projects (File | Import) containing macros or IP cores generated by the MegaWizard Plug-In Manager in the Quartus II environment. (SPT46894)

Denali/Debussy Interface1. Active-HDL 8.3 discontinues the support of the Denali and Debussy interfaces. (SPT46743)

The following changes and improvements have been made to the built-in source revision control interface:

The support for Subversion (SVN) has been added. (SPT47522, SPT47660, SPT47992, SPT47993)

The following changes and improvements have been made to the CODE2GRAPHICS Conversion Wizard:

The BDE Settings tab of the CODE2GRAPHICS Settings dialog box has been supplemented with the Choose items that will be hidden after conversion option. The new option enables hiding selected types of design objects (symbols, signals, processes, etc.) on a converted block diagram. If the option is selected, the additional Select items to hide dialog box appears during conversion and allows you to specify objects that will be hidden on a converted block diagram.

The following changes and improvements have been made to the PLI/VPI/DPI/VHPI Interfaces:

Double-clicking on an information, warning, or error message printed to the Console window by a VHPI/PLI/VPI routine such as vhpi_assert, tf_error, or tf_message now opens the HDL Editor and shows the source code. This functionality is available for VHDL simulations and Verilog simulations running with the -O2 option. (SPT48028)

Documentation The on-line documentation has been supplemented with Message Reference Guide

(\books\msgref.chm). The guide provides a verbose description of compiler error and warning messages accompanied by code samples and suggested code corrections/solutions. The Message Reference Guide is available from the References | Message Reference Guide section in the main TOC or from the References | Active-HDL Reference Guides | Message Reference Guide page of the Graphical View of Contents window. (SPT48509)

The on-line documentation describing the Accelerated Waveform Viewer has been updated. (SPT47313, SPT47361)

The Handel-C Reference Manual (handelc.chm) is no longer installed along with the Active-HDL on-line documentation.

The following application notes have been removed:

Co-simulation of Handel-C Projects in Active-HDL


Debugging Handel-C Projects

Using Celoxica Flowchart in Altera Designs

Using Celoxica Flowchart in Xilinx Designs

Others The default installation directory (C:\Program Files\Aldec\Active-HDL <version>) has been

changed. Now, Active-HDL is installed to C:\Aldec\Active-HDL <version>. (SPT48424)

The new Save Design Status command has been added to the Design menu. The new command allows generating a design report providing a set of detailed report files containing information about a user workstation, active design, attached design files, Design Flow Manager settings, design libraries, synthesis and/or implementation results, etc. The reports can be generated at any moment of design development. They are saved to the separate folders that are automatically attached to the design tree. (ANA49, SPT22446, SPT47732)

The context menu of the document tabs visible in the main application window has been supplemented with the Close All But This option. The option closes all document windows except the current one. (SPT47417)

The Select Window and Windows List windows have been changed. Now, the windows list the names of all open documents, present their types (file icons), and display an asterisk next to the file name if a file has been modified. If a design file is located outside the \src folder, the full file path is presented at the bottom of the window. Additionally, the Close All But This button has been added to the Windows List window. (SPT47675)

The Refresh contents window allows filtering and selecting whether hidden files and folders will be added to an active design. (SPT45941)

Active-HDL allows changing the current path in the Open (File | Open) or Add Files (Design | Add Files to Design) dialog boxes also with the use of the My Recent Documents or Recent Places shortcuts. Previously, the history of recently opened or added files was not available in the Open and Add Files dialog boxes. (SPT45735)

The View Message Help option has been added to the pop-up menu of the Console window. The new option opens the on-line documentation window with a description of an error/warning message pointed by the cursor in the Console window.

The SystemVerilog Source option has been added to the File | New menu. The new option opens an empty SystemVerilog source file. (SPT22616)


N O T E S

Aldec, Inc.

Corporate Headquarters2260 Corporate CircleHenderson, NV 89074

Tel: +1 702 990 4400Toll Free: +1 800 487 8743Fax: +1 702 990 4414

Active-HDLTM is a trademark of Aldec, Inc.All other trademarks or registered trademarks are property of their respective owners.