ad1821 modio soundcomm* host signal processing codec

aAD1821

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 World Wide Web Site: http://www.analog.com

Fax: 617/326-8703 © Analog Devices, Inc., 1997

REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

MODIO™ SoundComm®*Host Signal Processing Codec

FEATURES

General

Compatible with Microsoft® PC 97 Logo Requirements

Supports Applications Written for Windows® 95,

Windows 3.1, Windows NT, SoundBlaster® Pro,

AdLib®/OPL3®

ISA Plug and Play Compatible

Operation from +5 V Supply

Power Management Modes

100-Lead PQFP Package

Modem

V.34bis (14.4 kbps up to 33.6 kbps)

56k Software Upgradable

V.32/32bis, V.23, V.22/22bis, V.21, Bell 103 and Bell 212

Modem Protocols: V.8 and Automode

V.42/42bis MNP 5 Data Compression and V.43

MNP 2–4 Error Correction

Virtual COM Port 460.8 kbps and 16550 UART

Hayes AT Command Set

Fax

Group 3, Class 1 Support

V.17 (14.4 kbps), V.29 (9600/7200 bps), V.27/V.27ter

Hayes AT Command Set

TIES Escape Sequence

Voice/Telephony

AT#V Commands

Unimodem V

TAPI-Compliant

Voice/Fax/Modem Distinction

Ring Detection

*SoundComm is a registered trademark of Analog Devices, Inc.*Phat is a trademark of Analog Devices, Inc.All other trademarks are the property of their respective holders.

FUNCTIONAL BLOCK DIAGRAM

M A

I2S SERIAL PORT (0)

DIGITAL PLLG = GAINA = ATTENUATEM = MUTEMV = MASTER VOLUME

AD1821

XT

AL

I

XT

AL

O

VO

L_D

N

VO

L_U

P

MID

I_IN

MID

I_O

UT

A_1

B_1 A_X

B_X

A_2

B_2

A_Y

B_Y

MDM_IN/PHONE_IN

MIC

LINE

SYNTH

CD

VID

L_OUT

MDM_OUT/R_OUT

PCLKO

SDATA (1)LRCLK (1)BCLK (1)

SDATA (0)LRCLK (0)BCLK (0)

IOW

IOR

DACK (X)

AEN

PC_A (15:0)

PC_D (7:0)

IRQ (X)

DRQ (X)

SD

I

SD

O

SC

LK

I2S SERIAL PORT (1)

FO

RM

AT

FIF

O

PL

UG

AN

D P

LA

Y IS

A B

US

PA

RA

LL

EL

INT

ER

FA

CE

FO

RM

AT

FIF

O

16-BIT A/D

CONVERTERPGA

SE

LE

CT

OR

MPU-401WSS/

SB PROREGISTER

GAME PORTHARDWARE

VOLUMECONTROL

AGC0dB/20dB

OSCILLATORS

16-BIT D/A

CONVERTER

GAM

PH

AT

™S

TE

RE

O

MV

MV

DSP SERIAL PORT

GAM

GAM

GAM

SD

FS

DA

TA

CL

K

E2PROMCONTROL

SE

L

XIR

Q

MODEM/LOGICALDEVICE

CONTROL

AM

MV

M A

M A

M A

2

2

2

2

2

PHONE_OUT

PH

AT

™S

TE

RE

O

SERIAL PORTINTERFACE

MUSICSYNTHESIZER

GAM

AD1821

–2– REV. 0

On/Off Hook Control

Call Progress Monitor

DTMF Detection and Generation

Auto Dial

Call Forwarding and Conferencing

VOX (Voice Detection)

ADPCM (32 kpbs Voice Compression)

Caller ID

Full-Duplex Speakerphone

Handset Record and Playback

Handset On/Off Detection

DSVD Software Upgradeable

Audio

Stereo Audio 16-Bit SD Codec

V.34 Class Modem Analog Front End

Full-Duplex Capture and Playback Operation at

Different Sample Rates

Internal 3D Circuit—Phat™* Stereo Phase Expander

Integrated OPL3-Compatible Music Synthesizer

Software and Hardware Volume Control

PRODUCT OVERVIEWThe AD1821 MODIO™ (Modem over Audio) SoundComm®

HSP (Host Signal Processing) Codec is a single-chip audio andcommunications subsystem for personal computers. TheAD1821 solution includes the AD1821 mixed-signal controllerIC controller IC and MODIO™ host signal processing soft-ware drivers. The AD1821 maintains full legacy compatibilitywith applications written for SoundBlaster Pro and AdLib, whileservicing Microsoft PC 97 application requirements. TheAD1821 includes an internal OPL3 compatible music synthe-sizer, Phat™ Stereo circuitry for phase expanding the analogstereo output, an MPU-401 UART joystick interface withbuilt-in timer, a DSP serial port and two I2S Serial ports. TheMODIO™ drivers utilize CPU resources to implement highspeed fax, data, voice (with Echo Cancellation) communicationsand maintain audio compatibility. The drivers enable simulta-neous execution of communications and audio with data flowingthrough the AD1821, and provide a graceful degradation of mo-dem performance as the host CPU load changes. The AD1821on-chip Plug and Play routine provides configuration servicesfor all integrated logical devices.

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15SERIAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AD1821 Chip Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20AD1821 Plug and Play Device Configuration Registers . . . 21Sound System Direct Registers . . . . . . . . . . . . . . . . . . . . 22Sound System Indirect Registers . . . . . . . . . . . . . . . . . . . 28SB Pro; AdLib Registers . . . . . . . . . . . . . . . . . . . . . . . . . 37MIDI and MPU-401 Registers . . . . . . . . . . . . . . . . . . . . . 38Game Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39AD1821JS AND AD1821JS-M . . . . . . . . . . . . . . . . . . . . 39AD1821JS PLUG AND PLAY INTERNAL ROM . . . . . 39AD1821JS-M PLUG AND PLAY INTERNAL ROM . . 40

APPENDIX B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41PLUG AND PLAY KEY AND “ALTERNATE KEY”

SEQUENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41PROGRAMMING EXTERNAL EEPROMS . . . . . . . . . 42REFERENCE DESIGNS AND DEVICE DRIVERS . . . 42

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

TABLE OF CONTENTS

FiguresFunctional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 1. PIO Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 2. PIO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3. DMA Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 4. DMA Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 5. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 6. DSP Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 7. I2S Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . 7Figure 8. Reset Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 9. Serial Interface Right-Justified Mode . . . . . . . . . . 16Figure 10. Serial Interface I2S-Justified Mode . . . . . . . . . . . 16Figure 11. Serial Interface Left-Justified Mode . . . . . . . . . . 16Figure 12. DSP Serial Interface (Default Frame Rate) . . . . 19Figure 13. DSP Serial Interface (User Programmed

Frame Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 14. DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 15. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 16. AD1821 Frequency Response Plots . . . . . . . . . . 43

TablesTable I. DSP Port Time Slot Map . . . . . . . . . . . . . . . . . . . 17Table II. Chip Register Diagram . . . . . . . . . . . . . . . . . . . . . 20Table III. Logical Devices and Compatible Plug and

Play Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table IV. Logical Device Configuration . . . . . . . . . . . . . . . 22Table V. Sound System Direct Registers . . . . . . . . . . . . . . 22Table VI. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 26Table VII. Indirect Register Map and Reset/Default States . 29Table VIII. Sound System Indirect Registers . . . . . . . . . . . 30Table IX. SoundBlaster Pro ISA Bus Registers . . . . . . . . . . 37Table X. AdLib ISA Bus Registers . . . . . . . . . . . . . . . . . . . 38Table XI. MIDI ISA Bus Registers . . . . . . . . . . . . . . . . . . . 38Table XII. Game Port ISA Bus Registers . . . . . . . . . . . . . . 38

SPECIFICATIONSSTANDARD TEST CONDITIONS UNLESSOTHERWISE NOTEDTemperature 25 °CDigital Supply (VDD) 5.0 VAnalog Supply (VCC) 5.0 VSample Rate (FS) 48 kHzInput Signal Frequency 1008 HzAudio Output Passband 20 Hz to 20 kHzVIH 5.0 VVIL 0 V

AD1821

REV. 0 –3–

DAC Test Conditions0 dB AttenuationInput Full Scale16-Bit Linear Mode100 kΩ Output LoadMute OffMeasured at Line Output

ADC Test Conditions0 dB GainInput –4 dB Relative to Full ScaleLine Input Selected16-Bit Linear Mode

ANALOG INPUT

Parameter Min Typ Max Units

Full-Scale Input Voltage (RMS Values Assume Sine Wave Input)PHONE_IN, LINE, SYNTH, CD, VID, MDM_IN 1 V rms

2.83 V p-pMIC with +20 dB Gain (MGE = 1) 0.1 V rms

0.283 V p-pMIC with 0 dB Gain (MGE = 0) 1 V rms

2.83 V p-pInput Impedance* 17 kΩInput Capacitance* 15 pF

PROGRAMMABLE GAIN AMPLIFIER—ADC


Step Size (0 dB to 22.5 dB)(All Steps Tested) 1.5 dB

PGA Gain Range Span 22.5 dB

CD, LINE, MICROPHONE, MODEM, SYNTHESIZER, AND VIDEO INPUT ANALOG GAIN/AMPLIFIERS, ATTENUATORS/MUTE


CD, LINE, MIC, SYNTH, VID, MDM_INStep Size: (All Steps Tested)

+12 dB to –34.5 dB 1.5 dBInput Gain/Attenuation Range 46.5 dB

PHONE_INStep Size 0 dB to –45 dB: (All Steps Tested) 3.0 dBInput Gain/Attenuation Range 45 dB

AD1821

–4– REV. 0

DIGITAL DECIMATION AND INTERPOLATION FILTERS*


Audio Passband 0 0.4 × FS HzAudio Passband Ripple ±0.09 dBAudio Transition Band 0.4 × FS 0.6 × FS HzAudio Stopband 0.6 × FS ∞ HzAudio Stopband Rejection 82 dBAudio Group Delay 12/FS secGroup Delay Variation Over Passband 0.0 µs

ANALOG-TO-DIGITAL CONVERTERS


Resolution 16 BitsSignal-to-Noise Ratio (SNR) (A-Weighted, Referenced to Full Scale) –82 –80 dBTotal Harmonic Distortion (THD) (Referenced to Full Scale) 0.011 0.015 %

–79 –76.5 dBAudio Dynamic Range (–60 dB Input THD+N Referenced to

Full-Scale, A-Weighted) 79 82 dBAudio THD+N (Referenced to Full-Scale) 0.019 %

–76 –74.5 dBSignal-to-Intermodulation Distortion* (CCIF Method) 82 dBADC Crosstalk*

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –95 –80 dBLine to MIC (Input LINE, Ground and Select MIC, Read ADC) –95 –80 dBLine to SYNTH –95 –80 dBLine to CD –95 –80 dBLine to VID –95 –80 dB

Gain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %Interchannel Gain Mismatch (Difference of Gain Errors) ±1 dBADC Offset Error –22 +15 mV

DIGITAL-TO-ANALOG CONVERTERS


Resolution 16 BitsSignal-to-Noise Ratio (SNR) (A-Weighted) –83 –79 dBTotal Harmonic Distortion (THD) 0.006 0.009 %

–85 –80.5 dBAudio Dynamic Range (–60 dB Input THD+N Referenced to

Full Scale, A-Weighted) 79 82 dBAudio THD+N (Referenced to Full Scale) 0.013 0.017 %

–78 –75.5 dBSignal-to-Intermodulation Distortion* (CCIF Method) 95 dBGain Error (Full-Scale Span Relative to Nominal Input Voltage) ±10 %Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dBDAC Crosstalk* (Input L, Zero R, Measure R_OUT;

Input R, Zero L, Measure L_OUT) –80 dBTotal Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz

at L_OUT and R_OUT)* –45 dBAudible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz

at L_OUT and R_OUT)* –75 dB

MASTER VOLUME ATTENUATORS (L_OUT AND R_OUT, PHONE_OUT)


Master Volume Step Size (0 dB to –43.5 dB) 1.5 dBMaster Volume Step Size (–43.5 dB to –46.5 dB) 1.5 dBMaster Volume Output Attenuation Range Span 46.5 dBMute Attenuation of 0 dB Fundamental* 80 dB

REV. 0 –5–

AD1821DIGITAL MIX ATTENUATORS*


Step Size: I2S (0), I2S (1), Music, ISA 1.505 dBDigital Mix Attenuation Range Span 94.8 dB

ANALOG OUTPUT


Full-Scale Output Voltage (at L_OUT, R_OUT, PHONE_OUT ) 2.8 V p-pOutput Impedance* 570 ΩExternal Load Impedance* 10 kΩOutput Capacitance* 15 pFExternal Load Capacitance 100 pFVREFX* 2.10 2.25 2.40 VVREFX Current Drive* 100 µAVREFX Output Impedance* 6.5 kΩMute Click (Muted Analog Mixers), Muted Output Minus

Unmuted Output at 0 dB ±5 mV

SYSTEM SPECIFICATIONS*


System Frequency Response Ripple (Line In to Line Out) 1.0 dBDifferential Nonlinearity ±1 LSBPhase Linearity Deviation 5 Degrees

STATIC DIGITAL SPECIFICATIONS


High Level Input Voltage (VIH) 2 VXTALI 2.4 V

Low Level Input Voltage (VIL) 0.8 VHigh Level Output Voltage (VOH), IOH = 8 mA† 2.4 VLow Level Output Voltage (VOL), IOL = 8 mA 0.4 VInput Leakage Current –10 +10 µAOutput Leakage Current –10 +10 µA

POWER SUPPLY


Power Supply Range—Analog 4.75 5.25 VPower Supply Range—Digital 4.75 5.25 VPower Supply Current 221 mAPower Dissipation 1105 mWAnalog Supply Current 51 mADigital Supply Current 170 mAAnalog Power Supply Current—Power-Down 2 mADigital Power Supply Current—Power-Down 24 mAAnalog Power Supply Current—RESET 0.2 mADigital Power Supply Current—RESET 10 mAPower Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog

and Digital Supply Pins, Both ADCs and DACs) 40 dB

CLOCK SPECIFICATIONS*


Input Clock Frequency 33 MHzRecommended Clock Duty Cycle 25 50 75 %Power-Up Initialization Time 500 ms

AD1821

–6– REV. 0

TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)

Parameter Symbol Min Typ Max Units

IOW/IOR Strobe Width tSTW 100 nsIOW/IOR Rising to IOW/IOR Falling tBWDN 80 nsWrite Data Setup to IOW Rising tWDSU 10 nsIOW Falling to Valid Read Data tRDDV 40 nsAEN Setup to IOW/IOR Falling tAESU 10 nsAEN Hold from IOW/IOR Rising tAEHD 0 nsAdr Setup to IOW/IOR Falling tADSU 10 nsAdr Hold from IOW/IOR Rising tADHD 0 nsDACK Rising to IOW/IOR Falling tDKSU 20 nsData Hold from IOR Rising tDHD1 2 nsData Hold from IOW Rising tDHD2 15 nsDRQ Hold from IOW/IOR Falling tDRHD 25 nsDACK Hold from IOW/IOR Rising tDKHD 10 nsData [SDI] Input Setup Time to SCLK* tS 15 nsData [SDI] Input Hold Time from SCLK* tH 10 nsFrame Sync [SDFS] HI Pulse Width* tFSW 80 nsClock [SCLK] to Frame Sync [SDFS]

Propagation Delay* tPD 15 nsClock [SCLK] to Output Data [SDO] Valid* tDV 15 nsRESET Pulse Width tRPWL 100 nsBCLK HI Pulse Width tDBH 25 nsBCLK LO Pulse Width tDBL 25 nsBCLK Period tDBP 50 nsLRCLK Setup tDLS 5 nsSDATA Setup tDDS 5 nsSDATA Hold tDDH 5 ns

NOTES*Guaranteed, not tested.†(All ISA pins MIDI_OUT IOL = 24 mA. Refer to pin description for individual output drive levels.

Specifications subject to change without notice.

tDKSU tDKHD

tAESU tAEHD

tSTW

tRDDV tDHD1

tADSUtADHD

DRQ (0, 1, 3)

DACK (0, 1, 3)

AEN

PC_D [7:0]

PC_A [15:0]

IOR

Figure 1. PIO Read Cycle

tDKSU tDKHD

tAESU tAEHD

tSTW

tDHD2

tADSUtADHD

DRQ (0, 1, 3)

DACK (0, 1, 3)

AEN

PC_D [7:0]

PC_A [15:0]

tWDSU

IOW

Figure 2. PIO Write Cycle

AD1821

–7–REV. 0

tDKHDtDKSU

AEN

tDRHD

tAEHDtAESU

tSTW

tRDDV tDHD1

DRQ (0, 1, 3)

DACK (0, 1, 3)

PC_D [7:0]

IOR

Figure 3. DMA Read Cycle

tDKHDtDKSU

AEN

tDRHD

tAEHDtAESU

tSTW

tDHD2

DRQ (0, 1, 3)

DACK (0, 1, 3)

PC_D [7:0]

tWDSU

IOW

Figure 4. DMA Write Cycle

IOR/ IOW

DATA [7:0]

tBWDN

BYTE N N + 1 N + 2 N + 3

Figure 5. Codec Transfers

SCLK

tPD

tFSW

tS

tH

tDV

SDFS

SDI

SDO

BIT 15 BIT 14 BIT 0

BIT 15 BIT 14 BIT 0

Figure 6. DSP Port Timing

BCLK

SDATALEFT-JUSTIFIED

MODE

SDATARIGHT-JUSTIFIED

MODE

I2S-JUSTIFIEDMODE

SDATA

MSB LSB

tDBH tDBP

tDBLtDLS

tDDS

tDDH

tDDS

tDDH

tDDS

tDDH

tDDS

tDDH

MSB

LRCLK

MSB MSB-1

Figure 7. I2S Serial Port Timing

RESET

tRPWL

Figure 8. Reset Pulse Width

AD1821

–8– REV. 0

ENVIRONMENTAL CONDITIONSAmbient Temperature Rating:

TAMB = TCASE – (PD × θCA)TCASE = Case Temperature in °CPD = Power Dissipation in WθCA = Thermal Resistance (Case-to-Ambient)θJA = Thermal Resistance (Junction-to-Ambient)θJC = Thermal Resistance (Junction-to-Case)

Package uJA uJC uCA

PQFP 77°C/W 7°C/W 70°C/W

ABSOLUTE MAXIMUM RATINGS*

Parameter Min Max Units

Power SuppliesDigital (VDD) –0.3 6.0 VAnalog (VCC) –0.3 6.0 V

Input Current (Except Supply Pins) ±10.0 mAAnalog Input Voltage (Signal Pins) –0.3 VCC + 0.3 VDigital Input Voltage (Signal Pins) –0.3 VDD + 0.3 VAmbient Temperature (Operating) 0 +70 °CStorage Temperature –65 +150 °C*Stresses greater than those listed under Absolute Maximum Ratings may causepermanent damage to the device. This is a stress rating only; functional operationof the device at these or any other conditions above those indicated in theoperational section of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Function PackageModel Range Description Description Option*

AD1821JS 0°C to +70°C 100-Lead PQFP Audio/Modem S-100AD1821JS-M 0°C to +70°C 100-Lead PQFP Modem S-100

*S = Plastic Quad Flatpack.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD1821 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

The AD1821 latchup immunity has been demonstrated at ≥ +100 mA/–80 mA on all pins whentested to Industry Standard/JEDEC methods.

WARNING!

ESD SENSITIVE DEVICE

AD1821

–9–REV. 0

PIN CONFIGURATION

100-Lead PQFP(S-100)

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

22

21

12

24

23

26

25

28

27

30

29

32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 5031 37

76

77

78

79

74

75

72

73

70

71

80

65

66

67

68

63

64

61

62

59

60

69

57

58

55

56

53

54

51

52

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

PIN 1IDENTIFIER

TOP VIEW(Not to Scale)

SP

OR

T_S

DF

S/L

D_D

RQ

/VO

L_U

P

GN

DV

DD

PC

_D (

0)

GN

DV

DD

GN

D

PC

_D (

1)

PC

_D (

2)

PC

_D (

3)

PC

_D (

4)

PC

_D (

5)

PC

_D (

6)

PC

_D (

7)

R_V

ID

L_V

ID

VC

C

GN

DA

VR

EF

VR

EF

_X

R_F

ILT

L_F

ILT

R_A

AF

ILT

L_A

AF

ILT

R_L

INE

L_L

INE

MD

M_I

N/P

HO

NE

_IN

MIC

R_S

YN

TH

L_S

YN

TH

R_C

D

L_C

D

A_2

A_1

IRQ (5)

IRQ (7)

IRQ (9)/IRQ (14)

IRQ (10)/IRQ (4)

IRQ (11)/IRQ (9)/IRQ (4)

IRQ (15)/IRQ (11)

DRQ (0)

DRQ (1)

DRQ (3)

VDD

GND

XCTL1/RING/LD_SEL1

XCTL0/PCLKO/PNPRST

MIDI_OUT

MIDI_IN

GND

XTALO

XTALI

VDD

DACK (0)

DACK (1)

DACK (3)

EE_CLK

EE_DATA

B_X

B_Y

A_X

A_Y

B_1

B_2

I2S0_DATA/VOL_UP

I2S0_LRCLK/VOL_DN

PHONE_OUT

MDM_OUT/R_OUT

L_OUT

AD1821

I2S0_BCLK/GND

PC_A (15)

PC_A (14)

PC_A (13)

PC_A (12)

PC_A (11)

PC_A (10)

PC_A (9)

PC_A (8)

PC_A (7)

PC_A (6)

PC_A (5)

PC_A (4)

PC_A (3)

PC_A (2)

PC_A (1)

PC_A (0)

AEN

IOR

VDD

GND

RESET

RX3D

CX3D

IOW

NC = NO CONNECT

I2S

1_L

RC

LK

/MD

M_S

EL

/IRQ

(12

)/IR

Q (

13)

I2S

1_D

AT

A/IR

Q (

3)/IR

Q (

9)

I2S

1_B

CL

K/M

DM

_IR

Q

SP

OR

T_S

DI/L

D_I

RQ

/VO

L_D

N/G

ND

SP

OR

T_S

DO

/LD

_DA

CK

/VO

L_D

N/G

ND

SP

OR

T_S

CL

K/L

D_S

EL

/NC

AD1821

–10– REV. 0

PIN FUNCTION DESCRIPTIONS

Analog Signals

Pin Name PQFP I/O Description

MIC 44 I Microphone Input. The MIC input may be either line-level or –20 dB from line-level (thedifference being made up through a software controlled 20 dB gain block). The mono MICinput may be sent to the left and right channel of the ADC for conversion, or gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and then summed with left and rightline OUT before the Master Volume stage.

L_LINE 42 I Left Line-Level Input. The left line-level input may be: sent to the left channel of theADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and then summed withleft line OUT.

R_LINE 41 I Right Line-Level Input. The right line-level input may be: sent to the right channel of theADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and then summed withright line OUT.

L_SYNTH 46 I Left Synthesizer Input. The left MIDI upgrade line-level input may be: sent to the leftchannel of the ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and thensummed with left line OUT.

R_SYNTH 45 I Right Synthesizer Input. The right MIDI upgrade line-level input may be: sent to the rightchannel of the ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and thensummed with right line OUT.

L_CD 48 I Left CD Line-Level Input. The left CD line-level input may be: sent to the left channel ofthe ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and then summedwith left line OUT.

R_CD 47 I Right CD Line-Level Input. The right CD line-level input may be: sent to the right chan-nel of the ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and thensummed with right line OUT.

L_VID 32 I Left Video Input. The left audio track for a video line-level input may be: sent to the leftchannel of the ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps and thensummed with left line OUT.

R_VID 31 I Right Video Input. The right audio track for a video line-level input may be: sent to theright channel of the ADC; gained/attenuated from +12 dB to –34.5 dB in 1.5 dB steps andthen summed with right line OUT.

L_OUT 30 O Left Output. Left channel line-level post-mixed output. The final stage passes through theMaster Volume block and may be attenuated 0 dB to –45 dB in 1.5 dB steps.

MDM_OUT/ 29 O Modem Output/Right Output. Right channel line-level post-mixed output. The final stageR_OUT passes through the Master Volume block and may be attenuated 0 dB to –45 dB in 1.5 dB

steps.

MDM_IN/ 43 I Modem Input/Phone Input. Line-level input from a DAA/modem chipset.PHONE_IN

PHONE_OUT 28 O Phone Output. Line-level output from a DAA/modem chipset.

RX3D 26 O Phat™* Stereo Phase Expander filter network, resistor pin.

CX3D 27 I Phat™* Stereo Phase Expander filter network, capacitor pin.

AD1821

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Parallel Interface (All Outputs are 24 mA Drivers)


PC_D[7:0] 85–88, 91–94 83–86, 89–92 I/O Bidirectional ISA Bus PC Data, 24 mA drive. Connects the AD1821to the low byte data on the bus.

IRQ(x)* 75–81, 83 O Host Interrupt Request, 24 mA drive. IRQ (3)/IRQ (9), IRQ(5), IRQ(7),IRQ(9)/IRQ (14), IRQ(10)/IRQ(4), IRQ(11)/IRQ (9)/IRQ (4), IRQ(12)/IRQ(13), IRQ(15)/IRQ (11). Active HI signals indicating a pending interrupt.

DRQ(x) 72–74 O DMA Request, 24 mA drive. DRQ(0), DRQ(1), DRQ(3). Active HI signalsindicating a request for DMA bus operation.

PC_A[15:0] 4–19 I ISA Bus PC Address. Connects the AD1821 to the ISA bus address lines.

AEN 20 I Address Enable. Low signal indicates a PIO transfer.

DACK (x) 59–61 I DMA Acknowledge. DACK(0), DACK(1), DACK(3). Active LO signalindicating that a DMA operation can begin.

IOR 22 I I/O Read. Active LO signal indicates a read operation.

IOW 21 I I/O Write. Active HI signal indicates a write operation.

RESET 25 I Reset. Active HI.

Game Port


A_1 50 I Game Port A, Button #1.

A_2 49 I Game Port A, Button #2.

A_X 54 I Game Port A, X-Axis.

A_Y 53 I Game Port A, Y-Axis.

B_1 52 I Game Port B, Button #1.

B_2 51 I Game Port B, Button #2.

B_X 56 I Game Port B, X-Axis.

B_Y 55 I Game Port B, Y-Axis.

MIDI Interface Signal (24 mA Drivers)


MIDI_IN 66 I RXD MIDI Input. This pin is typically connected to Pin 15 of the gameport connector.

MIDI_OUT 67 O TXD MIDI Output. This pin is typically connected to Pin 12 of the gameport connector.

AD1821

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Muxed Serial Ports (8 mA Drivers)


I2S(0)_BCLK* 3 I I2S (0) Bit Clock.

I2S(0)_LRCLK* 2 I I2S (0) Left/Right Clock.

I2S(0)_DATA* 1 I I2S (0) Serial Data Input.

I2S(1)_BCLK* 82 I I2S (1) Bit Clock.

I2S(1)_LRCLK* 83 I I2S (1) Left/Right Clock.

I2S(1)_DATA* 81 I I2S (1) Serial Data Input.

SPORT_SDI* 100 I Serial Port Digital Serial Input.

SPORT_SCLK* 97 O Serial Port Serial Clock.

SPORT_SDFS* 98 O Serial Port Serial Data Frame Synchronization.

SPORT_SDO* 99 O Serial Port Serial Data Output.

Miscellaneous Analog Pins


VREF_X 36 O Voltage Reference. Nominal 2.25 volt reference available for dc-cou-pling and level-shifting. VREF_X should not be used to sink or source sig-nal current.

VREF 35 I Voltage Reference Filter. Voltage reference filter point for external by-passing only.

L_FILT 38 I Left Channel Filter. Requires a 1.0 µF to analog ground for properoperation.

R_FILT 37 I Right Channel Filter. Requires a 1.0 µF to analog ground for properoperation.

L_AAFILT 40 I Left Channel Antialias Filter. This pin requires a 270 pF NPOcapacitor to analog ground for proper operation.

R_AAFILT 39 I Right Channel Antialias Filter. This pin requires a 270 pF NPOcapacitor to analog ground for proper operation.

Crystal Pin


XTALO 64 O 33 MHz Crystal Output. If no Crystal is present leave XTALOunconnected.

XTALI 63 I 33 MHz Clock. When using a crystal as a clock source, the crystalshould be connected between the XTALI and XTALO pins. Clock in-put may be driven into XTALI in place of a crystal. When using an ex-ternal clock, VIH must be 2.4 V rather than the VIH of 2.0 V specifiedfor all other digital inputs.

External Logical Devices


LD_IRQ* 100 I Logical Device IRQ.

LD_DACK* 99 O Logical Device DACK.

LD_DRQ* 98 I Logical Device DRQ.

LD_SEL* 97 O Logical Device Select.

MDM_SEL* 83 O Modem Chip Set Select.

MDM_IRQ* 82 I Modem Chip Set IRQ.

LD_SEL1* 69 O Logical Device (1) Select.

PNPRST* 68 O Plug and Play Reset.

AD1821

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Hardware Volume Pins


VOL_DN* 2, 99, 100 I Master Volume Down. Modifies output level on pins L_OUT and R_OUT.Contains a 10 kΩ internal pull-up resistor. When asserted LO, decreases MasterVolume by 1.5 dB/sec. Must be asserted at least 25 ms to be recognized. Whenasserted simultaneously with VOL_UP, output is muted. Output level modifica-tion reflected in indirect register 0 × 29.

VOL_UP* 1, 98 I Master Volume Up. Modifies output level on pins L_OUT and R_OUT. Con-tains a 10 kΩ internal pull-up resistor. When asserted LO, increases MasterVolume by 1.5 dB/sec. Must be asserted at least 25 ms to be recognized. Whenasserted simultaneously with VOL_UP, output is muted. Output level modifica-tion reflected in indirect register 0 × 29.

Control Pins


XCTL0* 68 O External Control 0. The state of this pin (TTL HI or LO) is reflected in codecindexed register. This pin is an open drain driver.

PCLKO* 68 O Programmable Clock Output. This pin can be programmed to generate an out-put clock equal to FS, 8 × FS, 16 × FS, 32 × FS, 64 × FS, 128 × FS or 256 × FS.MPEG decoders typically require a master clock of 256 × FS for audiosynchronization.

XCTL1* 69 O External Control 1. The state of this pin (TTL HI or LO) is reflected in codecindexed register. Open drain, 8 mA active 0.5 mA pull-up resistor.

RING* 69 I Ring Indicator. Used to accept the ring indicator flag from the DAA.

Power Supplies


VCC 33 I Analog Supply Voltage (+5 V).

GNDA 34 I Analog Ground.

VDD 23, 62, 71, I Digital Supply Voltage (+5 V).89, 95

GND 3*, 24, 65, I Digital Ground.70, 84, 90,96, 99*, 100*

Optional EEPROM Pins


EE_CLK 58 O EEPROM Clock.

EE_DATA 57 I EEPROM Data.

*The position of this pin location/function is dependent on the EEPROM data.

AD1821

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HOST INTERFACEThe AD1821 contains all necessary ISA bus interface logic on-chip. This logic includes address decoding for all onboardresources, control and signal interpretation, DMA selection andcontrol logic, IRQ selection and control logic, and all interfaceconfiguration logic.

The AD1821 supports a Type “F” DMA request/grant architec-ture for transferring data with the ISA bus through the 8-bitinterface. The AD1821 also supports DACK preemption. Pro-grammed I/O (PIO) mode is also supported for control registeraccesses and for applications lacking DMA control. TheAD1821 includes dual DMA count registers for full-duplexoperation enabling simultaneous capture and playback on sepa-rate DMA channels.

Codec Functional DescriptionThe AD1821’s full-duplex stereo codec supports business audioand multimedia applications. The codec includes stereo audioconverters, complete on-chip filtering, MPC Level-2 andLevel-3 compliant analog mixing, programmable gain and at-tenuation, a variable sample rate converter, extensive digital mixingand FIFOs buffering the Plug and Play ISA bus interface. Whenusing MODIO modem software, PHONE_IN and R_OUTchannels are used to support modem and telephony features.

Analog InputsThe codec contains a stereo pair of ∑∆ analog-to-digital con-verters (ADC). Inputs to the ADC can be selected from the fol-lowing analog signals: mono (PHONE_IN), mono microphone(MIC), stereo line (LINE), external stereo synthesizer (SYNTH),stereo CD ROM (CD), stereo audio from a video source (VID)and post-mixed stereo or mono line output (OUT).

Analog MixingPHONE_IN, MIC, LINE, SYNTH, CD and VID can be mixedin the analog domain with the stereo line OUT from the Σ∆digital-to-analog converters (DAC). Each channel of the stereoanalog inputs can be independently gained or attenuated from+12 dB to –34.5 dB in 1.5 dB steps, except for PHONE_IN,which has a range of 0 dB to –45 dB steps. The summing pathfor the mono inputs (MIC, and PHONE_IN to line OUT) du-plicates mono channel data on both the left and right line OUT,which can also be gained or attenuated from +12 dB to –34.5 dBin 1.5 dB steps for MIC, and +0 dB to –45.5 dB in 3 dB stepsfor PHONE_IN. The left and right mono summing signals arealways identical being equally gained or attenuated.

Analog-to-Digital DatapathThe selector sends left and right channel information to the pro-grammable gain amplifier (PGA). The PGA following the selec-tor allows independent gain for each channel entering the ADCfrom 0 dB to 22.5 dB in 1.5 dB steps.

For supporting time correlated I/O echo cancellation, the ADCis capable of sampling microphone data on the left channel andthe mono summation of left and right OUT on the right channel.

The codec can operate in either a global stereo mode or a glo-bal mono mode with left channel inputs appearing at both chan-nels of the 16-bit Σ∆ converters. Data can be sampled at theprogrammed sampling frequency (from 4 kHz to 55.2 kHz with1 Hz resolution).

Digital Mixing & Sample RatesThe audio ADC sample rate and the audio DAC sample rates

are completely independent. The AD1821 includes a variablesample rate converter that lets the codec instantaneouslychange and process sample rates from 4 kHz to 55.2 kHz with aresolution of 1 Hz. The in-band integrated noise and distor-tion artifacts introduced by rate conversions are below –90 dB.

Up to four channels of digital data can be summed together andpresented to the stereo DAC for conversion. Each digital chan-nel pair can contain information encoded at a different samplerate. For example, 8 kHz .wav data received from the ISA inter-face, 48 kHz MPEG audio data received from I2S(0), digital44.1 kHz CD data received from I2S(1) and internally generated22.05 kHz music data may be summed together and convertedby the DACs.

Digital-to-Analog DatapathThe internally generated music synthesizer data, PCM datareceived from the ISA interface, data received from the I2S(0)port and data received from the I2S(1) port, and the DSP serialport passes through an attenuation mute stage. The attenuatorallows independent control over each digital channel, which canbe attenuated from 0 dB to –94.5 dB in 1.5 dB steps before be-ing summed together and passed to the DAC, or the channelmay be muted entirely.

Analog OutputsThe analog output of the DAC can be summed with any of theanalog input signals. The summed analog signal enters theMaster Volume stage where each channel L_OUT, R_OUT andPHONE_OUT may be attenuated from 0 dB to –46.5 dB in1.5 dB steps or muted.

Digital Data TypesThe codec can process 16-bit twos-complement PCM lineardigital data, 8-bit unsigned magnitude PCM linear data and8-bit µ-law or A-law companded digital data as specified in thecontrol registers. The AD1821 also supports ADPCM encodedin the Creative SoundBlaster ADPCM formats.

Host-Based Echo Cancellation SupportThe AD1821 supports time correlated I/O data format by pre-senting MIC data on the left channel of the ADC and the monosummation of left and right OUT on the right channel. TheADC sample rates are independent of the DAC sample rate allow-ing the AD1821 to support ADC time correlated I/O data at8 kHz and DAC data at any other sample rate in the range of4 kHz to 55.2 kHz simultaneously.

Telephony SupportThe AD1821 contains a PHONE_IN input and aPHONE_OUT output. These pins are supplied so the AD1821may be connected to a modem chip set, a telephone handset ordown-line phone.

WSS and SoundBlaster CompatibilityWindows Sound System software audio compatibility is builtinto the AD1821.

SoundBlaster emulation is provided through the SoundBlasterregister set and the internal music synthesizer. SoundBlaster Proversion 2.01 functions are supported, including record and Cre-ative SoundBlaster ADPCM.

Virtually all applications developed for SoundBlaster, WindowsSound System, AdLib and MIDI MPU-401 platforms run on theAD1821 SoundComm® Controller. Follow the same developmentprocess for the controller as you would for these other devices.

AD1821

–15–REV. 0

As the AD1821 contains SoundBlaster (compatible) and WindowsSound System logical devices. You may find the following relateddevelopment kits useful when developing AD1821 applications.

Developer Kit for SoundBlaster Series, 2nd ed. © 1993,Creative Labs, Inc., 1901 McCarthy Blvd., Milpitas, CA 95035

Microsoft Windows Sound System Driver Development Kit (CD),Version 2.0, © 1993, Microsoft Corp., One Microsoft Way,Redmond, WA 98052

The following reference texts can serve as additional sources ofinformation on developing applications that run on theAD1821.

S. De Furia & J. Scacciaferro, The MIDI Implementation Book,(© 1986, Third Earth, Pompton Lake)

C. Petzold, Programming Windows: the Microsoft guide to writ-ing applications for Windows 3.1, 3rd. ed., (© 1992, MicrosoftPress, Redmond)

K. Pohlmann, Principles of Digital Audio, (© 1989, Sams,Indianapolis)

A. Stolz, The SoundBlaster Book, (© 1993, Abacaus, GrandRapids)

J. Strawn, Digital Audio Engineering, An Anthology, (© 1985,Kaufmann, Los Altos)

Yamamoto, MIDI Guidebook, 4th. ed., (© 1987, 1989,Roland Corp.)

Multimedia PC CapabilitiesThe AD1821 is MPC-2 and MPC-3 compliant. This compli-ance is achieved through the AD1821’s flexible mixer and theembedded chip resources.

Music SynthesisThe AD1821 includes an embedded music synthesizer thatemulates industry standard OPL3 FM synthesizer chips anddelivers 20 voice polyphony. The internal synthesizer generatesdigital music data at 22.05 kHz and is summed into the DACsdigital data stream prior to conversion. To sum synthesizer datawith the ADC output, the ADC must be programmed for a22.05 kHz sample rate.

The synthesizer is a hardwareimplementation of Eusynth-1+code that was developed byEuphonics, a research and devel-opment company that specializesin audio processing and electronicmusic synthesis.

Wavetable MIDI InputsThe AD1821 has a dedicated analog input for receiving an ana-log wavetable synthesizer output. Alternatively, a wavetablesynthesizer’s I2S formatted digital output can be directly con-nected to one of the AD1821’s I2S serial ports. Digital wave-table data from the AD1821’s I2S port may be summed withother digital data streams being handled by the AD1821 andthen sent to the 16-bit Σ∆ DAC.

MIDIThe primary interface for communicating MIDI data to andfrom the host PC is the compatible MPU-401 interface thatoperates in UART mode. The MPU-401 interface has two

built-in FIFOs: a 64 byte receive FIFO and a 16 byte transmitFIFO.

Game PortAn IBM-compatible game port interface is provided on chip.The game port supports up to two joysticks via a 15-pin D-subconnector. Joystick registers supporting the MicrosoftDirect Input standard are included as part of the register map.The AD1821 may be programmed to automatically sample thegame port and save the value in the Joystick Position Data Reg-ister. When enabled, this feature saves up to 10% CPU MIPSby off-loading the host from constantly polling the joystick port.

Volume ControlThe registers that control the Master Volume output stage areaccessible through the parallel port. Master Volume output canalso be controlled through a 2-pin hardware interface. One pinis used to increase the gain, the other pin attenuates the outputand both pins together entirely mute the output. Once muted, anyfurther activity of these pins will unmute the AD1821’s output.

Plug and Play ConfigurationThe AD1821 is fully Plug and Play configurable. For mother-board applications, the built-in Plug and Play protocol can bedisabled with a software key providing a back door for the BIOSto configure the AD1821’s logical devices. For information onthe Plug and Play mode configuration process, see the Plug andPlay ISA Specification Version 1.0a (May 5, 1994). All theAD1821’s logical devices comply with Plug and Play resourcedefinitions described in the specification.

The AD1821 may alternatively be configured using an optionalPlug and Play Resource ROM. When the EEPROM is present,some additional AD1821 muxed-pin features become available.For example, pins that control an external modem logical deviceare muxed with the DSP serial port. Some of these pin optioncombinations are mutually exclusive (see Appendix A for moreinformation).

REFERENCESThe AD1821 also complies with the following related specifica-tions; they can be used as an additional reference to AD1821 op-erations beyond the material in this data sheet.

Plug and Play ISA Specification, Version 1.0a, © 1993, 1994,Intel Corp. & Microsoft Corp., One Microsoft Way,Redmond, WA 98052

Multimedia PC Level 2 Specification, © 1993, Multimedia PCMarketing Council, 1730 M St. NW, Suite 707, Washington,DC 20036

MIDI 1.0 Detailed Specification & Standard MIDI Files 1.0,© 1994, MIDI Manufacturers Association, PO Box 3173La Habra, CA 90632-3173

Recommendation G.711-Pulse Code Modulation (PCM) Of VoiceFrequencies (µ-Law & A-Law Companding), The InternationalTelegraph and Telephone Consultative Committee IX PlenaryAssembly Blue Book, Volume III - Fascicle III.4, GeneralAspects Of Digital Transmission Systems; TerminalEquipment’s, Recommendations G.700 - G.795, (Geneva,1988), ISBN 92-61-03341-5

IMA Digital Audio Doc-Pac (IMA-ADPCM), © 1992, Inter-active Multimedia Association, 48 Maryland Avenue, Suite202, Annapolis, MD 21401-8011

EuSynth-1+

AD1821

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SERIAL INTERFACESI2S Serial PortsThe two I2S serial ports on the AD1821 accept serial data in the following formats: Right-Justified, I2S-Justified and Left-Justified.

Figure 9 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the risingedge of the BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition, so that when there are 64 BCLK periodsper LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.

LRCLK

BCLK

SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LEFT CHANNEL RIGHT CHANNEL

14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

Figure 9. Serial Interface Right-Justified Mode

Figure 10 shows the I2S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the risingedge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay.

LRCLK

BCLK

SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

Figure 10. Serial Interface I2S-Justified Mode

Figure 11 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the risingedge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.

LRCLK

BCLK

SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

Figure 11. Serial Interface Left-Justified Mode

Bidirectional DSP Serial InterfaceThe AD1821 SoundComm® Controller transmits and receives both data and control/status information through its DSP serial inter-face port (SPORT). The AD1821 is always the bus master and supplies the frame sync and the serial clock. The AD1821 has fourpins assigned to the SPORT: SDI, SDO, SDFS, and SCLK. The SPORT has two operating modes: monitor and intercept. TheSPORT always monitors the various data streams being processed by the AD1821. In intercept mode, any of the digital data streamscan be manipulated by the DSP before reaching the final ADC or DAC stages.

The SDI and SDO pins handle the serial data input and output of the AD1821. Communication in and out of the AD1821 requires thatbits of data be transmitted after a rising edge of SCLK and sampled on the falling edge of SCLK. The SCLK frequency is always11 MHz (or 1/3 or XTALI).

DSP Serial Port Interface time slots are mapped as shown in Table I.

AD1821

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Table I. DSP Port Time Slot Map

Time Slot SDI Pin SDO Pin

0 Control Word Input Status Word Output1 Control Register Data Input Control Register Data Output2 * SS/SB ADC Right Input (to ISA) SS/SB ADC Right Output (from Codec)3 * SS/SB ADC Left Input (to ISA) SS/SB ADC Left Output (from Codec)4 * SS/SB DAC Right Input (to Codec) SS/SB DAC Right Output (from ISA)5 * SS/SB DAC Left Input (to Codec) SS/SB DAC Left Output (from ISA)6 * FM DAC Right Input (to Codec) FM DAC Right Output (from FM Synth Block)7 * FM DAC Left Input (to Codec) FM DAC Left Output (from FM Synth Block)8 * I2S (1) DAC Right Input (to Codec) I2S (1) DAC Right Output (from I2S Port [1])9 * I2S (1) DAC Left Input (to Codec) I2S (1) DAC Left Output (from I2S Port [1])10 * I2S (0) DAC Right Input (to Codec) I2S (0) DAC Right Output (from I2S Port [0])11 * I2S (0) DAC Left Input (to Codec) I2S (0) DAC Left Output (from I2S Port [0])

*This data is ignored by the AD1821 unless the channel pair is in intercept mode (see below).SS = Sound System ModeSB = SoundBlaster Mode

At start-up (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11 MHz sclk/(16 bits × 12 slots)). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot perframe mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.

The frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291and 2/3 Hz default), SS capture rate, SS playback rate, FM rate, I2S Port (1) rate, or I2S Port (0) rate. When the frame rate is lessthan 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. The number of SCLK periods added will vary somewhatfrom frame to frame.

To control the sample data flow of each channel through the DSP Port, valid input, valid output and request bits are located in thecontrol and status words. If the specified channel sample rate is equal to the frame rate, these bits may be ignored since they willalways be set to “1”.

By default, the DSP serial port allows only codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-tutions in sample data flow to and from the codec. There are five bits in SS register 33, which enable intercept mode for SS capture,SS playback, FM playback, I2S Port (1) playback and I2S Port (0) playback.

Control Word Input (Slot 0 SDI)

15 14 13 12 11 10 9 8FCLR RES RES SSCVI SSPVI FMVI IS1VI IS0VI

7 6 5 4 3 2 1 0ALIVE R/W IA[5:0]

IA [5:0] Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shownin Table VI.

R/W Read/Write request. Either a read from or a write to an SS indirect register occurs every frame. Setting this bit ini-tiates an SS indirect register read while clearing this bit initiates an SS indirect register write.

ALIVE DSP port alive bit. When set, this bit indicates to the power-down timer that the DSP port is active. When cleared,this bit indicates that the DSP port is inactive.

IS0VI I2S Port 0 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the I2Sport 0 channel pair, or (2) The AD1821 did not request data from the I2S port 0 channel pair in the previousframe. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I2S Port 0 substitutiondata. When this bit is cleared, data in slots 10 and 11 is ignored.

IS1VI I2S Port 1 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for I2S port1 channel pair or (2) The AD1821 did not request data from the I2S port channel pair in the previous frame. Oth-erwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I2S Port 1 substitution data. Whenthis bit is cleared, data in slots 8 and 9 is ignored.

FMVI FM Synthesis Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for theFM synthesis channel pair or (2) The AD1821 did not request data from the FM synthesis channel pair in the pre-vious frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots 6and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots 6and 7 is ignored.

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SSPVI SS/SB Playback Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled forSS/SB playback or (2) The AD1821 did not request data for SS/SB playback in the previous frame (see theSSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid rightand left SS/SB playback substitution data. If in “capture rate equal to playback rate” mode, setting this bit also in-dicates that valid capture substitution data is being sent to the AD1821. If not in modem mode, right and leftchannel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capturesubstitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as de-fined above, is ignored.

SSCVI SS/SB Capture Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/SB capture or (2) The AD1821 did not request data for SS/SB capture in the previous frame (see the SSCRQ bitin the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is beingsent to the AD1821. If not in modem mode, or DSP port or ISA bus based, right and left channel capture data isaccepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted in Slot3, because Slot 2, which is mapped to the right capture channel, is being used for modem. This mono data will,however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3 and 2is ignored.

RES Reserved: To ensure future compatibility write “0” to all reserved bits.

FCLR DSP Port Clear Status Flag. When this bit is set, (write 1), the PNPR and PDN flag bits in the status word (Bits15 and 14 of slots 0 SDO) are cleared. When this bit is cleared, (writing a 0), it has no effect on PNPR and PDNand preserves them in the previous states.

Status Word Output (Slot 0 SDO)

15 14 13 12 11 10 9 8PDN PNPR RES SSCVO SSPVO FMVO IS1VO IS0VO

7 6 5 4 3 2 1 0MB1 MB0 RES SSCRQ SSPRQ FMRQ IS1RQ IS0RQ

IS0RQ I2S Port (0) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (0) and its four-wordstereo input buffer is not full.

IS1RQ I2S Port (1) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (1) and its four-wordstereo input buffer is not full.

FMRQ FM Synthesis Input Request Flag. This bit is set if intercept mode is enabled for FM synthesis and its four-wordstereo input buffer is not full.

SSPRQ SS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB playback and its four-word stereo input buffer is not full.

SSCRQ SS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB capture and itsfour-word stereo input buffer is not full.

MB0 Mailbox 0 Status Flag. This bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1)was a write, and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirectregister 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and ahost CPU on the ISA bus.

MB1 Mailbox 1 Status Flag. This bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1)was a write and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirectregister 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and ahost CPU on the ISA bus.

IS0VO I2S Port 0 Valid Out. This bit is set if Slots 10 and 11 contain valid right and left I2S Port 0 data.

IS1V1 I2S Port 1 Valid Out. This bit is set if Slots 8 and 9 contain valid right and left I2S Port 1 data.

FMVO FM Synthesis Valid Out. This bit is set if Slots 6 and 7 contain valid left and right FM synthesis data.

SSPVO SS/SB Playback Valid Out. This bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data.

SSCVO SS/SB Capture Valid Out. This bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode,Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain validleft SS/SB capture data as Slot 2 and the ADC right channel are used by the modem.

AD1821

–19–REV. 0

PNPR Plug and Play Reset flag. This bit is set by an AD1821 reset (RESETB pin asserted LOW) or by a Plug and Playreset command. This bit is cleared by the assertion of the FCLR bit in the control word. While this bit is set, allattempts to write an SS indirect register via the DSP port will be ignored and fail. This is to ensure that Plug andPlay resets are immediately applied to the application running on the DSP, without requiring them to continuously pollthe Plug and Play reset status bit. During the frame in which this bit is cleared (by asserting FCLR), an attempt towrite an SS indirect register will succeed. If the FCLR bit is continuously asserted, writes to indirect registers viathe DSP port will always be enabled. A Plug and Play reset command will set this PNPR bit HIGH during at leastone frame.

PDN Power-Down flag. This bit is set by an AD1821 reset (RESETB pin asserted LOW), or by an AD1821 power-down. Before an AD1821 power-down sequence shuts down the DSP port, at least one frame will be sent with thisbit set. This bit can be cleared by the assertion of the FCLR (DSP port status clear) bit in the control word, pro-viding the AD1821 is no longer in power-down.

The SDFS pin is used for the serial interface frame synchronization. New frames are marked by a one SCLK duration HI pulse,driven out on SDFS, one serial clock period before the frame begins. Upon initializing, there are exactly 12 time slots per frame and16 bits per time slot. The frame rate is 57,291 and 2/3 Hz (11 MHz SCLK /(16 bits × 12 slots). The frame rate can also be changedfrom the default value by reprogramming the rate in registers. The frame rate can run at the default rate or be programmed to matchthe modem sample rate, ADC capture rate, DAC playback rate, music sample rate, I2S(1) sample rate or I2S(0) sample rate. Whenthe frame rate is not equivalent to the sample rate, Valid Out, Request In and Valid In bits are used to control the sample data flow.When the frame rate is equivalent to the sample rate, Valid and Request bits can be ignored.

SCLK

SDI OR SDO

SDFS

15 14 13 0123 15 14 13 0123 15 14 13 0123

SAMPLE PERIOD N

SLOT 0 SLOT 15 SLOT 0 SLOT 15 SLOT 0 SLOT 15

SAMPLE PERIOD N + 1 SAMPLE PERIOD N + 2

Figure 12. DSP Serial Interface (Default Frame Rate)

SCLK

SDI ORSDO

SDFS

15 14 13 0123 15 14 13 012315 14 13 0123

SAMPLE PERIOD N

SLOT 0 SLOT 15 SLOT 0 SLOT 15 SLOT 0 SLOT 15

SAMPLE PERIOD N + 1 SAMPLE PERIOD N + 2

Figure 13. DSP Serial Interface (User Programmed Frame Rate)

AD1821

–20– REV. 0

Figure 14 illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams man-aged by the AD1821. Any ADC or DAC data stream can be intercepted by the port, shipped to an external DSP or ASIC manipu-lated, and returned to any DAC summing path or to the ADC.

PLUG AND PLAYISA BUS

PARALLELINTERFACE

AUDIODAC

PGAAUDIO/MODEM

ADC

SERIAL PORT INTERFACE

MUSICSYNTHESIZER

FORMAT FIFO

I2S SERIAL PORT (0)

AM

SE

LE

CT

OR

AM

AM

AMI2S SERIAL PORT (1)

FORMAT FIFO

Figure 14. DSP Serial Port

ISA INTERFACEAD1821 Chip RegistersTable II, Chip Register Diagram, details the AD1821 direct register set available from the ISA Bus. Prior to any accesses by the host,the PC I/O addressable ports must be configured using the Plug and Play Resources.

Table II. Chip Register Diagram

Register Type-Register Name Register PC I/O Address

Plug and PlayADDRESS 0x279WRITE_DATA 0xA79READ_DATA Relocatable in Range 0x203 – 0x3FF

Sound System CodecCODEC REGISTERS 0x(SS Base+0 – SS Base+15)

Relocatable in Range 0x100 – 0x3FFSee Table V

SoundBlaster ProMusic0: Address (w), Status (r) 0x(SB Base) Relocatable in Range 0x010 – 0x3F0Music0: Data (w) 0x(SB Base+1)Music1: Address (w) 0x(SB Base+2)Music1: Data (w) 0x(SB Base+3)Mixer Address (w) 0x(SB Base+4)Mixer Data (w) 0x(SB Base+5)Reset (w) 0x(SB Base+6 or 7)Music0: Address (w) 0x(SB Base+8)Music0: Data (w) 0x(SB Base+9)Input Data (r) 0x(SB Base+A or +B)Status (r), Output Data (w) 0x(SB Base+C or +D)Status (r) 0x(SB Base+E or +F)

AD1821

–21–REV. 0

Register Type-Register Name Register PC I/O Address

AdLibMusic0: Address (w), Status (r) 0x(Adlib Base) Relocatable in Range 0x100 – 0x3F8Music0: Data (w) 0x(Adlib Base+1)Music1: Address (w) 0x(Adlib Base+2)Music1: Data (w) 0x(Adlib Base+3)

MIDI MPU-401MIDI Data (r/w) 0x(MIDI Base) Relocatable in Range 0x100 – 0x3F8MIDI Status (r), Command (w) 0x(MIDI Base+1)

Game PortGame Port I/O 0x(Game Base +0 to Game Base +7) Relocatable in Range0x100 – 0x3F8

AD1821 Plug and Play Device Configuration RegistersThe AD1821 may be configured according to the Intel/Microsoft Plug and Play Specification using the internal ROM. Alternatively,the PnP configuration sequence may be bypassed using the “Alternate Key Sequence” described in Appendix A.

The operating system configures/reconfigures AD1821 Plug and Play Logical Devices after system boot. There are no “boot-devices”among the Plug and Play Logical Devices in the AD1821. Non-Plug and Play BIOS systems configure the AD1821’s LogicalDevices after boot using drivers. Depending on BIOS implementations, Plug and Play BIOS systems may configure the AD1821’sLogical Devices before POST or after Boot. See the Plug and Play ISA Specification Version 1.0a for more information on configura-tion control. To complete this configuration, the system reads resource data from the AD1821’s on-chip resource ROM and fromany other Plug and Play cards in the system, and then arbitrates the configuration of system resources with a heuristic algorithm. Thealgorithm maximizes the number of active devices and the acceptability of their configurations.

The system considers all Plug and Play logical device resource data at the same time and makes a conflict-free assignment of re-sources to the devices. If the system cannot assign a conflict-free resource to a device, the system does not configure or activate thedevice. All configured devices are activated.

The system’s Plug and Play support selects all necessary drivers, starts them and maintains a list of system resources allocated to eachlogical device. As an option, system resources can be reassigned at runtime with a Plug and Play Resource Manager. The customsetup created using the manager can be saved and used automatically on subsequent system boots.

Plug and Play Device IDs (embedded in the logical device’s resource data) provide the system with the information required to findand load the correct device drivers. One custom driver, the AD1821 Sound System driver from Analog Devices, is required for cor-rect operation. In the other cases (MIDI, Game Port), the system can use generic drivers. Table III lists the AD1821’s LogicalDevices and compatible Plug and Play device drivers.

Table III. Logical Devices and Compatible Plug and Play Device Drivers

Logical Device Number Emulated Device Compatible (Device ID) Device ID

0 Sound System — ADS71801 MIDI MPU401 Compatible PNPB006 ADS71812 Game/Joystick Port PNPB02F ADS7182

The configuration process for the logical devices on the AD1821 is described in the Plug and Play ISA Specification Version 1.0a (May5, 1994). The specification describes how to transfer the logical devices from their start-up Wait For Key state to the Config state andhow to assign I/O ranges, interrupt channels and DMA channels. See Appendix A for an example setup program and specific Plugand Play resource data.

Table IV describes in detail the I/O Port Address Descriptors, DMA Channels, Interrupts for the functions required for the AD1821Logical Device groups.

AD1821

–22– REV. 0

Table IV. Logical Device Configuration

LDN PnP Function Description

0 I/O Port Address Descriptor (0x60-0x61) The SoundBlaster Pro address range is from 0x100 to 0x3F0. Thetypical address is 0x220. The range is 16 bytes long and must bealigned to a 16 byte memory boundary.

0 I/O Port Address Descriptor (0x62-0x63) The Adlib address range is from 0x100 to 0x3F8. The typical addressis 0x388. The range is 4 bytes long and must be aligned to an 8 bytememory boundary.

0 I/O Port Address Descriptor (0x64-0x65) The Codec address range is from 0x100 to 0x3F8. The range is16 bytes long and must be aligned to a 16 byte memory boundary.

0 Interrupt Request Level Select (0x70-0x71) This IRQ is shared between the SB Pro device and the Codec. Thesedevices require one of the following IRQ channels: 5, 7, 9, 11, 12 or15. Typically, the IRQ is set to 5 or 7 for this device.

0 DMA Playback Channel Select (0x74) This 8-bit channel is shared between the SB Pro device and the Codecfor playback. These devices require one of the following DMA chan-nels: 0, 1, 3. Typically, DMA channel 1 is set.

0 DMA Capture Channel Select (0x75) This the DMA channel used for capturing Codec data. The Codec op-erates in single channel mode if a separate DMA channel for captureand playback is not assigned. The following DMA channels may beprogrammed: 0, 1, 3. DMA Channel 4 indicates single channel mode.

1 I/O Port Address Descriptor (0x60-0x61) The MPU-401 compatible device address range is 0x100 to 0x3FE.Typical configurations use 0x330. The range is 2 bytes long and mustbe aligned to a 2 byte memory boundary.

1 Interrupt Request Level Select (0x70-0x71) The MIDI device requires one of the following IRQ channels: 5, 7, 9,11, 12 or 15.

2 I/O Port Address Descriptor (0x60-0x61) The Game Port address range is from 0x100 to 0x3F8. The typicaladdress is 0x200. The range is 8 bytes long and must be aligned to an8 byte memory boundary.

NOTEDMA channel 4 indicates single-channel mode.

Sound System Direct RegistersThe AD1821 has a set of 16 programmable Sound System Direct Registers and 36 Indirect Registers. This section describes all theAD1821 registers and gives their address, name and initialization state/reset value. Following each register table is a list (in ascendingorder) of the full register name, its usage and its type: (RO) Read Only, (WO) Write Only, (STKY) Sticky, (RW) Read Write andReserved (res). Table V is a map of the AD1821 direct registers.

Table V. Sound System Direct Registers

DirectAddress Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SSBASE + 0 CRDY VBL INADR[5:0]SSBASE + 1 PI CI TI VI DI RI GI SISSBASE + 2 Indirect SS Data [7:0]SSBASE + 3 Indirect SS Data [15:8]SSBASE + 4 RES PUR COR ORR [1:0] ORL [1:0]SSBASE + 5 PFH PDR PLR PUL CFH CDR CLR CULSSBASE + 6 PIO Playback/Capture [7:0]SSBASE + 7 RESERVEDSSBASE + 8 TRD DAZ PFMT [1:0] PC/L PST PIO PENSSBASE + 9 RES CFMT [1:0] PC/L CST CIO CENSSBASE + 10 RESERVEDSSBASE + 11 RESERVEDSSBASE + 12 JOYSTICK DATA [7:0]SSBASE + 13 JRDY JWRP JSEL [1:0] JMSK [3:0]SSBASE + 14 JAXIS [7:0]SSBASE + 15 JAXIS [15:8]

AD1821

–23–REV. 0

[Base+0] Chip/Modem Status/Indirect Address

7 6 5 4 3 2 1 0CRDY VBL INADR[5:0] RESET = [0x00]

INADR [5:0] (RW) Indirect Address for Sound System (SS). These bits are used to access the Indirect Registers shown in Table VIII.All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS DataRegisters, (Base+2) and (Base+3).

VBL Volume Button Location. When using an EEPROM to configure the PnP state of the AD1821, this bit determineswhether PQFP Pins 1 and 2 (TQFP Pins 99 and 100) are used for VOL_UP and VOL_DN or I2S0_DATA andI2S0_LRCLK respectively.0 I2S0_DATA and I2S0_LRCLK1 VOL_UP and VOL_DN

CRDY (RO) AD1821 Ready. The AD1821 asserts this bit when AD1821 can accept data.0 AD1821 not ready1 AD1821 ready

[Base+1] Interrupt Status

7 6 5 4 3 2 1 0PI CI TI VI DI RI GI SI RESET = [0x00]

SI (RO) SoundBlaster generated Interrupt.0 No interrupt1 SoundBlaster interrupt pending

GI (RW) Game Interrupt (Sticky, Write “0” to Clear).0 No interrupt1 An interrupt is pending due to Digital Game Port data ready

RI (RW) Ring Interrupt (Sticky, Write “0” to Clear).0 No interrupt1 An interrupt is pending due to a Hardware Ring pin being asserted

DI (RW) DSP Interrupt (Sticky, Write “0” to Clear).0 No interrupt1 An interrupt is pending due to a write to the DIT bit in indirect register [33] bit <13>

VI (RW) Volume Interrupt (Sticky, Write “0” to Clear).0 No interrupt1 An interrupt is pending due to Hardware Volume Button being pressed

TI (RW) Timer Interrupt. This bit indicates there is an interrupt pending from the timer count registers. (Sticky,Write “0” to Clear).0 No interrupt1 Interrupt is pending from the timer count register

CI (RW) Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count register.(Sticky, Write “0” to Clear).0 No interrupt1 Interrupt is pending from the capture DMA count register

PI (RW) Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA countregister. (Sticky, Write “0” to Clear).0 No interrupt1 Interrupt is pending from the playback DMA count register

[Base+2] Indirect SS Data Low Byte

7 6 5 4 3 2 1 0 Indirect SS Data [7:0] RESET = [0xXX]

[Base+3] Indirect SS Data High Byte

7 6 5 4 3 2 1 0 Indirect SS Data [15:8] RESET = [0xXX]

Indirect SS Indirect Sound System Data. Data in this register is written to the Sound System Indirect Register specified by theData [15:0] address contained in INDAR [5:0], Sound System Direct Register [Base+0]. Data is written when the Indirect SS

Data High Byte value is loaded.

AD1821

–24– REV. 0

[Base+4] PIO Debug

7 6 5 4 3 2 1 0RES PUR COR ORR[1:0] ORL[1:0] RESET = [0x00]

All bits in this register are sticky until any write that clears all bits to 0.

ORL/ORR (RO) Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left[1:0] channels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is

“sticky,” i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitlycleared. They are also cleared by powering down the chip.

ORL/ORR Over/Under Range Detection

00 Less than –1 dB Underrange

01 Between –1 dB and 0 dB Underrange

10 Between 0 dB and 1 dB Overrange

11 Greater than 1 dB Overrange

COR (RO) Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after thecapture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. Thecodec clears this bit immediately after a 4 byte capture sample is read.

PUR (RO) Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period af-ter the playback FIFO empties. The codec clears (0) this bit immediately after a 4 byte playback sample is writ-ten. When PUR is set, the playback channel has “run out” of data and either plays back a mid-scale value orrepeats the last sample.

[Base+5] PIO Status

7 6 5 4 3 2 1 0PFH PDR PLR PUL CFH CDR CLR CUL RESET = [0x00]

CUL (RO) Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upperor lower byte of the channel.0 Lower byte ready1 Upper byte ready or any 8-bit mode

CLR (RO) Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADCor the right channel ADC.0 Right channel1 Left channel or mono

CDR (RO) Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should beused only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full).0 ADC is stale. Do not reread the information1 ADC data is fresh. Ready for next host data read

CFH (RO) Capture FIFO Half Full. (FIFO has at least 32 bytes before full.)

PUL (RO) Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper orlower byte of the channel.0 Lower byte needed1 Upper byte needed or any 8-bit mode

PLR (RO) Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channelDAC or the right channel DAC.0 Right channel needed1 Left channel or mono

PDR (RO) Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be usedwhen direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes).0 DAC data is still valid. Do not overwrite1 DAC data is stale. Ready for next host data write value

PFH (RO) Playback FIFO Half Empty. FIFO can take at least 32-bytes, 8 groups of 4-bytes.

AD1821

–25–REV. 0

[Base+6] PIO Data

7 6 5 4 3 2 1 0PIO Playback/Capture [7:0] RESET = [0x00]

PIO Playback/ The Programmed I/O (PIO) Data Registers for capture and playback are mapped to the same address. WritesCapture [7:0] send data to the Playback Register and reads will receive data from the Capture Register.

Reading this register will increment the capture byte state machine so that the following read will be from thenext appropriate byte in the sample. The exact byte may be determined by reading the PIO Status Register.Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sampleuntil a new sample is received.

Writing data to this register will increment the playback byte tracking state machine so that the followingwrite will be to the correct byte of the sample. Once all bytes have been written, subsequent byte writes will beignored. The state machine is reset when the current sample is transferred.

Note: All writes to the FIFO “MUST” contain 4 bytes of data.* 1 sample of 16-bit stereo* 2 samples of 16-bit mono* 2 samples of 8-bit stereo (Linear PCM, µ-law PCM, A-Law PCM)* 4 samples of 8-bit mono (Linear PCM, µ-law PCM, A-Law PCM)

[Base+7] Reserved

7 6 5 4 3 2 1 0

Reserved [7:0] RESET = [0xXX]

[Base+8] Playback Configuration

7 6 5 4 3 2 1 0TRD DAZ PFMT [1:0] PC/L PST PIO PEN RESET = [0x00]

PEN (RW) Playback Enable. This bit enables or disables programmed I/O data playback.0 Disable1 Enable

PIO (RW) Programmed Input/Output. This bit determines whether the playback data is transferred via DMA or PIO.0 DMA transfers only1 PIO transfers only

PST (RW) Playback Stereo/Mono select. These bits select stereo or mono formatting for the input audio datastreams. In stereo, the Codec alternates samples between channels to provide left and right channel in-put. For mono, the Codec captures samples on the left channel stereo.0 Mono1 Stereo

PC/L (RW) Playback Companded/Linear Select. This bit selects between a linear digital representation of the audio signalor a nonlinear companded format for all output data. The type of linear PCM or the type of companded for-mat is defined by PFMT [1:0].0 Linear PCM1 Companded

PFMT [1:0] (RW) Playback Format. Use these bits to select the playback data format for output data according to Table VI andFigure 15.

DAZ (RW) DAC zero. This bit forces the DAC to zero.0 Repeat last sample1 Force DAC to ZERO

TRD (RW) Transfer Request Disable. This bit enables or disables Codec DMA transfers during a Codec interrupt (indi-cated by the SS Codec Status register’s INT bit being set [1]). This assumes Codec DMA transfers were en-abled and the PEN or CEN bits are set.0 Transfer Request Enable1 Transfer Request Disable

After setting format bits, sample data into the AD1821 must be ordered according to Figure 15, Table VI.

AD1821

–26– REV. 0

IOR/IOW

PC_D [7:0]

tBWDN

BYTE N N + 1 N + 2 N + 3

Figure 15. Codec Transfers

Table VI. Codec Transfers

Byte 3 Byte 2 Byte 1 Byte 0ST FMT1 FMT0 C/L Format MSB LSB MSB LSB MSB LSB MSB LSB

0 000 Mono Sample 3 Sample 2 Sample 1 Sample 0Linear, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsUnsigned Left Channel Left Channel Left Channel Left Channel

1 000 Stereo Sample 1 Sample 1 Sample 0 Sample 0Linear, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsUnsigned Right Channel Left Channel Right Channel Left Channel

0 001 Mono Sample 3 Sample 2 Sample 1 Sample 0µ-Law, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsCompanded Left Channel Left Channel Left Channel Left Channel

1 001 Stereo Sample 1 Sample 1 Sample 0 Sample 0µ-Law, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsCompanded Right Channel Left Channel Right Channel Left Channel

0 010 Mono Sample 1 Sample 1 Sample 0 Sample 0Linear 16-Bit Upper 8 Bits Lower 8 Bits Upper 8 Bits Lower 8 BitsLittle Endian Left Channel Left Channel Left Channel Left Channel

1 010 Stereo Sample 0 Sample 0 Sample 0 Sample 0Linear 16-Bit Upper 8 Bits Lower 8 Bits Upper 8 Bits Lower 8 BitsLittle Endian Right Channel Right Channel Left Channel Left Channel

0 011 Mono Sample 3 Sample 2 Sample 1 Sample 0A-Law, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsCompanded Left Channel Left Channel Left Channel Left Channel

1 011 Stereo Sample 1 Sample 1 Sample 0 Sample 0A-Law, 8-Bit 8 Bits 8 Bits 8 Bits 8 BitsCompanded Right Channel Left Channel Right Channel Left Channel

0 100 Reserved

1 100 Reserved

0 101 Reserved

1 101 Reserved

0 110 Mono Sample 1 Sample 1 Sample 0 Sample 0Linear, 16-Bit Lower 8 Bits Upper 8 Bits Lower 8 Bits Upper 8 BitsBig Endian Left Channel Left Channel Left Channel Left Channel

0 110 Stereo Sample 0 Sample 0 Sample 0 Sample 0Linear, 16-Bit Lower 8 Bits Upper 8 Bits Lower 8 Bits Upper 8 BitsBig Endian Right+ Channel Left Channel Left Channel Left Channel

0 111 Reserved

1 111 Reserved

AD1821

–27–REV. 0

[Base+9] Capture Configuration

7 6 5 4 3 2 1 0RES CFMT [1:0] CC/L CST CIO CEN RESET = [0x00]

CEN (RW) Capture Enable. This bit enables or disables data capture.0 Disable1 Enable

CIO (RW) Capture Programmed I/O. This bit determines whether the capture data is transferred via DMA or PIO.0 DMA1 PIO

CST (RW) Capture Stereo/Mono Select. This bit selects stereo or mono formatting for the input audio data streams.In stereo, the Codec alternates samples between channels to provide left and right channel input. For mono,the Codec captures samples on the left channel.0 Mono1 Stereo

CC/L (RW) Capture Companded/Linear Select. This bit selects between a linear digital representation of the audio sig-nal or a nonlinear, companded format for all output data. The type of linear PCM or the type of compandedformat is defined by CFMT [1:0].0 Linear PCM1 Companded

CFMT [1:0] (RW) Capture Format. Use these bits to select the format for capture data according to the following Table VI andFigure 15.

[Base+10] Reserved

7 6 5 4 3 2 1 0RESERVED RESET = [0xXX]

[Base+11] Reserved

7 6 5 4 3 2 1 0RESERVED RESET = [0xXX]

[Base+12] Joystick RAW DATA

7 6 5 4 3 2 1 0Joystick Data [7:0] RESET = [0xF0]

Joystick Data (RO) Joystick Data. Joystick Data (identical to 0x201): Writes to this register are ignored.

[Base+13] Joystick Control

7 6 5 4 3 2 1 0JRDY JWRP JSEL [1:0] JMSK [3:0] RESET = 0xF0

JMSK [3:0] (RW) Joystick Axis Mask. JRDY bit calculated based on axes selected by JMSK only.

xxx1 Enable AX

xx1x Enable AY

x1xx Enable BX

1xxx Enable BY

JSEL [1:0] (RW) Joystick Select. Selects one of four joystick axis register sets according to the following table:

00 Read AX (16 Bits) from [Base+14] & [Base+15]

01 Read AY (16 Bits) from [Base+14] & [Base+15]

10 Read BX (16 Bits) from [Base+14] & [Base+15]

11 Read BY (16 Bits) from [Base+14] & [Base+15]

JWRP (RW) Joystick Wrapmode. Continuous Joystick sampling mode—sampling automatically restarted every ~16 ms.

JRDY (RO) Joystick Ready. Sampling complete, joystick data ready for reading.Note: Sampling must be started manually if JWRP is set before any sampling cycles are run. To start sampling after setting the JWRPbit, write to the joystick port [Base+14].

AD1821

–28– REV. 0

[Base+14] Joystick Position Data Low Byte

7 6 5 4 3 2 1 0JAXIS [7:0] RESET = [0xFF]

JAXIS [7:0] (RO) Joystick Axis Low Byte.Note: Axis to be read through this register is selected by the JSEL bits in the control register. A write to this register starts a samplingcycle.

[Base+15] Joystick Position Data High Byte

7 6 5 4 3 2 1 0JAXIS [15:8] RESET = [0xFF]

JAXIS [15:8] (RO) Joystick Axis High Byte.

Note: Axis to be read through this register is selected by the JSEL bits in the control register. A write to this register starts a samplingcycle.

Sound System Indirect RegistersWriting Indirect RegistersAll Indirect Registers “MUST” be written in pairs: low byte followed by high byte. The Indirect Address Register [SSBASE+0]holds the address for a register pair, the Indirect Low Data Byte [SSBASE+2] is used to write low data byte and the Indirect HighData Byte [SSBASE+3] is used to write the high data byte. The low data byte is held in the temporary register until the upper byte iswritten.

Programming Example“Write Sample Rate for Voice Playback at 11,000 Hz (0x2AF8)”1) Write [SSBASE+0] with 0x02 ; indirect register for voice playback sample rate2) Write [SSBASE+2] with 0xF8 ; low byte of 16-bit sample rate register3) Write [SSBASE+3] with 0x2A ; high byte of 16-bit sample rate register

Reading Indirect RegistersAll indirect registers can be individually read. The Sound System Indirect Address Register [SSBASE+0] holds the address for a reg-ister pair, the Indirect Low Data Byte [SSBASE+2] is used to read low data byte and Indirect High Data Byte [SSBASE+3] is usedto read the High data byte.

Programming Example“Read Sample Rate for Voice Playback set to 11,000 Hz (0x2AF8)”1) Write [SSBASE+0] with 0x02 ; indirect register for voice playback sample rate2) Read [SSBASE+2] ; low byte of 16-bit sample rate register set to 0xF83) Read [SSBASE+3] ; high byte of 16-bit sample rate register set to 0x2A

ISR Saves and RestoresFor Interrupt Service Routines, ISRs, it is necessary to save and restore the Indirect Address and the Low Byte Temporary Dataholding registers inside the ISR.

Programming Example“Save/Restore during an ISR”Beginning of ISR:1) Read [SSBASE+0] ; save Indirect Address register to TMP_IA2) Write [SSBASE+0] with 0x00; ; indirect Register for Low Byte Temporary Data3) Read [SSBASE+2] ; save Low Byte Temporary data to TMP_LBT4) ISR Code ; ISR routine5) Write [SSBASE+2] with TMP_LBT ; restore Low Byte Temporary data TMP_LBT6) Write [SSBASE+0] with TMP_IA ; restore Indirect Address Register to TMP_IA7) Return from Interrupt ; return from ISR

AD1821

–29–REV. 0

Table VII. Indirect Register Map and Reset/Default States

Reset/Address Register Name Default State

00 Low Byte TMP 0xXX01 Interrupt Enable and External Control 0x010202 Voice Playback Sample Rate 0x1F4003 Voice Capture Sample Rate 0x1F4004 Voice Attenuation 0x808005 FM Attenuation 0x808006 I2S(1) Attenuation 0x808007 I2S(0) Attenuation 0x808008 Playback Base Count 0x000009 Playback Current Count 0x000010 Capture Base Count 0x000011 Capture Current Count 0x000012 Timer Base Count 0x000013 Timer Current Count 0x000014 Master Volume Attenuation 0x000015 CD Gain/Attenuation 0x888816 Synth Gain/Attenuation 0x888817 Video Gain/Attenuation 0x888818 Line Gain/Attenuation 0x888819 Mic/PHONE-IN Gain/Attenuation 0x888820 ADC Source Select and ADC PGA 0x000032 Chip Configuration 0x00F033 DSP Configuration 0x000034 FM Sample Rate 0x562235 I2S(1) Sample Rate 0xAC4436 I2S(0) Sample Rate 0xAC4437 Reserved 0x000038 Programmable Clock Rate 0xAC4439 3D Phat™ Stereo Control/PHONE_OUT Gain Attenuation 0x800040 Reserved 0x000041 Hardware Volume Button Modifier 0xXX1B42 DSP Mailbox 0 0x000043 DSP Mailbox 1 0x000044 Power-Down and Timer Control 0x000045 Version ID 0x000046 Reserved 0x0000

AD1821

–30– REV. 0

Table VIII. Sound System Indirect Registers

(High Byte) (Low Byte) ADDRESS 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 00 (0x00) RES LBTD [7:0] 01 (0x01) PIE CIE TIE VIE DIE RIE JIE SIE RES XC1 XC0 02 (0x02) VPSR [15.8] VPSR [7:0] 03 (0x03) VCSR [15:8] VCSR [7:0] 04 (0x04) LVM RES LVA [5:0] RVM RES RVA [5:0] 05 (0x05) LFMM RES LFMA [5:0] RFMM RES RFMA [5:0] 06 (0x06) LS1M RES LS1A [5:0] RS1M RES RS1A [5:0] 07 (0x07) LS0M RES LS0A [5:0] RS0M RES RS0A [5:0] 08 (0x08) PBC [15:8] PBC [7:0] 09 (0x09) PCC [15:8] PCC [7:0] 10 (0x0A) CBC [15:8] CBC [7:0] 11 (0x0B) CCC [15:8] CCC [7:0] 12 (0x0C) TBC [15:8] TBC [7:0] 13 (0x0D) TCC [15:8] TCC [7:0] 14 (0x0E) LMVM RES LMVA [4:0] RMVM RES RMVA [4:0] 15 (0x0F) LCDM RES LCDA [4:0] RCDM RES RCDA [4:0] 16 (0x10) LSYM RES LSYA [4:0] RSYM RES RSYA [4:0] 17 (0x11) LVDM RES LVDA [4:0] RVDM RES RVDA [4:0] 18 (0x12) LLM RES LLA [4:0] RLM RES RLA [4:0] 19 (0x13) MCM M20 RES MCA [4:0] PIM RES PIA [3:0] RES 20 (0x14) LAGC LAS [2:0] LAG [3:0] RAGC RAS [2:0] RAG [3:0] 32 (0x20) WSE CDE RES CNP RES COF [3:0] I2SF1 [1:0] I2SF0 [1:0] 33 (0x21) DS1 DS0 DIT RES ADR I1T I0T CPI PBI FMI I1I I01 DFS [2:0] 34 (0x22) FSMR [15:8] FMSR [7:0] 35 (0x23) S1SR [15:8] S1SR [7:0] 36 (0x24) S0SR [15:8] S0SR [7:0] 37 (0x25) RES RES 38 (0x26) PCR [15:8] PCR [7:0] 39 (0x27) 3DDM RES 3DD [3:0] RES POM RES POA [4:0] 40 (0x28) RES RES 41 (0x29 ) RES VMU VUP VDN BM [4:0] 42 (0x2A) MB0R [15:8] MB0R [7:0] 43 (0x2B) MB1R [15:8] MB1R [7:0] 44 (0x2C) CPD RES PIW PIR PAA PDA PDP PTB 3D PD3D GPSP RES 45 (0x2D) VER [15:8] VER [7:0] 46 (0x2E) RES RES

[00] INDIRECT LOW BYTE TMP DEFAULT = [0xXX]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RES LBTD [7:0]

LBTD [7:0] Low Byte Temporary Data holding latch for register pair writes;Written on any write to [SSBase + 2],Read from [SSBase + 2] when the indirect address is 0x00.

[01] INTERRUPT ENABLE AND EXTERNAL CONTROL DEFAULT = [0x0102]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

PIE CIE TIE VIE DIE RIE JIE SIE RES XC1 XC0

XC0 RW External Control 0. The state of this bit is reflected on the XCTL0 pin. This pin is also muxed withPCLKO. COF must be greater than 11 for PCLKO to be disabled, see SS [32].

XC1 RW External Control 1. The state of this bit is reflected on the XCTL1 pin. XCTL1 may also be used forRing-In Interrupt.

SIE RW SoundBlaster Interrupt Enable;0 SoundBlaster Interrupt disabled1 SoundBlaster Interrupt enabled

JIE RW Joystick Interrupt Enable;0 Joystick Interrupt disabled1 Joystick Interrupt enabled

AD1821

–31–REV. 0

RIE RW Ring Interrupt Enable;0 Ring Interrupt disabled1 Ring Interrupt enabled

DIE RW DSP Interrupt Enable;0 DSP Interrupt disabled1 DSP Interrupt enabled

VIE RW Volume Interrupt Enable. If enabled, software increments/decrements BUTTON MODIFIER viainterrupt routine and pushing buttons only sets VUP, VDN, VMU bits. It does not change the volume.0 Volume Interrupt disabled1 Volume Interrupt enabled

TIE RW Timer Interrupt Enable;0 Timer Interrupt disabled1 Timer Interrupt enabled

CIE RW Capture Interrupt Enable;0 Capture Interrupt disabled1 Capture Interrupt enabled

PIE RW Playback Interrupt Enable;0 Playback Interrupt disabled1 Playback Interrupt enabled

[02] VOICE PLAYBACK SAMPLE RATE DEFAULT = [0x1F40]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1

VPSR [15:8] VPSR [7:0]

VPSR [15:0] Voice Playback Sample Rate. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments. Thedefault playback sample rate is 8 kHz.

[03] VOICE CAPTURE SAMPLE RATE DEFAULT = [0x1F40] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

VCSR [15:8] VCSR [7:0]

VCSR [15:0] Voice Capture Sample Rate. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments.Ignored if CNP bit in SS [32] = 0 in which case VPSR [15:0] controls capture rate. The default capture sample rateis 8 kHz.

[04] VOICE ATTENUATION DEFAULT = [0x8080]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LVM RES LVA [5:0] RVM RES RVA [5:0]

RVA [5:0] Right Voice Attenuation for Playback channel. The LSB represents –1.5 dB, 000000 = 0 dB and the range is0 dB to –94.5 dB.

RVM Right Voice Mute. 0 = Unmuted, 1 = Muted.LVA [5:0] Left Voice Attenuation for Playback channel. The LSB represents –1.5 dB, 000000 = 0 dB and the range is

0 dB to –94.5 dBLVM Left Voice Mute. 0 = Unmuted, 1 = Muted.

[05] FM ATTENUATION DEFAULT = [0x8080]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LFMM RES LFMA [5:0] RFMM RES RFMA [5:0]

RFMA [5:0] Right F Music Attenuation for the internal Music Synthesizer. The LSB represents –1.5 dB, 000000 = 0 dB andthe range is 0 dB to –94.5 dB.

RFMM Right F Music Mute. 0 = Unmuted, 1 = Muted.LFMA [5:0] Left F Music Attenuation for the internal Music Synthesizer. The LSB represents –1.5 dB, 000000 = 0 dB and the

range is 0 dB to –94.5 dB.LFMM Left F Music Mute. 0 = Unmuted, 1 = Muted.

[06] I2S(1) ATTENUATION DEFAULT = [0x8080]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LS1M RES LS1A [5:0] RS1M RES RS1A [5:0]

RS1A [5:0] Right I2S(1) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.

AD1821

–32– REV. 0

RS1M Right I2S(1) Mute. 0 = Unmuted, 1 = Muted.LS1A [5:0] Left I2S(1) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.LS1M Left I2S(1) Mute. 0 = Unmuted, 1 = Muted.

[07] I2S(0) ATTENUATION DEFAULT = [0x8080]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LS0M RES LS0A [5:0] RS0M RES RS0A [5:0]

RS0A [5:0] Right I2S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.RS0M Right I2S(0) Mute. 0 = Unmuted, 1 = Muted.LS0A [5:0] Left I2S(0) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range is 0 dB to –94.5 dB.LS0M Left I2S(0) Mute. 0 = Unmuted, 1 = Muted.

[08] PLAYBACK BASE COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

PBC [15:8] PBC [7:0]

PBC [15:0] Playback Base Count. This register is for loading the Playback DMA Count. Writing a value to this register alsoloads the same data into the Playback Current Count register. You must load this register when Playback Enable(PEN) is deasserted. When PEN is asserted, the Playback Current Count decrements once for every four bytestransferred via a DMA cycle. The next transfer, after zero is reached in the Playback Current Count, will generatean interrupt and reload the Playback Current Count with the value in the Playback Base Count. The Playback BaseCount should always be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). Thecircular software DMA buffer must be divisible by four to ensure proper operation.

[09] PLAYBACK CURRENT COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

PCC [15:8] PCC [7:0]

PCC [15:0] Playback Current Count register. Contains the current Playback DMA Count. Reads and Writes must be donewhen PEN is deasserted.

[10] CAPTURE BASE COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CBC [15:8] CBC [7:0]

CBC [15:0] Capture Base Count. This register is for loading the Capture DMA Count. Writing a value to this register alsoloads the same data into the Capture Current Count register. Loading must be done when Capture Enable (CEN)is deasserted. When CEN is asserted, the Capture Current Count decrements once for every four bytes transferredvia a DMA cycle. The next transfer, after zero is reached in the Capture Current Count, will generate an interruptand reload the Capture Current Count with the value in the Capture Base Count. The Capture Base Count shouldalways be programmed to Number Bytes divided by four, minus one ((Number Bytes/4) –1). The circular softwareDMA buffer must be divisible by four to ensure proper operation.

[11] CAPTURE CURRENT COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CCC [15:8] CCC [7:0]

CCC [15:0] Capture Current Count register. Contains the current Capture DMA Count. Reading and Writing must be donewhen CEN is deasserted.

[12] TIMER BASE COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

TBC [15:8] TBC [7:0]

TBC [15:0] Timer Base Count. Register for loading the Timer Count. Writing a value to this register also loads the same datainto the Timer Current Count register. Loading must be done when Timer Enable (TE) is deasserted. When TE isasserted, the Timer Current Count register decrements once for every specified time period. The time period (10 µsor 100 ms) is programmed via the PTB bit in SS [44]. When TE is asserted, the Timer Current Count decrements onceevery time period. The next count, after zero is reached in the Timer Current Count register, will generate an interruptand reload the Timer Current Count register with the value in the Timer Current Count register.

AD1821

–33–REV. 0

[13] TIMER CURRENT COUNT DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

TCC [15:8] TCC [7:0]

TCC [15:0] Timer DMA Current Count register. Contains the current timer count. Reading and Writing must be done whenTE is deasserted.

[14] MASTER VOLUME ATTENUATION DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LMVM RES LMVA [4:0] RMVM RES RMVA [4:0]

RMVA [4:0] Right Master Volume Attenuation. The LSB represents –1.5 dB, 00000 = 0 dB and the range is 0 dB to–46.5 dB. This register is added with the Hardware Volume Button Modifier value to produce the final DAC MasterVolume attenuation level. See Hardware Volume Button Modifier Register description for more details.

RMVM Right Master Volume Mute. 0 = Unmuted, 1 = Muted.LMVA [4:0] Left Master Volume Attenuation. The LSB represents –1.5 dB, 00000 = 0 dB and the range is 0 dB to

–46.5 dB. This register is added with the Hardware Volume Button Modifier value to produce the final DAC MasterVolume attenuation level. See Hardware Volume Button Modifier Register description for more details.

LMVM Left Master Volume Mute. 0 = Unmuted, 1 = Muted.

[15] CD GAIN/ATTENUATION DEFAULT = [0x8888]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LCDM RES LCDA [4:0] RCDM RES RCDA [4:0]

RCDA [4:0] Right CD Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.RCDM Right CD Mute. 0 = Unmuted, 1 = Muted.LCDA [4:0] Left CD Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.LCDM Left CD Mute. 0 = Unmuted, 1 = Muted.

[16] SYNTH GAIN/ATTENUATION DEFAULT = [0x8888]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LSYM RES LSYA [4:0] RSYM RES RSYA [4:0]

RSYA [4:0] Right SYNTH Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.RSYM Right SYNTH Mute. 0 = Unmuted, 1 = Muted.LSYA [4:0] Left SYNTH Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.LSYM Left SYNTH Mute. 0 = Unmuted, 1 = Muted.

[17] VID GAIN/ATTENUATION DEFAULT = [0x8888]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LVDM RES LVDA [4:0] RVDM RES RVDA [4:0]

RVDA [4:0] Right VID Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.RVDM Right VID Mute. 0 = Unmute, 1 = Muted.LVDA [4:0] Left VID Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.LVDM Left VID Mute. 0 = Unmuted, 1 = Muted.

[18] LINE GAIN/ATTENUATION DEFAULT = [0x8888]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LLM RES LLA [4:0] RLM RES RLA [4:0]

RLA [4:0] Right LINE Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.RLM Right Line Mute. 0 = Unmuted, 1 = Muted.LLA [4:0] Left LINE Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is +12 dB to –34.5 dB.LLM Left Line Mute. 0 = Unmuted, 1 = Muted.

AD1821

–34– REV. 0

[19] MIC/PHONE_IN GAIN/ATTENUATION DEFAULT = [0x8888]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MCM M20 RES MCA [4:0] PIM RES PIA [3:0] RES

PIA [3:0] PHONE_IN Attenuation. The LSB represents –3 dB, 0000 = 0 dB and the range is 0 dB to –45 dB.PIM PHONE_IN Mute.MCA [4:0] Microphone Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is ±12 dB to –34.5 dB.M20 Microphone 20 dB Gain. The M20-bit enables the Microphone +20 dB gain stage.MCM Microphone Mute.

[20] ADC SOURCE SELECT AND ADC PGA DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

LAGC LAS [2:0] LAG [3:0] RAGC RAS [2:0] RAG [3:0]

RAG [3:0] Right ADC Gain Control ADC source select and Gain. For Gain, LSB represents +1.5 dB, 0000 = 0 dBand the range is 0 dB to +22.5 dB.

RAGC Right Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled.LAG [3:0] Left ADC Gain Control ADC source select and Gain. For Gain, LSB represents +1.5 dB, 0000 = 0 dB

and the range is 0 dB to +22.5 dB.LAGC Left Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled.

RAS [2:0] ADC Right Input Source LAS [2:0] ADC Left Input Source000 R_LINE 000 L_LINE001 R_OUT 001 L_OUT010 R_CD 010 L_CD011 R_SYNTH 011 L_SYNTH100 R_VID 100 L_VID101 Mono Mix 101 MIC110 Reserved 110 PHONE_IN111 Reserved 111 Reserved

[32] CHIP CONFIGURATION DEFAULT = [0x00F0]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

WSE CDE RES CNP RES IME IMR COF [3:0] I2SF1 [1:0] I2SF0 [1:0]

I2SF0 [1:0] I2S Port Configuration for serial data type.I2SF1 [1:0] 00 Disabled

01 Right Justified10 I2S Justified11 Left Justified

COF [3:0] Clock Output Frequency. Programmable clock output on PCLKO pin is determined using the following formulaPCLKO = 256 × PCR/2COF where COF = 0:11 and PCR is the value of the Programmable Clock Rate Register,SS [38]. If COF > 11, then PCLKO is disabled.

CNP Capture not equal to Playback.0 = Capture equals Playback. The capture sample rate is determined by the playback sample rate in SS [02].1 = Capture not equal to Playback.

CDE CD Enable, Set to “1” when a CD player is connected to I2S (0).WSE Sound System Enable.

0 = SoundBlaster Mode.1 = Sound System Mode under Windows.

Note: When in SoundBlaster Mode, the Codec ADC and DAC channels will be used solely for convertingSoundBlaster data.

AD1821

–35–REV. 0

[33] DSP CONFIGURATION DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

DS1 DS0 DIT RES ADR I1T I0T CPI PBI FMI I1I I0I DFS [2:0]

DFS [2:0] DSP Frame Sync Source. Sets the DSP Port Frame Sync according to the following source.000—Maximum Frame Rate001—I2S(0) Sample Rate010—I2S(1) Sample Rate011—Music Synthesizer Sample Rate100—Sound System Playback Sample Rate101—Sound System Capture Sample Rate111—Reserved

I0I I2S(0) Data Intercept. 0 = Disable, 1 = Intercept I2S(0) Data Enabled.I1I I2S(1) Data Intercept. 0 = Disable, 1 = Intercept I2S(1) Data Enabled.FMI FM Music Synthesizer Data Intercept. 0 = Disable, 1 = Intercept FM Music Data Enabled.PBI Playback Data Intercept. 0 = Disable, 1 = Intercept Playback Data Enabled.CPI Capture Data Intercept. 0 = Disable, 1 = Intercept Capture Data Enabled.I0T I2S(0) Takeover Data. 0 = Disable, 1 = Enabled.I1T I2S(1) Takeover Data. 0 = Disable, 1 = Enabled.ADR Audio Resync. Writing “1” causes all FIFOs in the DSP port to be re-initialized.DIT DSP Interrupt. A write to this bit causes an ISA interrupt if DIE is asserted.DS0 DSP Mailbox 0 Status. 0 = last access indicates read, 1 = last access indicates write.DS1 DSP Mailbox 1 Status. 0 = last access indicates read, 1 = last access indicates write.

[34] FM SAMPLE RATE DEFAULT = [0x5622] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

FMSR [15:8] FMSR [7:0]

FMSR [15:0] F Music Sample Rate register. The sample rate can be programmed from 4 kHz to 27.6 kHz in 1 hertz increments.

[35] I2S(1) SAMPLE RATE DEFAULT = [0xAC44] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

S1SR [15:8] S1SR [7:0]

S1SR [15:0] I2S(1) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments.Programming this register has no effect unless I2SF1 [1:0] is enabled.

[36] I2S(0) SAMPLE RATE DEFAULT = [0xAC44]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

S0SR [15:8] S0SR [7:0]

S0SR [15:0] I2S(0) Sample Rate register. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments.Programming this register has no effect unless I2SF0 [1:0] is enabled.

[37] RESERVED DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RES RES

[38] PROGRAMMABLE CLOCK RATE DEFAULT = [0xAC44]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

PCR [15:8] PCR [7:0]

PCR [15:0] Programmable Clock Rate register. The clock rate can be programmed from 25 kHz to 50 kHz in 1 hertzincrements. This register is only valid when the COF bits in SS [32] are set for the multiplier factor. PCLKO =256 × PCR/2COF. See SS [32] for determining the value of COF.

[39] 3D Phat™ Stereo Control and PHONE_OUT Attenutation DEFAULT = [0x8000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

3DDM RES 3DD [3:0] RES POM RES POA [4:0]

POA [4:0] PHONE_OUT Attenuation. The LSB represents –1.5 dB, 0000 = 0 dB and the range is 0 dB to –46.5 dB.

AD1821

–36– REV. 0

POM PHONE-OUT Mute. 0 = Unmuted, 1 = Muted.3DD [3:0] 3D Depth Phat™ Stereo Enhancement Control. The LSB represents 6 2/3% phase expansion, 0000 = 0% and

the range is 0% to 100%.3DDM 3D Depth Mute. Writing a “1” to this bit has the same affect as writing 0s to 3DD [3:0] bits, and causes

the Phat™ 3D Stereo Enhancement to be turned off. 0 = Phat™* Stereo is on, 1 = Phat™ Stereo is off.

[40] RESERVED DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RES RES

[41] HARDWARE VOLUME BUTTON MODIFIER DEFAULT = [0xXX1B] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RES VMU VUP VDN BM [4:0]

BM [4:0] Button ModifierVDM Volume DownVUP Volume UpVMU Volume Mute

This register contains a Master Volume attenuation offset, which can be incremented or decremented via the Hardware VolumePins. This register is summed with the Master Volume attenuation to produce the actual Master Volume DAC attenuation. A mo-mentary grounding of greater than 50 ms on the VOL_UP pin will cause a decrement (decrease in Attenuation) in this register.Holding the pin LO for greater than 200 ms will cause an auto-decrement every 200 ms. This is also true for a momentary ground-ing of the VOL_DN pin. A momentary grounding of both the VOL_UP and VOL_DN causes a mute and no increment or decre-ment to occur.

When Muted, an unmute is possible by a momentary grounding of both the VOL_UP and VOL_DN pins together, a momen-tary grounding of VOL_UP (this also causes a volume increase), a momentary grounding of VOL_DN (this also causes a volumedecrease) or a write of “0” to the VI bit in SS [BASE+1].

[42] DSP MAILBOX 0 DEFAULT = [0x0000] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MB0R [15:8] MB0R [7:0]

MB0R [15:0] This register is used to send data and control information to and from the DSP.

[43] DSP MAILBOX 1 DEFAULT = [0x0000] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MB1R [15:8] MB1R [7:0]

MB1R [15:0] This register is used to send data and control information to and from the DSP.

[44] POWER-DOWN AND TIMER CONTROL DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CPD RES PIW PIR PAA PDA PDP PTB 3D PD3D GPSP RES

The AD1821 supports a timeout mechanism used in conjunction with the Timer Base Count and Timer Current Count registersto generate a power-down interrupt. This interrupt allows software to power down the entire chip by setting the CPD bit. Thispower-down control feature lets users program a time interval from 1 ms to approximately 1.8 hours in 1 ms increments. Fivepower-down count reload enable bits are used to reload the Timer Current Count from the Timer Base Count when activity isseen on that particular channel.

Programming Example: Generate Interrupt if No ISA Reads or Writes occur within 15 Minutes.1) Write [SSBASE+0] with 0x0C ; Write Indirect address for TIMER BASE COUNT “register 12”2) Write [SSBASE+2] with 0x28 ; Write TIMER BASE COUNT with (15 min × 60 sec/min × 10) = 0x2328 mili-Seconds3) Write [SSBASE+3] with 0x23 ; Write High byte of TIMER BASE COUNT4) Write [SSBASE+0] with 0x2C ; Write Indirect address for POWER-DOWN and TIMER CONTROL register5) Write [SSBASE+2] with 0x00 ; Write Low byte of POWER-DOWN and TIMER CONTROL register6) Write [SSBASE+3] with 0x30 ; Set Enable bits for PIW & PIR7) Write [SSBASE+0] with 0x01 ; Write Indirect address for INTERRUPT CONFIG register8) Write [SSBASE+2] with 0x82 ; Set the TE (Timer Enable) bit9) Write [SSBASE+3] with 0x20 ; Set the TIE (Timer Interrupt Enable) bit

AD1821

–37–REV. 0

GPSP Game Port Speed Select. Selects the operating speed of the game port.0 Slow Game Port1 Fast Game Port

PD3D Power-Down 3D. Turns off internal Phat™ Stereo circuitry.0 On1 Off

3D 3D Analog Mixer Bypass. Allows the analog output of the D/A converters to bypass the Phat™ Stereo Circuit. Enablesultimate flexibility for mixing and any combination of 3D enhanced analog signals or non-3D enhanced signals withthe DAC output.0 3D Phat™ Stereo Enabled for DAC Output1 3D Phat™ Stereo Bypassed for DAC Output

PTB Power-Down Time Base. 1 = timer set to 100 ms, 0 = timer set to 10 µs.PDP Power-down count reload on DSP Port enabled; “1” = Reload count if DSP Port enabled. DSP Port is enabled when

Slot 0 of SDI of the DSP Serial Port Input is Alive (Bit 7 = 1).

PDA Power-down count reload on Digital Activity; “1” = Reload count on Digital Activity. Digital Activity is defined as anyactivity on (I2S0, I2S1, FM or PLAYBACK).

PAA Power-down count reload on Analog Activity; “1” = Reload count on Analog Activity. Analog Activity is defined as anyanalog input unmuted (LINE, CD, SYNTH, MIC, MONO) or MASTER VOLUME unmuting.

PIR Power-down count reload on ISA Read; “1” = Reload count on ISA read. ISA Read is defined as a read from any activelogical device inside the AD1821.

PIW Power-down count reload on ISA Write; “1” = Reload count on ISA write. ISA Write defined as a write to any activelogical device inside the AD1821.

CPD Chip Power-Down1 Power-Down;0 Power-Up

For Power-up, software should poll the [SSBASE+0] CRY bit for “1” before writing or reading any logical device.

[45] VERSION ID DEFAULT = [0x0000]7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

VER [15:8] VER [7:0]

[46] RESERVED DEFAULT = [0x0000] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

RES RES

Test register. Should never be written or read under normal operation.

SB Pro; AdLib RegistersThe AD1821 contains sets of ISA Bus registers (ports) that correspond to those used by the SoundBlaster Pro audio card fromCreative Labs and the AdLib audio card from AdLib Multimedia. Table IX lists the ISA Bus SoundBlaster Pro registers. Table Xlists the ISA Bus AdLib registers. Because the AdLib registers are a subset of those in the SoundBlaster card, you can find completeinformation on using both of these registers in the Developer Kit for SoundBlaster Series, 2nd ed. © 1993, Creative Labs, Inc.,1901 McCarthy Blvd., Milpitas, CA 95035.

Table IX. SoundBlaster Pro ISA Bus Registers

Register Name ISA Bus Address

Music0: Address (w), Status (r) 0x(SB Base) Relocatable in range 0x010 – 0x3F0Music0: Data (w) 0x(SB Base+1)Music1: Address (w) 0x(SB Base+2)Music1: Data (w) 0x(SB Base+3)Mixer Address (w) 0x(SB Base+4)Mixer Data (w) 0x(SB Base+5)Reset (w) 0x(SB Base+6)Music0: Address (w) 0x(SB Base+8)Music0: Data (w) 0x(SB Base+9)Input Data (r) 0x(SB Base+A)Status (r), Output Data (w) 0x(SB Base+C)Status (r) 0x(SB Base+E)

AD1821

–38– REV. 0

Table X. AdLib ISA Bus Registers

Register Name ISA Bus Address

Music0: Address (w), Status (r) 0x(Adlib Base) Relocatable in range 0x008 – 0x3F8Music0: Data (w) 0x(Adlib Base+1)Music1: Address (w) 0x(Adlib Base+2)Music1: Data (w) 0x(Adlib Base+3)

MIDI and MPU-401 RegistersThe AD1821 contains a set of ISA Bus registers (ports) that correspond to those used by the ISA bus MIDI audio interface cards.Table XI lists the ISA Bus MIDI registers. These registers support commands and data transfers described in MIDI 1.0 DetailedSpecification and Standard MIDI Files 1.0, © 1994, MIDI Manufacturers Association, PO Box 3173 La Habra, CA 90632-3173.

Table XI. MIDI ISA Bus Registers

Register Name Address

MIDI Data (r/w) 0x(MIDI Base) Relocatable in range 0x008 to 0x3F8MIDI Status (r), Command (w) 0x(MIDI Base+1)

0x(MIDI Base+1)BIT 7 6 5 4 3 2 1 0

STATE 1 0 0 0 0 0 0 0NAME DRR DSR RESERVED

DSR (R) Data Send Ready. When read, this bit indicates that you can (0) or cannot (1) write to theMIDI Data register. (Full = 1, Empty = 0)

DRR (R) Data Receive Ready. When read, this bit indicates that you can (0) or cannot (1) read from theMIDI Data register. (Unreadable = 1, Readable = 0)

CMD [7:0] (W) MIDI Command. Write MPU-401 commands to bits [7:0] of this register.

NOTESThe AD1821 supports only the MIDI 0xFF (reset) and 0x3F (pass-through mode) commands. The controller powers setup for intel-ligent MIDI mode, but must be put in pass-through mode. To start MIDI operations, send a reset command (0xFF) and then send apass-through mode command (0x3F). The MIDI data register contains an acknowledge byte (0xFE) after each command transfer.

All commands return an ACK byte in “smart” mode.

Status commands (0xAx) return ACK and a data byte; all other commands return ACK.

All commands except reset (0xFF) are ignored in UART mode. No ACK bytes are returned.

“Smart” mode data transfers are not supported.

Game Port RegistersThe AD1821 contains a Game Port ISA Bus Register that corresponds to the game port described in the PnP specification.

Table XII. Game Port ISA Bus Registers

Register Name Address

Game Port I/O 0x(Game Port Base+0 to Game Port Base+7Relocatable in the range 0x100 to 0x3F8

AD1821

–39–REV. 0

APPENDIX AAD1821JS and AD1821JS-M

Contains the internal ROM code on the AD1821JS. Consult the Reference Design Guide for external EEPROM Code.

AD1821JS PLUG AND PLAY INTERNAL ROMNote: All addresses are depicted in hexidecimal notation.Vendor ID: ADS7180Serial Number: FFFFFFFFChecksum: B6PNP Version: 1.0, vendor version: 11ASCII string: Analog DevicesLogical Device ID: ADS7180

not a boot device, implements PNP register(s) 31Start dependent function, best config

IRQ: channel(s) 5 7type(s) active-high, edge-triggered

DMA: channel(s) 1Type F, count-by-byte, nonbus-mastering, 8-bit only

DMA: channel(s) 0 1 3Type F, count-by-byte, nonbus-mastering, 8-bit only

I/O: 16-bit decode, range [0220,0240] mod 20, length 10I/O: 16-bit decode, range [0388,0388] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, acceptable configIRQ: channel(s) 5 7 10

type(s) active-high, edge-triggeredDMA: channel(s) 0 1 3

Type F, count-by-byte, nonbus-mastering, 8-bit onlyDMA: channel(s) 0 1 3

Type F, count-by-byte, nonbus-mastering, 8-bit onlyI/O: 16-bit decode, range [0220,0240] mod 20, length 10I/O: 16-bit decode, range [0388,0388] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, acceptable configIRQ: channel(s) 5 7 9 10 11 15



Type F, count-by-byte, nonbus-mastering, 8-bit only

I/O: 16-bit decode, range [0220,02E0] mod 20, length 10I/O: 16-bit decode, range [0388,03B8] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, suboptimal configIRQ: channel(s) 5 7 10


Type F, count-by-byte, nonbus-mastering, 8-bit onlyDMA: NULLI/O: 16-bit decode, range [0220,02E0] mod 20, length 10I/O: 16-bit decode, range [0388,03B8] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

End all dependent functionsLogical Device ID: ADS7181

not a boot device, implements PNP register(s) 31Compatible Device ID: PNPB006Start dependent function, best config

IRQ: channel(s) 5 7 9 11type(s) active-high, edge-triggered

I/O: 16-bit decode, range [0300,0330] mod 30, length 02Start dependent function, acceptable config

IRQ: channel(s) 5 7 9 10 11 15type(s) active-high, edge-triggered

I/O: 16-bit decode, range [0300,0420] mod 30, length 02End all dependent functionsLogical Device ID: ADS7182

not a boot device, implements PNP register(s) 31Compatible Device ID: PNPB02FStart dependent function, best config


I/O: 16-bit decode, range [0200,0208] mod 08, length 08End all dependent functionsEnd:

AD1821

–40– REV. 0

Contains the internal ROM code on the AD1821JS-M. Consult the Reference Design Guide for external EEPROM Code.

AD1821JS-M PLUG AND PLAY INTERNAL ROMVendor ID: ADS7181Serial Number: FFFFFFFFChecksum: 2FPNP Version: 1.0, vendor version: 20ASCII string: Analog DevicesLogical Device ID: ADS7180

not a boot device, implements PNP register(s) 31Start dependent function, best config

IRQ: channel(s) 5 7type(s) active-high, edge-triggered

DMA: channel(s) 1Type F, count-by-byte, nonbus-mastering, 8-bit only

DMA: channel(s) 0 1 3Type F, count-by-byte, nonbus-mastering, 8-bit only

I/O: 16-bit decode, range [0220,0240] mod 20, length 10I/O: 16-bit decode, range [0388,0388] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, acceptable configIRQ: channel(s) 5 7 10



Type F, count-by-byte, nonbus-mastering, 8-bit onlyI/O: 16-bit decode, range [0220,0240] mod 20, length 10I/O: 16-bit decode, range [0388,0388] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, acceptable configIRQ: channel(s) 5 7 9 10 11 15



Type F, count-by-byte, nonbus-mastering, 8-bit only

I/O: 16-bit decode, range [0220,02E0] mod 20, length 10I/O: 16-bit decode, range [0388,03B8] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

Start dependent function, suboptimal configIRQ: channel(s) 5 7 9 10 11 15


Type F, count-by-byte, nonbus-mastering, 8-bit onlyDMA: NULLI/O: 16-bit decode, range [0220,02E0] mod 20, length 10I/O: 16-bit decode, range [0388,03B8] mod 08, length 04I/O: 16-bit decode, range [0500,0560] mod 10, length 10

End all dependent functionsLogical Device ID: ADS7181

not a boot device, implements PNP register(s) 31Compatible Device ID: PNPB006Start dependent function, best config

IRQ: channel(s) 5 7 9 11type(s) active-high, edge-triggered


IRQ: channel(s) 5 7 9 10 11 15type(s) active-high, edge-triggered

I/O: 16-bit decode, range [0300,0420] mod 30, length 02End all dependent functionsLogical Device ID: ADS7182

not a boot device, implements PNP register(s) 31Compatible Device ID: PNPB02FStart dependent function, best config


I/O: 16-bit decode, range [0200,0208] mod 08, length 08End all dependent functionsEnd:

AD1821

–41–REV. 0

APPENDIX B

PLUG AND PLAY KEY AND “ALTERNATE KEY” SEQUENCESOne additional feature of the AD1821 is an alternate programming method used, for example, if a BIOS wants to assume control ofthe AD1821 and present DEVNODES to the OS (rather than having the device participate in Plug and Play enumeration). The fol-lowing technique may be used.

Instead of the normal 32 byte Plug and Play key sequence, an alternate 126 byte key is used. After the 126 byte key, the AD1821device will transition to the Plug and Play “config” state. It can then be programmed as usual using the standard Plug and Play ports.After programming, the AD1821 should be sent to the Plug and Play “WFK” (wait for key) state. Once the AD1821 has seen the al-ternate key, it will no longer parse for the Plug and Play key (and therefore never participate in Plug and Play enumeration). It can bereprogrammed by reissuing the alternate key again.

Both the Plug and Play key and the alternate key are sequences of writes to the Plug and Play address register, 0x279. Below are theISA data values of both keys.

This is the standard Plug and Play sequence:

6a b5 da ed f6 fb 7d be df 6f 37 1b 0d 86 c3 61b0 58 2c 16 8b 45 a2 d1 e8 74 3a 9d ce e7 73 39

This is the longer, 126-byte alternate key. It is generated by the function:f[n+1] = (f[n] >> 1)| (((f[n] ^ (f[n] >> 1)) & 0x01) << 6) f[0] = 0x0101 40 20 10 08 04 02 41 60 30 18 0c 06 43 21 5028 14 0a 45 62 71 78 3c 1e 4f 27 13 09 44 22 5168 34 1a 4d 66 73 39 5c 2e 57 2b 15 4a 65 72 797c 3e 5f 2f 17 0b 05 42 61 70 38 1c 0e 47 23 1148 24 12 49 64 32 59 6c 36 5b 2d 56 6b 35 5a 6d76 7b 3d 5e 6f 37 1b 0d 46 63 31 58 2c 16 4b 2552 69 74 3a 5d 6e 77 3b 1d 4e 67 33 19 4c 26 5329 54 2a 55 6a 75 7a 7d 7e 7f 3f 1f 0f 07

AD1821

–42– REV. 0

PROGRAMMING EXTERNAL EEPROMSThe PnP EEPROM can be written only in the “Alternate Key State”; this prevents accidental EEPROM erasure when using stan-dard PnP setup. The procedure for writing an EEPROM is:

1) Enter PnP configuration state and fully reset the part by writing 0x07 to PnP register 0x02. This step can be eliminated if the parthas not been accessed since power-up, a previous full PnP reset or assertion of the ISA bus RESET signal.

2) Send the alternate initiation key to the PnP address port. EEPROM writes are disabled if the standard PnP key is used.

3) Enter isolation state and write a CSN to enter configuration state. Do not perform any isolation reads.

4) Poll PnP register 0x05 until it equals 0x01 and wait at least 336 microseconds (ensures that EEPROM is idle).

5) Write the second byte of your serial identifier to PnP register 0x20.

6) Read PnP register 0x04.

7) Wait for at least 464 microseconds, plus the EEPROM’s write cycle time (up to 10 ms for a Xicor X24C02).

8) Repeat steps 4 through 7 for each byte in your PnP ROM, starting with the third byte of the serial identifier and ending with thefinal checksum byte. You must then continue to write filler bytes until 512 bytes, minus one more than the number of flag bytes,have been written. Finally, write the flag byte(s) (described above) and the first byte of the serial identifier.

9) Fully reset the part by writing 0x07 to PnP register 0x02.

The AD1821 will now act according to the contents of the EEPROM.

NOTESProgramming will not work if more than one part uses the same alternate initiation key in the system.

If a 256-byte EEPROM is used, it is not necessary to wait 10 ms after writing bytes 255 to 511, because the EEPROM will ignorethem anyway.

You can skip over bytes that you don’t care to write by just performing a ROM read instead of a ROM write followed by a ROM read.

REFERENCE DESIGNS AND DEVICE DRIVERSReference designs and device drivers for the AD1821 are available via the Analog Devices Home Page on the World Wide Web athttp://www.analog.com. Reference designs may also be obtained by contacting your local Analog Devices Sales representative orauthorized distributor.

AD1821

–43–REV. 0

xFS

0

–100

–10

–40

–60

–80

–90

–20

–30

–50

–70

–110

0 0.80.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9 1

dB

a. ADC Audio/Modem

xFS

0

–0.1

–0.2

0 0.1

dB

0.2 0.3 0.4

b. ADC Audio/Modem Passband

Figure 16. AD1821 Frequency Response Plots (Full-Scale Line-Level Input, 0 dB Gain). The Plots Do Not Reflect the AdditionalBenefits of the On-Chip Analog Filters. Out-of-Band Images Will Be Attenuated by an Additional 31.4 dB at 100 kHz.

xFS

0

–200

0 81 2 3 4 5 6 7

–20

–80

–120

–160

–180

–40

–60

–100

–140

dB

c. DAC Audio/Modem

xFS

0

–0.1

–0.2

0 0.1

dB

0.2 0.3 0.4

d. DAC Audio/Modem Passband

AD1821

–44– REV. 0

C30

57–1

2–7/

97P

RIN

TE

D IN

U.S

.A.

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

100-Lead Plastic Quad Flatpack(S-100)

81

1001

5080

3130

51

TOP VIEW(PINS DOWN)

PIN 1

0.015 (0.35)0.009 (0.25)

0.923 (23.45)0.903 (22.95)

0.742 (18.85) TYP

0.791 (20.10)0.783 (19.90)

0.68

7 (1

7.45

)0.

667

(16.

95)

0.48

6 (1

2.35

) T

YP

0.55

5 (1

4.10

)0.

547

(13.

90)

0.029 (0.73)0.023 (0.57)

SEATINGPLANE

0.096(2.45)MAX

0.037 (0.95)0.026 (0.65)

0.004 (0.10)MAX

0.010 (0.25)MIN

0.083 (2.10)0.075 (1.90)

ad1821 modio soundcomm* host signal processing codec

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