ad9248
TRANSCRIPT
14-Bit, 20 MSPS/40 MSPS/65 MSPSDual A/D Converter
AD9248
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES Integrated dual 14-bit ADC Single 3 V supply operation (2.7 V to 3.6 V) SNR = 71.6 dB (to Nyquist, AD9248-65) SFDR = 80.5 dBc (to Nyquist, AD9248-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 MHz, 3 dB bandwidth Exceptional crosstalk immunity > 85 dB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer Output datamux option
APPLICATIONS Ultrasound equipment Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and hold amplifiers (SHAs) and an integrated voltage reference. The AD9248 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and to guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for various applications, including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available and can compensate for wide variations in the clock duty cycle, allowing the converter to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow.
FUNCTIONAL BLOCK DIAGRAM
VIN+_A
VIN–_A
REFT_A
REFB_A
VREF
SENSE
AGND
REFT_B
REFB_B
VIN+_B
VIN–_B
OTR_A
D13_A TO D0_A
OEB_A
MUX_SELECTCLK_ACLK_BDCS
SHARED_REFPWDN_APWDN_BDFS
OTR_B
D13_B TO D0_B
OEB_B
AVDD AGND
DRVDD DRGND
14
AD9248
14
0.5V
OUTPUTMUX/
BUFFERS
1414 OUTPUTMUX/
BUFFERS
CLOCKDUTY CYCLESTABILIZER
MODECONTROL
ADC
SHA
SHA
0444
6-00
1
ADC
Figure 1.
Fabricated on an advanced CMOS process, the AD9248 is available in a Pb-free, space saving, 64-lead LQFP or LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/ 40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS allow flexibility between power, cost, and performance to suit an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW, AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS = 180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/ AD9248-65) maintains performance over a wide range of clock duty cycles.
6. Multiplexed data output option enables single-port operation from either Data Port A or Data Port B.
AD9248
Rev. B | Page 2 of 48
TABLE OF CONTENTS Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Absolute Maximum Ratings ............................................................ 8
Explanation of Test Levels ........................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input ............................................................................... 17
Clock Input and Considerations .............................................. 18
Power Dissipation and Standby Mode ..................................... 19
Digital Outputs ........................................................................... 19
Timing .......................................................................................... 19
Data Format ................................................................................ 20
Voltage Reference ....................................................................... 20
AD9248 LQFP Evaluation Board ................................................. 22
Clock Circuitry ........................................................................... 22
Analog Inputs ............................................................................. 22
Reference Circuitry .................................................................... 22
Digital Control Logic ................................................................. 22
Outputs ........................................................................................ 22
LQFP Evaluation Board Bill of Materials (BOM) .................. 24
LQFP Evaluation Board Schematics ........................................ 25
LQFP PCB Layers ....................................................................... 29
Dual ADC LFCSP PCB .................................................................. 35
Power Connector ........................................................................ 35
Analog Inputs ............................................................................. 35
Optional Operational Amplifier .............................................. 35
Clock ............................................................................................ 35
Voltage Reference ....................................................................... 35
Data Outputs ............................................................................... 35
LFCSP Evaluation Board Bill of Materials (BOM) ................ 36
LFCSP PCB Schematics ............................................................. 37
LFCSP PCB Layers ..................................................................... 40
Thermal Considerations ............................................................ 45
Outline Dimensions ....................................................................... 46
Ordering Guide .......................................................................... 47
REVISION HISTORY 11/10—Rev. A to Rev. B Changes to Absolute Maximum Ratings Section ......................... 8 Changes to Figure 3 .......................................................................... 9 Add Figure 4; Renumbered Sequentially ....................................... 9 Changes to Theory of Operation Section and Analog Input Section .............................................................................................. 17 Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 35 Updated Outline Dimensions ....................................................... 46
3/05—Rev. 0 to Rev. A Added LFCSP ...................................................................... Universal Changes to Features .......................................................................... 1 Changes to Applications .................................................................. 1 Changes to General Description .................................................... 1 Changes to Product Highlights ....................................................... 1 Changes to Table 6 .......................................................................... 10
Changes to Terminology ............................................................... 11 Changes to Figure 22 ...................................................................... 15 Changes to Clock Input and Considerations Section ................ 18 Changes to Timing Section ........................................................... 19 Changes to Figure 33 ...................................................................... 19 Changes to Data Format Section .................................................. 20 Changes to Table 10 ....................................................................... 24 Changes to Figure 39 ...................................................................... 25 Changes to Table 13 ....................................................................... 36 Updated Outline Dimensions ....................................................... 46 Changes to Ordering Guide .......................................................... 47
1/05—Revision 0: Initial Version
AD9248
Rev. B | Page 3 of 48
SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1. Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI 14 14 14 Bits ACCURACY
No Missing Codes Guaranteed Full VI 14 14 14 Bits Offset Error 25°C I ±0.2 ±1.3 ±0.2 ±1.3 ±0.2 ±1.3 % FSR Gain Error1 Full IV ±0.25 ±2.2 ±0.3 ±2.4 ±0.5 ±2.5 % FSR Differential Nonlinearity (DNL)2 Full V ±0.65 ±0.65 ±0.7 LSB 25°C IV ±0.6 ±1.0 ±0.6 ±1.0 ±0.65 ±1.0 LSB Integral Nonlinearity (INL)2 Full V ±2.7 ±2.7 ±2.8 LSB
25°C IV ±2.3 ±4.5 ±2.3 ±4.5 ±2.4 ±4.5 LSB TEMPERATURE DRIFT
Offset Error Full V ±2 ±2 ±3 ppm/°C Gain Error1 Full V ±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV
INPUT REFERRED NOISE Input Span = 1 V 25°C V 2.1 2.1 2.1 LSB rms Input Span = 2.0 V 25°C V 1.05 1.05 1.05 LSB rms
ANALOG INPUT Input Span = 1.0 V Full IV 1 1 1 V p-p Input Span = 2.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 7 7 7 pF
REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES
Supply Voltages AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V
Supply Current IAVDD2 Full V 60 110 200 mA IDRVDD2 Full V 5 11 16 mA
PSRR Full V ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION
DC Input4 Full V 180 330 600 mW Sine Wave Input2 Full VI 190 217 360 400 640 700 mW Standby Power5 Full V 2.0 2.0 2.0 mW
AD9248
Rev. B | Page 4 of 48
Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit MATCHING CHARACTERISTICS
Offset Error (Nonshared Reference Mode)
25°C I ±0.19 ±1.56 ±0.19 ±1.56 ±0.25 ±1.74 % FSR
Offset Error (Shared Reference Mode)
25°C I ±0.19 ±1.56 ±0.19 ±1.56 ±0.25 ±1.74 % FSR
Gain Error (Nonshared Reference Mode)
25°C I ±0.07 ±1.43 ±0.07 ±1.43 ±0.07 ±1.47 % FSR
Gain Error (Shared Reference Mode)
25°C I ±0.01 ±0.06 ±0.01 ±0.06 ±0.01 ±0.10 % FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 294 Measured with dc input at maximum clock rate. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
AD9248
Rev. B | Page 5 of 48
AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V external reference, TMIN to TMAX, DCS Enabled, unless otherwise noted.
Table 2. Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz Full V 73.4 73.1 72.8 dB 25°C IV 73.1 73.7 72.8 73.4 72.3 73.1 dB
fINPUT = 9.7 MHz Full V 72.9 dB 25°C IV 72.4 73.1 dB fINPUT = 19.6 MHz Full V 72.7 dB 25°C IV 72.3 72.9 dB fINPUT = 35 MHz Full V 71.5 dB 25°C IV 71.2 71.6 dB fINPUT = 100 MHz 25°C V 70 69.5 69.0 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fINPUT = 2.4 MHz Full V 73.0 72.8 72.5 dB 25°C IV 72.2 73.2 72.0 73.0 71.7 72.7 dB fINPUT = 9.7 MHz Full V 72.0 dB 25°C IV 70.9 72.2 dB fINPUT = 19.6 MHz Full V 72.1 dB 25°C IV 71.0 72.3 dB fINPUT = 35 MHz Full V 70.9 dB 25°C IV 70.0 71.0 dB fINPUT = 100 MHz 25°C V 69.5 69.0 68.5 dB
EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 2.4 MHz Full V 11.8 11.8 11.8 Bits 25°C IV 11.7 11.8 11.7 11.8 11.6 11.8 Bits fINPUT = 9.7 MHz Full V 11.7 Bits 25°C IV 11.5 11.7 Bits fINPUT = 19.6 MHz Full V 11.7 Bits 25°C IV 11.5 11.7 Bits fINPUT = 35 MHz Full V 11.5 Bits 25°C IV 11.3 11.5 Bits fINPUT = 100 MHz 25°C V 11.3 11.2 11.2 Bits
WORST HARMONIC (SECOND or THIRD) fINPUT = 2.4 MHz Full V 86.0 85.0 84.0 dBc 25°C IV 77.5 87.5 77.5 86.0 77.5 86.0 dBc fINPUT = 9.7 MHz Full V 83.0 dBc 25°C I 76.1 84.0 dBc fINPUT = 19.6 MHz Full V 83.0 dBc 25°C I 76.0 84.0 dBc fINPUT = 35 MHz Full V 80.0 dBc 25°C I 73.0 80.5 dBc
AD9248
Rev. B | Page 6 of 48
Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER SPUR
(NONSECOND or THIRD)
fINPUT = 2.4 MHz Full V 88.0 88.0 85.5 dBc 25°C I 83.3 89.0 83.5 89.0 81.0 86.0 dBc fINPUT = 9.7 MHz Full V 87.0 dBc 25°C I 83.1 88.0 dBc fINPUT = 19.6 MHz Full V 88.0 dBc 25°C I 82.6 88.5 dBc fINPUT = 35 MHz Full V 85.5 dBc 25°C I 79.8 86.0 dBc fINPUT = 100 MHz 25°C V 79.0 81.0 75.0 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz Full V 86.0 85.0 84.0 dBc 25°C IV 77.5 87.5 77.5 86.0 77.5 86.0 dBc fINPUT = 9.7 MHz Full V 83.0 dBc 25°C I 76.1 84.0 dBc fINPUT = 19.6 MHz Full V 83.0 dBc 25°C I 76.0 84.0 dBc fINPUT = 35 MHz Full V 80.0 dBc 25°C I 73.0 80.5 dBc
CROSSTALK Full V −85.0 −85.0 −85.0 dB
DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3. Test AD9248BST/BCP-20 AD9248BST-40 AD9248BST-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS
High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA Input Capacitance Full IV 2 2 2 pF
LOGIC OUTPUTS1 High Level Output Voltage Full IV DRVDD −
0.05 DRVDD −
0.05 DRVDD −
0.05 V
Low Level Output Voltage Full IV 0.05 0.05 0.05 V
1 Output voltage levels measured with capacitive load only on each output.
AD9248
Rev. B | Page 7 of 48
SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4. Test AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 20 40 65 MSPS Minimum Conversion Rate Full V 1 1 1 MSPS CLK Period Full V 50.0 25.0 15.4 ns CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns
DATA OUTPUT PARAMETER Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns Pipeline Delay (Latency) Full V 7 7 7 Cycles Aperture Delay (tA) Full V 1.0 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms Wake-Up Time3 Full V 2.5 2.5 2.5 ms
OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles
1 The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24). 2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N–1
N N+1N+2
N+3
N+4N+5 N+6
N+7
N+8
ANALOGINPUT
CLOCK
DATAOUT
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
MIN 2.0ns,MAX 6.0ns
tPD =
0444
6-00
2
Figure 2. Timing Diagram
AD9248
Rev. B | Page 8 of 48
ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Table 5. Parameter Rating ELECTRICAL
AVDD to AGND −0.3 V to +3.9 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +3.9 V Digital Outputs to DRGND −0.3 V to DRVDD + 0.3 V OEB, DFS, CLK, DCS, MUX_SELECT,
SHARED_REF to AGND −0.3 V to AVDD + 0.3 V
VINA, VINB to AGND −0.3 V to AVDD + 0.3 V VREF to AGND −0.3 V to AVDD + 0.3 V SENSE to AGND −0.3 V to AVDD + 0.3 V REFB, REFT to AGND −0.3 V to AVDD + 0.3 V PDWN to AGND −0.3 V to AVDD + 0.3 V
ENVIRONMENTAL1 Operating Temperature −40°C to +85°C Junction Temperature 150°C Lead Temperature (10 sec) 300°C Storage Temperature −65°C to +150°C
1 Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA = 26.4°C/W with heat slug soldered to ground plane. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS I 100% production tested. II 100% production tested at 25°C and sample tested at
specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization
testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
ESD CAUTION
AD9248
Rev. B | Page 9 of 48
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64
AVD
D
63
CLK
_A
62
SHA
RED
_REF
61
MU
X_SE
LEC
T
60
PDW
N_A
59
OEB
_A
58
OTR
_A
57
D13
_A (M
SB)
56
D12
_A
55
D11
_A
54
D10
_A
53
DR
GN
D
52
DR
VDD
51
D9_
A
50
D8_
A
49
D7_
A
47 D5_A46 D4_A45 D3_A
42 D0_A (LSB)
43 D1_A
44 D2_A
48 D6_A
41 DRVDD40 DRGND39 OTR_B
37 D12_B36 D11_B35 D10_B34 D9_B33 D8_B
38 D13_B (MSB)
2VIN+_A3VIN–_A4AGND
7REFB_A
6REFT_A
5AVDD
1AGND
8VREF9SENSE10REFB_B
12AVDD13AGND14VIN–_B15VIN+_B16AGND
11REFT_B
PIN 1
17
AVD
D
18
CLK
_B
19
DC
S
20
DFS
21
PDW
N_B
22
OEB
_B
23
D0_
B (L
SB)
24
D1_
B
25
D2_
B
26
D3_
B
27
D4_
B
28
DR
GN
D
29
DR
VDD
30D
5_B
31D
6_B
32
D7_
B
AD9248TOP VIEW
(Not to Scale)
64-LEAD LQFP
0444
6-00
3
Figure 3. 64-Lead LQFP Pin Configuration
64-LEAD LFCSPTOP VIEW
(Not to Scale)
D6_AD5_AD4_AD3_AD2_AD1_AD0_A (LSB)
DRGNDOTR_BD13_B (MSB)D12_BD11_BD10_BD9_BD8_B
AD9248
AGND
AVDDREFT_AREFB_A
VREFSENSE
REFB_B
AGNDVIN–_BVIN+_B
VIN+_AVIN–_A
AVDDREFT_B
CLK
_ASH
AR
ED_R
EFM
UX_
SELE
CT
OEB
_A
D13
_A (M
SB)
D12
_AD
11_A
D10
_AD
RG
ND
D9_
AD
8_A
D7_
A
CLK
_BD
CS
DFS
PDW
N_B
OEB
_B
D1_
BD
2_B
D3_
BD
4_B
DR
GN
D
D5_
BD
6_B
D7_
B
D0_
B (L
SB)
AGND
AGND
AVD
D
DR
VDD
DRVDD
AVD
D
PDW
N_A
OTR
_A
DR
VDD
PIN 1INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
123456789
10111213141516
NOTES1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND.
48474645444342414039383736353433
0444
6-10
3
Figure 4. 64-Lead LFCSP Pin Configuration
AD9248
Rev. B | Page 10 of 48
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode. 20 DFS Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B.
Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z). 22 OEB_B Output Enable Pin for Channel B.
Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23 to 27, 30 to 38
D0_B (LSB) to D13_B (MSB)
Channel B Data Output Bits.
28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor. 39 OTR_B Out-of-Range Indicator for Channel B. 42 to 51, 54 to 57
D0_A (LSB) to D13_A (MSB)
Channel A Data Output Bits.
58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Pin for Channel A.
Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. 60 PDWN_A Power-Down Function Selection for Channel A.
Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z). 61 MUX_SELECT Data Multiplexed Mode.
(See Data Format section for how to enable; high setting disables output data multiplexed mode.) 62 SHARED_REF Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A. EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
AD9248
Rev. B | Page 11 of 48
TERMINOLOGY Aperture Delay SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion.
Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on the input to the ADC.
Integral Nonlinearity (INL) Deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.
Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point.
Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX.
Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.
Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (SINAD) Ratio The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed dB.
Effective Number of Bits (ENOB) Using the following formula
ENOB = (SINAD − 1.76)/6.02
ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR) The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in dB.
Spurious-Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Nyquist Sampling When the frequency components of the analog input are below the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling.
IF Sampling Due to the effects of aliasing, an ADC is not limited to Nyquist sampling. Higher sampled frequencies are aliased down into the first Nyquist zone (DC − fCLOCK/2) on the output of the ADC. The bandwidth of the sampled signal should not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Crosstalk Coupling onto one channel being driven by a (−0.5 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components.
AD9248
Rev. B | Page 12 of 48
TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.
–12010
MA
GN
ITU
DE
(dB
FS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
0444
6-06
0
SNR = 72.6dBSINAD = 71.9dBH2 = –81.5dBcH3 = –86.8dBcSFDR = 81.5dB
CROSSTALKSECOND
HARMONIC
THIRDHARMONIC
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz While Channel B Is Digitizing fIN = 10 MHz
–12010
MA
GN
ITU
DE
(dB
FS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
0444
6-06
1
SNR = 70.5dBSINAD = 69.4dBH2 = –92.3dBcH3 = –80.1dBcSFDR = 80.1dBc
SECONDHARMONIC
THIRD HARMONIC
CROSSTALK
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz While Channel B Is Digitizing fIN = 76 MHz
–12010
MA
GN
ITU
DE
(dB
FS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
0444
6-06
2
SNR = 68.1dBSINAD = 68.0dBH2 = –83.4dBcH3 = –83.1dBcSFDR = 75.1dBc
SECOND HARMONICCROSSTALK
Figure 7. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz While Channel B Is Digitizing fIN = 126 MHz
ADC SAMPLE RATE (MSPS)
90
55
40
SFD
R/S
NR
(dB
c)
85
80
75
70
65
60
45 50 55 60 65
95
100
50 0444
6-00
7
SNR
SFDR
Figure 8. AD9248-65 Single-Tone SFDR/SNR vs. FS with fIN = 32.5 MHz
SNRSFDR
SNR
ADC SAMPLE RATE (MSPS)
90
55
40
SFD
R/S
NR
(dB
c)
85
80
75
70
65
60
95
100
5035302520
0444
6-00
8
Figure 9. AD9248-40 Single-Tone SFDR/SNR vs. FS with fIN = 20 MHz
SFDR
SNR
ADC SAMPLE RATE (MSPS)
90
55
SFD
R/S
NR
(dB
c)
85
80
75
70
65
60
95
100
500 5 10 15 20
0444
6-00
9
Figure 10. AD9248-20 Single-Tone SFDR/SNR vs. FS with fIN = 10 MHz
AD9248
Rev. B | Page 13 of 48
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
90
SFD
R/S
NR
(dB
c)
80
70
60
100
50
–3540
–30 –25 –20 –15 –10 –5 0
0444
6-01
0
Figure 11. AD9248-65 Single-Tone SFDR/SNR vs. AIN with fIN = 32.5 MHz
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
90
SFD
R/S
NR
(dB
c)
80
70
60
100
50
–3540
–30 –25 –20 –15 –10 –5 0
0444
6-01
1
Figure 12. AD9248-40 Single-Tone SFDR/SNR vs. AIN with fIN = 20 MHz
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
90
SFD
R/S
NR
(dB
c) 80
70
60
100
50
–3540
–30 –25 –20 –15 –10 –5 0
0444
6-01
2
Figure 13. AD9248-20 Single-Tone SFDR/SNR vs. AIN with fIN = 10 MHz
SNRSFDR
SNR
INPUT FREQUENCY (MHz)
90
SFD
R/S
NR
(dB
c)
85
80
75
95
70
065
20 40 60 80 100 120 140
0444
6-01
3
Figure 14. AD9248-65 Single-Tone SFDR/SNR vs. fIN
SNRSFDR
SNR
90
85
80
75
95
70
065
20 40 60 80 100 120 140
INPUT FREQUENCY (MHz)
SFD
R/S
NR
(dB
c)
0444
6-01
4
Figure 15. AD9248-40 Single-Tone SFDR/SNR vs. fIN
SNRSFDR
SNR
90
85
80
75
95
70
065
20 40 60 80 100 120 140INPUT FREQUENCY (MHz)
SFD
R/S
NR
(dB
c)
0444
6-01
5
Figure 16. AD9248-20 Single-Tone SFDR/SNR vs. fIN
AD9248
Rev. B | Page 14 of 48
–12010
MA
GN
ITU
DE
(dB
FS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
IMD = –85dBc
0444
6-06
3
Figure 17. Dual-Tone FFT with fIN1 = 39 MHz and fIN2 = 40 MHz
–12010
MA
GN
ITU
DE
(dB
FS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
IMD =–83dBc
0444
6-06
4
Figure 18. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz
–12010 15 20 25 3050
–100
–80
–60
–40
–20
0
MA
GN
ITU
DE
(dB
FS)
FREQUENCY (MHz)
0444
6-01
8
Figure 19. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
95
SFD
R/S
NR
(dB
FS)
90
85
80
100
75
–24
70
–21 –18 –15 –12 –9 –6
65
60 0444
6-01
9
Figure 20. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
95
SFD
R/S
NR
(dB
FS)
90
85
80
100
75
–24
70
–21 –18 –15 –12 –9 –6
65
60 0444
6-02
0
Figure 21. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz
SNRSFDR
SNR
INPUT AMPLITUDE (dBFS)
95
SFD
R/S
NR
(dB
FS)
90
85
80
100
75
–24
70
–21 –18 –15 –12 –9 –6
65
60 0444
6-02
1
Figure 22. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 200 MHz and fIN2 = 201 MHz
AD9248
Rev. B | Page 15 of 48
CLOCK FREQUENCY (MHz)
SIN
AD
(dB
c)
72
70
74
068
20 40 60
SINAD –65SINAD –40
SINAD –20
12.0
11.5
11.0 0444
6-02
2EN
OB
Figure 23. SINAD vs. FS with Nyquist Input
DUTY CYCLE (%)
85
SIN
AD
/SFD
R (d
Bc) 80
75
70
95
65
30
60
40 45 50 55 60 65
55
50
DCS ON (SFDR)
DCS OFF (SINAD)
DCS OFF (SFDR)
90
35
DCS ON (SINAD)
0444
6-02
3
Figure 24. SINAD/SFDR vs. Clock Duty Cycle
TEMPERATURE (°C)
80
SIN
AD
/SFD
R (d
B) 78
76
74
84
72
–50
70
0 50 100
68
66
SINAD
SFDR82
0444
6-02
4
Figure 25. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
SAMPLE RATE (MSPS)
500
AVD
D P
OW
ER (m
W)
400
300
200
600
1000 10 20 30 40 50 60
–65
–40
–20
0444
6-02
5
Figure 26. Analog Power Consumption vs. FS
CODE
INL
(LSB
)
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
800060002000 40000 10000 12000 14000 16000
0444
6-02
6
Figure 27. AD9248-65 Typical INL
CODE
DN
L (L
SB)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
800060002000 40000 10000 12000 14000 16000
0444
6-02
7
Figure 28. AD9248-65 Typical DNL
AD9248
Rev. B | Page 16 of 48
EQUIVALENT CIRCUITS AVDD
VIN+_A, VIN–_A,VIN+_B, VIN–_B
0444
6-02
8
Figure 29. Equivalent Analog Input Circuit
DRVDD
0444
6-02
9
Figure 30. Equivalent Digital Output Circuit
AVDD
CLK_A, CLK_BDCS, DFS,
MUX_SELECT,SHARED_REF
0444
6-03
0
Figure 31. Equivalent Digital Input Circuit
AD9248
Rev. B | Page 17 of 48
THEORY OF OPERATION The AD9248 consists of two high performance ADCs that are based on the AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietary front end SHA followed by a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage, followed by eight 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 14-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock.
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched-capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing.
ANALOG INPUT The analog input to the AD9248 is a differential, switched-capacitor SHA that has been designed for optimum perfor-mance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit. In Figure 32, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application.
In IF under-sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.
5pF
5pFT
T
VIN+
VIN–CPAR
T
T
H
H
CPAR
0444
6-03
1
Figure 32. Switched-Capacitor Input
An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as:
REFT = ½(AVDD + VREF)
REFB = ½(AVDD −VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
The equations above show that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9248 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as:
VCMMIN = VREF/2
VCMMAX = (AVDD + VREF)/2
AD9248
Rev. B | Page 18 of 48
The minimum common-mode input level allows the AD9248 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN−. The AD9248 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9248-40 and AD9248-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while driving the AD9248 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9248. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 33.
AD9248
VINA
VINB
AVDD
AGND
2V p-p
50Ω
50Ω
10pF
10pF49.9Ω
1kΩ
1kΩ0.1μF
0444
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2
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance.
CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.
The AD9248 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9248’s separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without significant performance degradation.
The AD9248-65 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. When proper track-and-hold times for the converter are required to maintain high performance, maintaining a 50% duty cycle clock is particularly important in high speed applications. It may be difficult to maintain a tightly controlled duty cycle on the input clock on the PCB (see Figure 24). DCS can be enabled by tying the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 μs to 3 μs to allow the DLL to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated as
( )⎥⎦⎤
⎢⎣
⎡×××
×=jINPUT tfπ
SNR2
1log20
In the equation, the rms aperture jitter, tJ , represents the root-sum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9248, it is important to minimize input clock jitter. The clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9248 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
AD9248
Rev. B | Page 19 of 48
A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles.
POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9248 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by
DIGITAL OUTPUTS IDRVDD = VDRVDD × CLOAD × fCLOCK × N The AD9248 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency.
Either channel of the AD9248 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins. The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information. It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 1 mW for the ADC. Note that if DCS is enabled, it is mandatory to disable the clock of an independently powered-down channel. Otherwise, significant distortion results on the active channel. If the clock inputs remain active while in total standby mode, typical power dissipation of 12 mW results.
TIMING The AD9248 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propa-gation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9248 using the DCS pin. This provides a stable 50% duty cycle to internal circuits. The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 μF and 10 μF decoupling capacitors on REFT and REFB.
The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9248. These transients can detract from the converter’s dynamic performance. The lowest typical conversion rate of the AD9248 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade.
B–8 A–7 B–7 A–6 B–6 A–5 B–5 A–4 B–4 A–3 B–3 A–2 B–2 A–1 B–1 A0 B0 A1
A–1A0 A1 A2
A3A4 A5
A6
A7
A8
B–1B0 B1 B2
B3B4 B5
B6
B7
B8
ANALOG INPUTADC A
ANALOG INPUTADC B
CLK_A = CLK_B =MUX_SELECT
D0_A TOD11_A
tPD tPD
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Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
AD9248
Rev. B | Page 20 of 48
DATA FORMAT The AD9248 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a single 14-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, that is, the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports.
If the ADCs run with synchronized timing, this same clock can be applied to the MUX_SELECT pin. Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade AC performance. It is recommended to keep the clock skew <100 pS. After the MUX_SELECT rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channel’s data is placed on the bus. Typically, the other unused bus would be disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 34 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. Note that both channels must remain active in this mode and that each channel’s power-down pin must remain low.
VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9248. The input range can be adjusted by varying the reference voltage applied to the AD9248, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage).
The shared reference mode allows the user to connect the references from the dual ADCs together externally for superior
gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. To enable shared reference mode, the SHARED_REF pin must be tied high and the external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B, and REFB_A must be shorted to REFB_B.)
Internal Reference Connection
A comparator within the AD9248 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 35), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected, as shown in Figure 36, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+
VIN–
10μF
10μF0.1μF
0.1μF
REFT
ADCCORE
SELECTLOGIC
SENSE0.1μF 0.5V
AD9248
REFB
0.1μFVREF
0444
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Figure 35. Internal Reference Configuration
Table 7. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure 36) Internal Fixed Reference AGND to 0.2 V 1.0 2.0
AD9248
Rev. B | Page 21 of 48
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 37 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9248 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading.
VIN+
VIN–
VREF
REFT
SENSE
0.5V
AD9248
REFB
R1
R210μF
10μF
0.1μF
0.1μF10μF
ADCCORE
SELECTLOGIC
0.1μF
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Figure 36. Programmable Reference Configuration
TEMPERATURE (°C)
0.2
VREF
ER
RO
R (%
)
1.2
1.0
0.8
0.6
0.4
0–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
VREF = 1V
VREF = 0.5V
0444
6-03
6
Figure 37. Typical VREF Drift
LOAD (mA)
–0.20
ERR
OR
(%)
0.05
0
–0.05
–0.10
–0.15
–0.250 0.5 1.0 1.5 2.0 2.5 3.0
0.5V ERROR
1V ERROR
0444
6-03
7
Figure 38. VREF Accuracy vs. Load
AD9248
Rev. B | Page 22 of 48
AD9248 LQFP EVALUATION BOARD The evaluation board supports both the AD9238 and AD9248 and has five main sections: clock circuitry, inputs, reference circuitry, digital control logic, and outputs. A description of each section follows. Table 8 shows the jumper settings and notes assumptions in the comment column.
Four supply connections to TB1 are necessary for the evaluation board: the analog supply of the DUT, the on-board analog circuitry supply, the digital driver DUT supply, and the on-board digital circuitry supply. Separate analog and digital supplies are recommended, and on each supply 3 V is nominal. Each supply is decoupled on-board, and each IC, including the DUT, is decoupled locally. All grounds should be tied together.
CLOCK CIRCUITRY The clock circuitry is designed for a low jitter sine wave source to be ac-coupled and level shifted before driving the 74VHC04 hex inverter chips (U8 and U9) whose output provides the clock to the part. The POT (R32 and R31) on the level shifting circuitry allows the user to vary the duty cycle if desired. The amplitude of the sine wave must be large enough for the trip points of the hex inverter and within the supplies to avoid noise from clipping. To ensure a 50% duty cycle internal to the part, the AD9248-65 has an on-chip duty cycle stabilizer circuit that is enabled by putting in Jumper JP11. The duty cycle stabilizer circuitry should only be used at clock rates above 40 MSPS.
Each channel has its own clock circuitry, but normally both clock pins are driven by a single 74VHC04, and the solder Jumper JP24 is used to tie the clock pins together. When the clock pins are tied together and only one 74VHC04 is being used, the series termination resistor for the other channel must be removed (either R54 or R55, depending on which inverter is being used).
A data capture clock for each channel is created and sent to the output buffers in order to be used in the data capture system if needed. Jumper JP25 and Jumper JP26 are used to invert the data clock, if necessary, and can be used to debug data capture timing problems.
ANALOG INPUTS The AD9248 achieves the best performance with a differential input. The evaluation board has two input options for each channel, a transformer (XFMR) and an AD8138, both of which perform single-ended-to-differential conversions. The XFMR allows for the best high frequency performance, and the AD8138 is ideal for dc evaluation, low frequency inputs, and driving an ADC differentially without loading the single-ended signal.
The common-mode level for both input options is set to midsupply by a resistor divider off the AVDD supply but can also be overdriven with an external supply using the (test points) TP12, TP13 for the AD8138s, and TP14, TP15 for the XFMRs. For low distortion of full-scale input signals when using an AD8138, put Jumper JP17 and Jumper JP22 in Position B and put an external negative supply on the TP10 and TP11 testpoints.
For best performance, use low jitter input sources and a high performance band-pass filter after the signal source, before the evaluation board (see Figure 39). For XFMR inputs, use solder Jumper JP13 and Jumper JP14 for Channel A, and Jumper JP20 and Jumper JP21 for Channel B. For AD8138 inputs, use solder Jumper JP15 and Jumper JP16 for Channel A, and Jumper JP18 and Jumper JP19 for Channel B. Remove all solder from the jumpers not being used.
REFERENCE CIRCUITRY The evaluation board circuitry allows the user to select a reference mode through a series of jumpers and provides an external reference if necessary. Please refer to Table 9 to find the jumper settings for each reference mode. The external reference on the board is a simple resistor divider/zener diode circuit buffered by an AD822 (U4). The POT (R4) can be used to change the level of the external reference to fine adjust the ADC full scale.
DIGITAL CONTROL LOGIC The digital control logic on the evaluation board is a series of jumpers and pull-down resistors used as digital inputs for the following pins on the AD9248: the power-down and output enable bar for each channel, the duty cycle restore circuitry, the twos complement output mode, the shared reference mode, and the MUX_SELECT pin. Refer to Table 8 for normal operating jumper positions.
OUTPUTS The outputs of the AD9248 (and the data clock discussed earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to ensure the correct load on the outputs of the DUT, as well as the extra drive capability to the next part of the system. The 74VHC541s are latches, but on this evaluation board, they are wired and function as buffers. Jumper JP30 can be used to tie the data clocks together if desired. If the data clocks are tied, the R39 or R40 resistor must be removed, depending on which clock circuitry is being used.
AD9248
Rev. B | Page 23 of 48
Table 8. PCB Jumpers
JP Description Normal Setting Comment
1 Reference Out 1 V Reference Mode 2 Reference In 1 V Reference Mode 3 Reference Out 1 V Reference Mode 4 Reference Out 1 V Reference Mode 5 Reference Out 1 V Reference Mode 6 Shared Reference Out 7 Shared Reference Out 8 PDWN B Out 9 PDWN A Out 10 Shared Reference Out 11 Duty Cycle In Duty Cycle Restore On 12 Twos Complement Out 13 Input In Using XFMR Input 14 Input In Using XFMR Input
15 Input Out Using XFMR Input 16 Input Out Using XFMR Input 17 AD8138 Supply A Using XFMR Input 18 Input Out Using XFMR Input 19 Input Out 20 Input In 21 Input In 22 AD8138 Supply A 23 Mux Select Out 24 Tie Clocks In Using One Signal for Clock 25 Data Clock A 26 Data Clock Out Using One Signal for Clock 27 Mux Select In 28 OEB_A Out 29 Mux Select Out 30 Data Clock Out 35 OEB_B Out
Table 9. Reference Jumpers Reference Mode JP1 JP2 JP3 JP4 JP5 1 V Internal Out In Out Out Out 0.5 V Internal Out Out In Out Out External In Out Out Out In
AD9248EVALUATION BOARD
SINE SOURCELOW JITTER
(HP8644)
SINE SOURCELOW JITTER
(HP8644)
BAND-PASSFILTERS
OUTPUTBUFFERS
INPUTCIRCUITRY
CLOCKCIRCUITRY
AD9248
0444
6-03
8
REFERENCE MODESELECTION/EXTERNALREFERENCE/CONTROL
LOGIC
Figure 39. PCB Test Setup
AD9248
Rev. B | Page 24 of 48
LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 10. No. Quantity Reference Designator Device Package Value 1 18 C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90 Capacitors ACASE 10 μF 2 23 C3 to C10, C29 to C31, C56, C61 to C65, C77, C79, C80, C84 to C86 Capacitors 0805 0.1 μF 3 7 C13, C15, C18, C19, C21, C23, C25 Capacitors 0603 0.001 μF 4 15 C6, C14, C16, C17, C20, C22, C24, C26, C32, C35 to C40 Capacitors 0603 0.1 μF 5 4 C41 to C44 Capacitors DCASE 22 μF 6 4 C45 to C48 Capacitors 1206 0.1 μF 7 2 C49, C53 Capacitors ACASE 6.3 V 8 2 C52, C57 Capacitors 0201 0.01 μF 9 4 C54, C55, C68, C69 Capacitors 0805 10 4 C58, C59 ,C70, C71 Capacitors 0603 DNP 11 2 C60, C72 Capacitors 0603 20 pF 12 1 D1 AD1580 SOT-23CAN 1.2 V 13 1 J1 SAM080UPM 14 14 JP1 to JP5, JP8 to JP12, JP23, JP28, JP29, JP35 JPRBLK02 15 13 JP6, JP7, JP13, JP14 to JP16, JP18 to JP21, JP24, JP27, JP30 JPRSLD02 16 4 JP17, JP22, JP25, JP26 JPRBLK03 17 4 L1 to L4 IND1210 LC1210 10 μH 18 6 R1, R2, R13, R14, R23, R27 Resistors 1206 33 Ω 19 1 R3 Resistor 1206 5.49 kΩ 20 1 R4 Resistor RV3299UP 10 kΩ 21 7 R5, R6, R38, R41, R43, R44, R51 Resistors 0805 5 kΩ 22 6 R7, R8, R19, R20, R52, R53 Resistors 1206 49.9 Ω 23 8 R9, R18, R29, R30, R47 to R50 Resistors 0805 1 kΩ 24 6 R10, R12, R15, R24, R25, R28 Resistors 1206 499 Ω 25 2 R11, R26 Resistors 1206 523 Ω 26 4 R16, R17, R21, R22 Resistors 1206 40 Ω 27 2 R31, R32 Resistors RV3299W 10 kΩ 28 4 R33 to R35, R42 Resistors 0805 500 Ω 29 2 R36, R37 Resistors 1206 10 kΩ 30 2 R39, R40 Resistors 0805 22 Ω 31 2 R54, R55 Resistors 1206 0 Ω 32 16 RP1 to RP16 Resistor Pack RCA74204 22 Ω 33 6 S1 to S6 SMA200UP 34 2 T1, T2 DIP06RCUP T1-1T 35 1 TB1 TBLK06REM 36 4 TP1, TP3, TP5, TP7 LOOPTP RED 37 4 TP2, TP4, TP6, TP8 LOOPTP BLK 38 7 TP9, TP12 to TP17 LOOPMINI WHT 39 2 TP10, TP11 LOOPMINI RED 40 1 U1 64LQFP7X7 AD9248 41 4 U2, U3, U7, U10 SOL20 74VHC541 42 1 U4 SOIC-8 AD822 43 2 U5, U6 SO8NC7 AD8138 44 2 U8, U9 TSSOP-14 74VHC04
AD9248
Rev. B | Page 25 of 48
LQFP EVALUATION BOARD SCHEMATICS
B
TP8 B
LK
TP2 B
LK
AVD
DIN
AVD
DR
EDTP
110
μHL2
DU
TAVD
DIN
TB1
DU
TAVD
D
TP3 R
ED10
μHL1
BLK
TP4
RED
TP5
10μH
L4
DVD
DIN
AG
ND
TB1
AG
ND
DR
VDD
IN
TB1
TB1
TB1
DVD
D
DU
TDR
VDD
TP7 R
ED
BLK
TP6
10μH
L3
R2
33Ω
AG
ND
;7A
VDD
;14
U8
12
U8
AG
ND
;7A
VDD
;14
10
U8
8
JP26
3
2
WH
TTP
1674
VHC
04
74VH
C04
74VH
C04
B
1311 9
JP25 2
13
R1
33ΩJP
24
R54 0Ω
TP17
WH
T
CLK
AO
U9
AG
ND
;7A
VDD
;14
12
AG
ND
;7A
VDD
;14
U9
10
74VH
C04
74VH
C04
U9
AG
ND
;7A
VDD
;14
974
VHC
04
U9
AG
ND
;7A
VDD
;14
3
AG
ND
;7A
VDD
;14
U9
6
AG
ND
;7A
VDD
;14
U9
21
74VH
C04
74VH
C04
74VH
C04
R53
49.9Ω
S6R
3210
kΩ
R42
500Ω
C84
0.1μ
F
CLK
AC
W CW
R31
10kΩ
AVD
D
R34
500Ω
R35
500Ω
C77
0.1μ
F
R52
49.9Ω
C73
10μF
6.3V
S5
C79
0.1μ
F
CLK
B
AVD
D
C74
10μF
6.3V
C80
0.1μ
F
U8
AG
ND
;7A
VDD
;14
5
AG
ND
;7A
VDD
;14
U8
43
U8
AG
ND
;7A
VDD
;14
74VH
C04
74VH
C04
74VH
C04
AG
ND
;7A
VDD
;14
1
DA
TAC
LKB
13 11
AVD
D
R33
500Ω
DU
TCLK
A
5
DA
TAC
LKA
DU
TCLK
B
C42
22μF 25V
C46
0.1μ
F
C41
22μF 25V
C45
0.1μ
F
C44
22μF 25V
C48
0.1μ
F
C43
22μF
F25V
C47
0.1μ
F
R55 0Ω
8
4
A A1
2
1 2 3TB
1
5 4 6
6
0444
6-03
9
Figure 40. Evaluation Board Schematic
AD9248
Rev. B | Page 26 of 48
R20
49.9Ω
R8
49.9Ω
R19
49.9Ω
R7
49.9Ω
C59
DN
P
C58
DN
P
C71
DN
P
C70
DN
P 0.1μ
FC
65C64
0.1μ
FR
181k
ΩR
501k
Ω
R29
1kΩ
R9
1kΩ
R30
1kΩ
R47
1kΩ
C85
0.1μ
F C63
0.1μ
F
C68
VAL C
69VA
L
VAL
C55
VAL
C54
C56
0.1μ
F
C62
0.1μ
F
C61
0.1μ
F
C53
1 0V
6.3V C
49 10V
6.3V
R21
40Ω
R22
40Ω
R23
33Ω
JP18
JP19
R24
499Ω
R25
499Ω
JP22
2
S4
JP20
JP21
T1
T1–1
T6 4
1 2 3
JP14
JP13
S2
R14
33Ω
VIN
+_A
VIN
–_A
VIN
+_B
VIN
–_B
JP17
2
31
499Ω
R12
JP16
JP15
R13
33Ω
R17
40Ω
R27
33Ω
T1–1
T
T2321
46
S3
TP11
RED
R16
40Ω
C87
10μF
6.3V
TP12
WH
T
TP13
WH
T
TP14
WH
T
TP15
WH
T
U6 18
6 3
245
U5
5 42
36
8 1
C88
10μF
6.3V
C50
10μF
6.3V
C51
10μF
6.3V
R49
1kΩ
R48
1kΩ
R15
499Ω
C86
0.1μ
F
R10
499Ω
S1
R11
523Ω R
2652
3ΩR28
499Ω
C60
20pF C
7220
PF
NC
= 5
NC
= 5
AD
8138
AD
8138
XFM
R IN
PUT
B
XFM
R IN
PUT
A
SP
SP
SHEE
T 3
SHEE
T 3
A
–IN
+IN
VEE
VCCVO
CVO
+
VO–
AVD
D
AVD
D
AVD
DA
VDD
AVD
D
AM
P IN
PUT
A
AM
P IN
PUT
B
–IN
+IN
VEE
VCCVO
CVO
+
VO–
B BA
TP10
RED
C89
10μF
6.3V
C90
10μF
6.3V
13
OO
OO
0444
6-04
0
AVD
D
Figure 41. Evaluation Board Schematic (Continued)
AD9248
Rev. B | Page 27 of 48
DU
TAVD
D
AVD
D
AVD
D
R36
10kΩ
JP6
R41
5kΩ
R51
5kΩ
AVD
DC1
10μF
6.3V
AVD
D
R44
5kΩ
C34
10μF
6.3V
VIN
+_B
VIN
–_B
VIN
–_A
OTR
AD
A13
DA
12D
A11
DA
10
DA
9D
A8
DA
7D
A6
DA
5D
A4
DA
3D
A2
DA
1
OTR
BD
B13
DB
12D
B11
DB
10D
B9
DB
7D
B6
DB
5
DB
4D
B3
DB
2D
B1
D1
21
DU
TAVD
D
DU
TDR
VDD
R4
10kΩ
DB
0
DB
8
DA
0
AG
ND
;4A
VDD
;8
U4
2
13
AG
ND
;4A
VDD
;8
U4
OU
T
57
6
VIN
+_A
C35
0.1μ
FC
370.
1μF
C38
0.1μ
FC
360.
1μF
R3
5.49
kΩ
R5
5kΩ
C30
0.1μ
F
C29
0.1μ
F
0.1μ
F
R43
5kΩ
R6
5kΩ
R38
5kΩ
U1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
3231302928272625
48
241
333435363738394041424344454647
232221201918171615141312111098765432
C12
10μF
6.3V
TP9
WH
T
JP7
AVD
D
CLK
AO
DU
TCLK
B
DU
TCLK
A
R37
10kΩ
C52
0.01
μF
1.2V
AD
822
AD
822
AD
9248
VIN
+_A
VIN
–_A
AVS
S2A
VDD
2R
EFT_
AR
EFB
_AVR
EFSE
NSE
REF
B_B
REF
T_B
AVD
D3
AVS
S3VI
N–_
BVI
N+_
BA
VSS4
AVD
D4
CLK
_BD
UTY
END
FSPD
WN
_B
D0_
B (L
SB)
D5_
AD
4_A
D3_
AD
2_A
D1_
AD
0_A
(LSB
)D
RVD
D2
DR
VSS2
OTR
_B(M
SB) D
13_B
D12
_BD
11_B
D10
_BD
9_B
D8_
B
AVS
S1
D1_
B
D6_
A
D2_
BD
3_B
D4_
BD
RVS
S1D
RVD
D1
D5_
BD
6_B
D7_
B
D7_
AD
8_A
D9_
AD
RVD
D3
DR
VSS3
D10
_AD
11_A
D12
_A(M
SB) D
13_A
OTR
_A
PDW
N_A
MU
X_SE
LEC
TSH
AR
ED_R
EFC
LK_A
AVD
D1
OEB
_A
OEB
_BC
31
JP11
JP12
JP2
JP3
JP4
JP1
C57
0.01
μFJP
5
C32
0.1μ
F
C39
0.1μ
FC
400.
1μF
C33
10μF
6.3V
CW
JP35
JP8
C24
0.1μ
FC
250.
001μ
FC
260.
1μF
C13
0.00
1μF
C14
0.1μ
F
C11
10μF
6.3V
C23
0.00
1μF
JP23
JP27
JP29
JP28
JP10
C22
0.1μ
FC
150.
001μ
FC
170.
1μF
C18
0.00
1μF
C19
0.00
1μF
C20
0.1μ
FC
210.
001μ
FC
160.
1μF
JP9C2
10μF
6.3V
AVD
D
+IN
–IN
OU
T+I
N
–IN
0444
6-04
1
Figure 42. Evaluation Board Schematic (Continued)
AD9248
Rev. B | Page 28 of 48
4
2
2RP11
DVDD
U10
182
11121314151617
201019
1
9876543
U7
3456789
119 10
20
17161514131211
2
DA13DA12DA11DA10DA9DA8
DA7DA6DA5DA4DA3DA2DA1
RP104RP10 63
RP4 63RP42
RP34RP3 63RP32RP3 81RP24RP2 63RP22RP2 81RP14RP1 63RP12
C30.1μF
C100.1μF
C90.1μF
C80.1μF
RP4 81
RP44
OTRA
DA0
RP102RP10 81RP94RP9 6
5
7
5
3RP92
RP9 8
7
5
7
5
7
1
RP124RP12 63RP12RP12 81RP11RP11 63RP11
C2810μF6.3V
81
C7510μF6.3V
JP30
R3922Ω
R4022ΩDATACLKA
DATACLKB
RP1 22Ω 81
A2A3A4A5A6A7A8
G1G2 GND
VCC
Y2Y3Y4Y5Y6Y7Y8
A1 Y174VHC541
A2A3A4A5A6A7A8
G1G2 GND
VCC
Y2Y3Y4Y5Y6Y7Y8
A1 Y174VHC541
22Ω22Ω
22Ω22Ω
22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω
SAM080UPM
22Ω
22Ω
22Ω22Ω22Ω22Ω22Ω
22Ω
22Ω22Ω22Ω22Ω22Ω22Ω22Ω
A8 Y8
22Ω
SAM080UPM
18
2
23
143
4
4
4
2
2
22Ω2
4
2
4
2
4
2
1
191
9 11
DVDD
C70.1μF
C60.1μF
C50.1μF
C40.1μF
C2710μF6.3V
C7610μF6.3V
182
11121314151617
1020
9876543
U3
345678
119 10
20
171615141312
2
DA13DA12DA11DA10DA9DA8
DA6DA5DA4DA3DA2DA1DA0
RP14RP14 63
RP8 63
54
RP8
RP7RP7 63RP7RP7 81RP6RP6 63RP6RP6 81RP5RP5 63RP5
RP8 81
OTRB
RP14RP14 81RP13RP13 6
5
7
5
73
RP13
RP13 81
RP16RP16RP16 7
8
65
RP16RP15 5
6RP15RP15 7
A2A3A4A5A6A7
G1G2 GND
VCC
Y2Y3Y4Y5Y6Y7
A1 Y174VHC541
22Ω22Ω
22Ω22Ω
22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω22Ω
RP5 22Ω
22Ω
22Ω22Ω
22Ω22Ω
22Ω
22Ω22Ω22Ω22Ω22Ω22Ω22Ω 18
RP8 22Ω
1DA7 RP15 822Ω
131197531
39373533312927252321191715
403836343230282624222018161412108642
53514947454341
79777573716967656361595755
8078767472706866646260585654525048464442
5
7
7
5
7
5
7
5
J1
HEA
DER
UP
MA
LE N
O S
HR
OU
D
U2
A2A3A4A5A6A7A8
G2G1
GNDVCC
Y2Y3Y4Y5Y6Y7Y8
A1 Y174VHC541
J1
HEA
DER
UP
MA
LE N
O S
HR
OU
D
87
5
7
5
7
5
7
0444
6-04
2
Figure 43. Evaluation Board Schematic (Continued)
AD9248
Rev. B | Page 29 of 48
LQFP PCB LAYERS
0444
6-04
3
Figure 44. PCB Top Layer
AD9248
Rev. B | Page 30 of 48
0444
6-04
4
Figure 45. Bottom Layer
AD9248
Rev. B | Page 31 of 48
0444
6-04
5
Figure 46. PCB Ground Plane
AD9248
Rev. B | Page 32 of 48
0444
6-04
6
Figure 47. PCB Split Power Plane
AD9248
Rev. B | Page 33 of 48
0444
6-04
9
Figure 48. PCB Top Silkscreen (Note that the PCB Supports Both the AD9238 and AD9248 LQFP)
AD9248
Rev. B | Page 34 of 48
0444
6-04
8
Figure 49. PCB Bottom Silkscreen
AD9248
Rev. B | Page 35 of 48
DUAL ADC LFCSP PCB The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with Analog Devices standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for quick ADC evaluation.
POWER CONNECTOR Power is supplied to the board via three detachable 4-lead power strips.
Table 11. Power Connector Terminal Comments VCC1 3.0 V Analog supply for ADC VDD1 3.0 V Output supply for ADC VDL1 3.0 V Supply circuitry VREF Optional external VREF +5 V Optional op amp supply −5 V Optional op amp supply 1VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS The evaluation board accepts a 2 V p-p analog input signal centered at ground at two SMB connectors, Input A and Input B. These signals are terminated at their respective transformer primary side. T1 and T2 are wideband RF transformers that provide the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. The analog signals can be low-pass filtered at the transformer secondary to reduce high frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD8139 op amp that can serve as a convenient solution for dc-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
CLOCK The clock inputs are buffered on the board at U5 and U6. These gates provide buffered clocks to the on-board latches, U2 and U4, ADC input clocks, and DRA, DRB that are available at the output Connector P3, P8. The clocks can be inverted at the timing jumpers labeled with the respective clocks. The clock paths also provide for various termination options. The ADC input clocks can be set to bypass the buffers at solder bridges P2, P9 and P10, P12. An optional clock buffer U3, U7 can also be placed. The clock inputs can be bridged at TIEA, TIEB (R20, R40) to allow one to clock both channels from one clock source; however, optimal performance is obtained by driving J2 and J3.
Table 12. Jumpers Terminal Comments OEB A Output Enable for A Side PDWN A Power-Down A MUX Mux Input SHARED REF Shared Reference Input DR A Invert DR A LATA Invert A Latch Clock ENC A Invert Encode A OEB B Output Enable for B Side PDWN B Power-Down B DFS Data Format Select SHARED REF Shared Reference Input DR B Invert DR B LATB Invert B Latch Clock ENC B Invert Encode B
VOLTAGE REFERENCE The ADC SENSE pin is brought out to E41, and the internal reference mode is selected by placing a jumper from E41 to ground (E27). External reference mode is selected by placing a jumper from E41 to E25 and E30 to E2. R56 and R45 allow for programmable reference mode selection.
DATA OUTPUTS The ADC outputs are latched on the PCB at U2, U4. The ADC outputs have the recommended series resistors in line to limit switching transient effects on ADC performance.
AD9248
Rev. B | Page 36 of 48
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 13. No. Quantity Reference Designator Device Package Value 1 2 C1, C3 Capacitors 0201 20 pF 2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 μF 3 44 C4, C6, C8, C11 to C15, C20, C21,
C24 to C27, C29 to C35, C39 to C61 Capacitors 0402 0.1 μF
4 6 C16 to C19, C37, C38 Capacitors TAJD 10 μF 5 2 C23, C28 Capacitors 0201 0.1 μF 6 6 J1 to J6 SMBs 7 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland 8 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland 9 2 P31, P8 Connectors 10 4 R1, R2, R32, R34 Resistors 0402 36 Ω 11 6 R3, R6, R7, R8, R11, R14, R33, R42, R51, R61 Resistors 0402 50 Ω 12 4 R4, R5, R36, R37 Resistors 0402 33 Ω 13 9 R9, R10, R12, R13, R20, R35, R38, R40, R43 Resistors 0402 0 Ω 14 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω 15 2 R17, R25 Resistors 0402 525 Ω 16 27 R19, R21, R27, R28, R39, R41, R44,
R46 to R49, R52, R54, R55, R57 to R60, R62 to R70 Resistors 0402 1 kΩ
17 4 R22 to R24, R30 Resistors 0402 40 Ω 18 2 R45, R56 Resistors 0402 10 kΩ 19 1 R50 Resistor 0402 22 Ω 20 8 RZ1 to RZ6, RZ9, RZ10 Resistor Pack 220 Ω 21 2 T1, T2 Transformers AWT-1WT Mini-Circuits® 22 1 U1 AD9248 LFCSP-64 23 2 U2, U425 SN74LVTH162374 TSSOP-48 24 2 U32, U7 SN74LVC1G04 SOT-70 25 2 U5, U6 SN74VCX86 SO-14 26 2 U11, U12 AD8139 SO-8/EP 27 4 R6, R8, R33, R42 Resistors 0402 100 Ω
1 P3, P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA. 2 U3, U7 not placed.
AD9248
Rev. B | Page 37 of 48
LFCSP PCB SCHEMATICS
D7_AD7A 49 D8_AD8A 50 D9_AD9A 51 DRVDD252 DRGND253 D10_AD10A 54 D11_AD11A 55 D12_AD12A 56 D13_AD13A 57 OTR_AOTRA 58 OEB_A59PDWN_A60
MUX_SEL61SH_REF62
CLK_A63 AVDD5VD 64 EPAD65
D7BD7_B 32 D6B31D5_B 30DRVDD 29DRGND 28 D4BD4_B 27 D3BD3_B 26 D2BD2_B 25 D1B2423222120DCS 19 ENCB
D6_B
D1_BD0_BOEB_BPDWN_BDFS
CLK_B
D6_
AD
6A48
D5_
AD
5A47
D4_
AD
4A46
D3_
AD
3A45
D2_
AD
2A44
D1_
AD
1A43
D0_
AD
0A42
DR
VDD
141
DR
GN
D1
40
OTR
_BO
TRB
39
D13
_BD
13B
38
D12
_BD
12B
37
D11
_BD
11B
36
D10
_BD
10B
35
D9_
BD
9B34
D8_
BD
8B33
1A
GN
D2
VIN
_A3
VIN
_AB
4A
GN
D1
VD5
AVD
D1
6R
EFT_
A7
REF
B_A
VREF
8VR
EFSE
NSE
9SE
NSE
10R
EFB
_B11
REF
T_B
VD12
AVD
D2
13A
GN
D2
14VI
N_B
B15
VIN
_B16
AG
ND
3
VCC
14
4B13
4A12
4Y11
3B10
3A9
3Y8
1A 1B 1Y 2A 2B 2Y GN
D
1 2 3 4 5 6 7 GN
D7
2Y6
2B5
2A4
1Y3
1B2
1A1
3Y 3A 3B 4Y 4A 4B VCC
8 9 10 11 12 13 14
18 VDAVDD3 17
D0B
D5B
+
++
++
+
ENCA
VREF
C30
0.1μ
FR
4510
kΩ
R56
10kΩ
E2
E27
E25
E30
E41
VD
C11
0.1μ
F SEN
SE
EXT_
VREF
C2
10μF
VREF
AN
D S
ENSE
CIR
CU
IT
MU
XR
35 0ΩR
38
0Ω R20 0Ω R40
0Ω
R14
50Ω
J5
TIEB
TIEA
TO T
IE C
LOC
KS
TOG
ETH
ER
C4
0.1μ
F
VDD
VDD
C60.
1μF
E22
E24 VD
R67
1kΩ
R68
1kΩ
�R
701k
ΩR
691k
Ω
E21
E40 VD
E26
E29 VD
E31
E33 VD
PAD
S TO
SH
OR
TR
EFER
ENC
ES T
OG
ETH
ER
P15
P16
P18
P17
REF
TAR
EFTB
REF
BA
REF
BB
REF
B_B
REF
T_B
AM
POU
TBR36
33Ω
R37
33Ω
AM
POU
TBB C
320
pF
C28
0.1μ
F
C7
10μF
C54
0.1μ
FC23
0.1μ
F
C5
10μF
C55
0.1μ
F
C24
0.1μ
F
C26
0.1μ
F
C29
0.1μ
F
C27
0.1μ
F
H3
MTH
OLE
6 H1
MTH
OLE
6H
2M
THO
LE6 H4
MTH
OLE
6
41
23
41
23
41
23
P5 P6 P7
VD VDD
VDL
C37
10μF
C38
10μF
C16
10μF
C17
10μF
C18
10μF
C19
10μF
C39
0.1μ
F
C43
0.1μ
F
C44
0.1μ
F
C45
0 .1μ
F
+5V
–5V
EXT_
VREF
VDL
VDD
VD
P11
P4P1
E34
E16
VD VDR
551k
Ω
E37E
38
R48
1kΩ
0Ω R12 0Ω R13
E35E3
6VD
R49
1kΩ
C41
0.1μ
F
VD
VD
J2EN
CO
DE
BR
5150
Ω
C42
0.1μ
F
R54
1kΩ
R52
1kΩ
P2P9
U3
P13
ENC
B
VD
VD
C22
10μF
C57
0.1μ
F
R6
100Ω
R8
100Ω
TIEB
1 2 3
5 4
SN74
LVC
1G04
NC
A GN
D
VCC Y
1 2 3
5 4
SN74
LVC
1G04
NC
A GN
D
VCC Y
P10
P12
C36
10μF
C58
0.1μ
F
ENC
A
VD
VDR
3310
0Ω
R42
100Ω
R5022Ω
R430Ω
U1
E13
E12
VD VDR
471k
Ω
E15
E14
R46
1kΩ
0Ω R90Ω R10 C
LKLA
TB
DR
BDR
A
CLK
LATA
J6R
6150
Ω
C56
0.1μ
F
VD
J3
ENC
OD
E A R
1150
Ω
C40
0.1μ
F
R41
1kΩ
TIEA
R39
1kΩ
VD
C25
0.1μ
F
E3
E4VD
R44
1kΩ
P14
E6E5VD
E20
E18
VD
E9E7
VD
R66
1kΩ
R65
1kΩ
R64
1kΩ
E10
E17
R63
1kΩ
R62
1kΩ
VD
VDD
C8
0.1μ
F
MU
X
DU
T C
LOC
K S
ELEC
TAB
LETO
BE
DIR
ECT
OR
BU
FFER
ED
74LC
X8674
LCX8
6
R4
33Ω
J1AIN
B
C13
0.1μ
F
R59
1kΩ
R7
50Ω
AM
PIN
B
C10
10μF C12
0.1μ
F
E43
E42
C9
10μFC
310.
1μF
R57
1kΩ
1 2 3
6 5 4
CTA
PB
R5
33Ω
1 2 3
6 5 4C
TAPA
AM
POU
TAB
AM
POU
TAC
140.
1μF
AM
PIN
A
R3
50Ω
J4C
120
pF
VD–5
V+5
VVD
VDD
VDL
EXT_
VREF
CTA
PA R58
1kΩ VD VD
R60
1kΩ
CTA
PB
T1T2
SEE
BEL
OW
DU
T C
LOC
K S
ELEC
TAB
LETO
BE
DIR
ECT
OR
BU
FFER
ED
U5
U6
U7
AIN
A
0444
6-05
0
Figure 50. PCB Schematic (1 of 3)
AD9248
Rev. B | Page 38 of 48
R8
R7
R6
R5
R4
R3
R1
R2
8765431 216 15 14 13 12 11 10 9
220
220
220
135791113151719212325272931333537
246810121416182022242628303234363840
HEA
DER
4022
0
SN74
LVC
H16
373A
U2
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GN
D
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GN
D
GN
D
GN
DG
ND
GN
D
GN
DG
ND
220
R8
R7
R6
R5
R4
R3
R1
R2 22
0
220
220
SN74
LVC
H16
373A
U4
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GN
D
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GN
D
GN
D
GN
DG
ND
GN
D
GN
DG
NDQ
= O
UTP
UT
D =
INPU
T
4746444341403837
23568911123635333230292726
1314161719202223 4101521
45393428 4825
718
4231
124C
LKLA
TB
CLK
LATB
CLK
LATA
VDL
VDL
VDL
RZ6
RSO
16IS
O
RZ5
RSO
16IS
O
8765431 216 15 14 13 12 11 10 9
RZ4
RSO
16IS
O
8765431 216 15 14 13 12 11 10 9
RZ3
RSO
16IS
O
4746444341403837
23568911123635333230292726
1314161719202223 4101521
45393428 4825
718
4231
124
8765431 216 15 14 13 12 11 10 9
RZ1
RSO
16IS
O
135791113151719212325272931333537
246810121416182022242628303234363840
P3
RZ9
RSO
16IS
O
RZ1
0R
SO16
ISO
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D8A
D9A
D2A
D3A
D4A
D5AD6AD7A
D0A
D1A
GN
D
D9P
D8P
D7P D6P
D5P
D4P
D3P
D2P
D1P
D0P
GN
DD
RA
DR
B
OTR
AD
13A
D12
AD
11A
D10
A
D7B
D9B
D8B
OTR
BD
13B
D12
BD
11B
D10
B
DO
RP
D13
PD
12P
D11
PD
10P
DO
RQ
D13
QD
12Q
D11
QD
10Q
D9Q D0Q
D8Q D1Q
D2Q
D6Q
D7Q D3Q
D4Q
D5Q
D13
PD
12P
D11
PD
10P
D0P
DO
RP
D13
QD
12Q
D11
QD
10Q
D0Q
DO
RQ
VDL
VDL
VDL
VDL
CLK
LATA
8765431 216 15 14 13 12 11 10 9
RZ2
RSO
16IS
O
D5B
D6B
D4B
D3B
D2B
D1B D0B
R8
R7
R6
R5
R4
R3
R1
R2 R8
R7
R6
R5
R4
R3
R1
R2
R8
R7
R6
R5
R4
R3
R1
R2
Q =
OU
TPU
TD
= IN
PUT
R8
R7
R6
R5
R4
R3
R1
R2
8765431 216 15 14 13 12 11 10 9
R8
R7
R6
R5
R4
R3
R1
R2
8765431 216 15 14 13 12 11 10 9
R8
R7
R6
R5
R4
R3
R1
R2
8765431 216 15 14 13 12 11 10 9
13579111315171921232527293133353739
246810121416182022242628303234363840
HEA
DER
4013579111315171921232527293133353739
246810121416182022242628303234363840
P8
VDL
C49
0.1μ
F
C48
0.1μ
F
C47
0.1μ
F
C46
0.1μ
F
C53
0.1μ
F
C52
0.1μ
F
C51
0.1μ
F
�C
50
0.1μ
F
3939
VDL
0444
6-05
1
Figure 51. PCB Schematic (2 of 3)
AD9248
Rev. B | Page 39 of 48
+IN
+OU
T
–IN
–OU
TEPA
D
NC
V+V–
VOC
M
AD
8139
C20
0.1μ
F8
41
5
9
73
62 U12
C35
0.1μ
F
R29
499Ω
R30
40ΩR
2552
5Ω
AM
POU
TBA
MPO
UTB
B
+5V
–5V
AM
PIN
B
C34
0.1μ
F
R28
1kΩ
R27
1kΩ
VD
R24
40Ω
+IN
+OU
T
–IN
–OU
TEPA
D
NC
V+V–
VOC
M
AD
8139
C21
0.1μ
F8
41
5
9
73
62 U11
C32
0.1μ
F
R17
525Ω
R22
40ΩR
1649
9Ω
AM
POU
TAB
AM
POU
TA
+5V
–5V
AM
PIN
A
C33
0.1μ
F
R19
1kΩ
R21
1kΩVD
R23
40Ω
OP
AM
P IN
PUT
OFF
PIN
1 O
F TR
AN
SFO
RM
ER
0444
6-05
2
R31
499Ω
C61
R26
499Ω
C15 R
1549
9Ω
C60
R18
499Ω
C59
Figure 52. PCB Schematic (3 of 3)
AD9248
Rev. B | Page 40 of 48
LFCSP PCB LAYERS
0444
6-05
3
Figure 53. PCB Top-Side Silkscreen
AD9248
Rev. B | Page 41 of 48
0444
6-05
4
Figure 54. PCB Top-Side Copper Routing
AD9248
Rev. B | Page 42 of 48
0444
6-05
5
Figure 55. PCB Ground Layer
AD9248
Rev. B | Page 43 of 48
0444
6-05
6
Figure 56. PCB Split Power Plane
AD9248
Rev. B | Page 44 of 48
0444
6-05
7
Figure 57. PCB Bottom-Side Copper Routing
AD9248
Rev. B | Page 45 of 48
0444
6-05
8
Figure 58. PCB Bottom-Side Silkscreen
THERMAL CONSIDERATIONS The AD9248 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. Improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. Recommended array is 0.3 mm vias on 1.2 mm pitch. θJA = 26.4°C/W with this recommended configuration. Soldering the slug to the PCB is a requirement for this package.
0444
6-05
9
Figure 59. Thermal Via Array
AD9248
Rev. B | Page 46 of 48
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBD 0517
06-A
TOP VIEW(PINS DOWN)
1
1617
3332
484964
0.230.180.13
0.40BSC
LEAD PITCH
1.60MAX
0.750.600.45
VIEW A
PIN 1
0.200.09
1.45 1.40 1.35
0.08COPLANARITY
VIEW AROTATED 90° CCW
SEATINGPLANE
7°3.5°0°0.15
0.05
9.209.00 SQ8.80
7.207.00 SQ6.80
Figure 60. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-1)
Dimensions shown in millimeters
PIN 1INDICATOR
TOPVIEW
8.75BSC SQ
9.00BSC SQ
164
1617
4948
3233
0.500.400.30
0.50 BSC 0.20 REF
12° MAX0.80 MAX0.65 TYP
1.000.850.80
7.50REF
0.05 MAX0.02 NOM
0.60 MAX0.60 MAX
*4.854.70 SQ4.55
EXPOSED PAD(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION 08
2908
-B
SEATINGPLANE
PIN 1INDICATOR
0.300.250.18
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad
(CP-64-1) Dimensions shown in millimeters
AD9248
Rev. B | Page 47 of 48
ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9248BSTZ-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BSTZ-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BSTZ-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BSTZRL-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BSTZRL-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BSTZRL-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1 AD9248BCPZ-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BCPZ-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BCPZ-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BCPZRL-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BCPZRL-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BCPZRL-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD9248BST-65EBZ Evaluation Board with AD9248BSTZ-65 AD9248BCP-65EBZ Evaluation Board with AD9248BCPZ-65
1 Z = RoHS Compliant Part.
AD9248
Rev. B | Page 48 of 48
NOTES
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