adaptive beamforming using qr in fpga richard walke, real-time system lab advanced processing centre...
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![Page 1: Adaptive beamforming using QR in FPGA Richard Walke, Real-time System Lab Advanced Processing Centre S&E Division](https://reader036.vdocuments.net/reader036/viewer/2022062422/56649ed95503460f94be79d1/html5/thumbnails/1.jpg)
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Adaptive beamforming using QR in FPGARichard Walke, Real-time System LabAdvanced Processing CentreS&E Division
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Contents
1 Architecture of adaptive beamformer
2 FPGA components
• Digital receiver
• QR processor – for adaptive weight calculation
3 Design methodology
4 Demonstration overview
5 Conclusions
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Architecture of adaptive beamformerSection 1
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Rx
Beamformed signal
Antenna Array
Analogue receivers
DRx
DRx
DRx
Rx
Rx
Digital receivers
Adaptive Weight Calculation
+
W1
W2
Wn
Spatial filter
Adaptive beamformerArchitecture of adaptive beamformer
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FPGA componentsSection 2
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Runtime configuration parameters
2
Imagereject
Bandwidthcontrol
Complexequaliser
Imagereject
Bandwidthcontrol
Imagereject
Bandwidthcontrol
Imagereject
Bandwidthcontrol
Radar receiver specification
Array of programmable ‘tap-processors’
Software configurable FIRFPGA Components
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• Software programmable parameters include:
– filter length
– decimation ratio
– complex/real arithmetic
– number of channels
– time varying filtering (inter & intra-pulse)
• Performance 20-30 GOPS on XC2V6000-5
– 100 GOPS on Virtex2 Pro (2003)
FPGA Components
Software configurable FIR
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• Building block for a range of adaptive algorithms– Sample matrix inversion (SMI)– Soft constraints– ESMI– STAP
Pre-processor Post-processing
QR decomposition
RISC/DSP
FPGA
Beamforming weightsAntenna data
Constraints
Weight calculation using QRFPGA Components
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QR decompositionFPGA Components
r2,2 r2,3
x1 y
r1,1 u1r1,2 r1,3 r1,4
r2,4 u2
u3r3,4r3,3
r4,4 u4
x2 x3 x4
Input dataVectorise cell:11 real floating-point operations
Rotate cell:16 real floating-pointoperations
For SMI: Rw=u
(r,x)
(r’,0)
cos =r
r2+x2
sin =x
r2+x2
(u,y)(u’,y’)
u’y’ =
uy
cos sin -sin cos
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• Good numerical properties. Arithmetic choices:
– CORDIC: shift-add
– Fixed-point: multiply-add
– Floating-point: Higher dynamic range, allows algorithms with fewer operations & lower wordlength. Smallest!
• Highly parallel (Givens rotations)
– Suits FPGA
– Need to reduce parallelism for many applications!
Features of QRFPGA Components
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1,1 1,31,2 1,4 1,5
2,2 2,42,3 2,5
3,3 3,53,4
4,4 4,5
1,6
2,6
3,6
4,6
5,5 5,6
2. Discretemapping
67% utilisation80%
60%
40%
20%
100%
100%
83%
67%
50%
33%
100%
67% utilisation
1. Mixed mapping
Obtaining lower-levels of parallelismFPGA Components
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Linear systolic array
Novel mapping of QRFPGA Components
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FPGA implementation
16
16
11
16
16
16
16
16
16
139 14-bit FP operators @ 160MHz = 22 GFLOPSNumber of Ops
8xFP multipliers
2 x
complex
adder
Complex
multiplier
FP
addFP divider vectorise
processor
rotate
processor
rotate
processor
rotate
processor
rotate
processor
rotate
processor
rotate
processor
rotate
processor
FP
add
Complex
multiplier
XCV3200E-8
FPGA Components
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QR processor - main featuresFPGA Components
1 Boundary3 Internal
32
23% 6 GFLOPS 2.24W4
1 Boundary12 Internal
82%2 20.3 GFLOPS 8W6
LUTS
Rams3
FFs
Mults
34
15K
16K
22%
23%
22%
23%
4 GFLOPS 70WPentiumTM 4 2GHz1
1 Estimated (based on data from Richard Linderman)2 Estimated (design too large for PC)3 Also depends upon number of inputs4 Obtained via Xpower5 For XC2V6000-56 Extrapolated
101MHz5
1 Boundary9 Internal
74% 15 GFLOPS 7W6
14-bit mantissa
17-bit mantissa
14-bit mantissa
97MHz
100MHz2
Size Utilisation (XC2V6000) Operations PowerMantissa wordlength
Clock
x50
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Heterogeneous design methodologySection 3
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GEDAETM
Heterogeneous design methodology
• Graphically specify system
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GEDAETM
Heterogeneous design methodology
• Graphically specify system
– primitive functions in ‘c’
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GEDAETM
Heterogeneous design methodology
• Graphically specify system
– primitive functions in ‘c’
– executable specification
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GEDAETM
Heterogeneous design methodology
• Graphically specify system
– primitive functions in ‘c’
– executable specification
• Auto-code generation
– parallel programme constructed by GEDAE
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GEDAETM
Heterogeneous design methodology
• Graphically specify system
– primitive functions in ‘c’
– executable specification
• Auto-code generation
– parallel programme constructed by GEDAE
• Currently no support for FPGA
– highly compatible model
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Core based methodologyHeterogeneous design methodology
• Cores used for key functions
– FFT, QR, FIR filter ...
– Build in parallelism (manually)
– Parameterised Processor
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Core based methodologyHeterogeneous design methodology
• Cores used for key functions
– FFT, QR, FIR filter ...
– Build in parallelism (manually)
– Parameterised
• Automatically generated system
– communications inserted
FPGA
Processor
Processor
FFT core from library
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Core based methodologyHeterogeneous design methodology
• Cores used for key functions
– FFT, QR, FIR filter ...
– Build in parallelism (manually)
– Parameterised
• Automatically generated system
– communications inserted
• Architectural exploration
– Compaan gives Matlab NLP to VHDL
– RTL output in future version
FPGA
Processor
Processor
FFT core from library
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Adaptive beamformer demonstration overview
Section 4
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System mappingDemonstration overview
Delay
Sample
PCI IF
Virtual channel IF
Chan0 Chan1
FPGA (TransTech PMC)
Chan2 Chan3
QRDRx
Virtual Channel API
PowerPC (DNA VQG4 VME)
Back-substitution
Host PC (laptop)
Environment synthesis
and system configuration
Host PC (laptop)
Verification and display
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Conclusion
• FPGAs
– Performance dependent upon level of optimisation
– Floating-point is realistic
– 10x compute improvement
– 5 - 20x power improvement
• Design is main issue
– Hardware design: High levels of parallelism required
– Core-based design approaches offer interim solution
– Architectural synthesis tools are emerging
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Acknowledgements
• The project to develop a core-based design methodology is a collaboration between:
– QinetiQ Ltd
• poc: [email protected]
– BAE SYSTEMS ATC, Gt Baddow
• poc: [email protected]
• Contributions have been made by John McAllister under contract with the Queen’s University of Belfast.
• This work was sponsored by the United Kingdom Ministry of Defence Corporate Research Programme.
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