advance datasheet revision: april 2016

Preliminary Information: The data contained in this document describes new products in the sampling or preproduction phase of development and is for information only.

Northrop Grumman reserves the right to change without notice the characteristic data and other specifications as they apply to this product. The product represented by

this datasheet is subject to U.S. Export Law as contained in ITAR or the EAR regulations.

Advance Datasheet Revision: April 2016

APN244 24-28 GHz GaN Power Amplifier

Web: http://www.as.northropgrumman.com/mps ©2016 Northrop Grumman Systems Corporation

Phone: (310) 814-5000 • Fax: (310) 812-7011 • E-mail: [email protected]

Product Features

RF frequency: 24 to 28 GHz

Linear Gain: 20 dB typ.

Psat: 38 dBm typ.

Die Size: 6.43 sq. mm.

0.2um GaN HEMT Process

4 mil SiC substrate

DC Power: 28 VDC @ 0.5 A

Product Description The APN244 monolithic GaN HEMT amplifier

is a broadband, two-stage power device,

designed for use in Ka-Band communication

applications such as point-to-point and

point-to-multipoint digital (LMDS) radios and

SatCom Terminals. To ensure rugged and

reliable operation, HEMT devices are fully

passivated. Both bond pad and backside

metallization are Au-based that is compatible

with epoxy and eutectic die attach methods.

Applications

Point-to-Point Digital Radios

Point-to-Multipoint Digital Radios

Space-Earth Communications

Space Research & Earth Exploration

Performance Characteristics (Ta = 25°C)

Absolute Maximum Ratings (Ta = 25°C)

X = 3.3mm Y = 1.95mm

Specification * Min Typ Max Unit Frequency 24 28 GHz

Linear Gain 18 20 dB

Input Return Loss 7 8 dB

Output Return Loss 4 10 dB

P1db (PP*) 36 dBm

Psat (PP*) 37 38 dBm

PAE @ Psat (PP*) 31 %

Max PAE (PP*) 32 %

Vd1, Vd2 28 V

Vg1 -3.5 V

Vg2 -3.5 V

Id1 100 mA

Id2 400 mA

Parameter Min Max Unit

Vd1 ,Vd2 20 28 V

Id1 100 mA

Id2 400 mA

Vg1, Vg2 -5 0 V

Input drive level 27 dBm

Assy. Temperature 300 deg. C

(TBD seconds)

* Pulsed-Power On-Wafer unless otherwise noted

Approved for Public Release: Northrop Grumman Case 16-1027, 05/16








Linear Gain vs. Frequency *

Measured Performance Characteristics (Typical Performance at 25°C)

Vd = 28.0 V, Id1 = 100 mA, Id2 = 400 mA

Power, Gain, PAE% vs. Frequency *

Output Return Loss vs. Frequency *

* Pulsed-Power On-Wafer

Input Return Loss vs. Frequency *

0

2

4

6

8

10

12

14

16

18

20

22

24

26

20 21 22 23 24 25 26 27 28 29 30 31 32

Gain

(d

B)

Frequency (GHz)

0

5

10

15

20

25

30

35

40

45

23 24 25 26 27 28 29 30

Po

ut

(dB

m),

Gain

(d

B),

PA

E%

Frequency (GHz)

Linear Gain (dB) Gain @ Pin=-10 dBm

PGain@Pin=27dBm (dB) P1dB (dBm)

Psat (dBm) PAE% @ PSat

Max PAE%

-20-19-18-17-16-15-14-13-12-11-10-9-8-7-6-5-4-3-2-10

20 21 22 23 24 25 26 27 28 29 30 31 32

Ou

tpu

t R

etu

rn L

oss (

dB

)

Frequency (GHz)

-30

-25

-20

-15

-10

-5

0

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Inp

ut

Retu

rn L

oss (

dB

)

Frequency (GHz)









Power, Gain, PAE% vs. Frequency

Pulsed-Power On-Wafer

Output Power, Gain vs. Input Power


PAE% vs. Input Power


Stage Currents vs. Input Power


Measured Performance Characteristics (Typical Performance at 25°C)

Vd = 28.0 V, Id1 = 100 mA, Id2 = 400 mA

0

5

10

15

20

25

30

35

40

-10 0 10 20 30

PA

E%

Input Power (dBm)

Freq=23 GHz

Freq=24 GHz

Freq=25 GHz

Freq=26 GHz

Freq=27 GHz

Freq=28 GHz

Freq=29 GHz

Freq=30 GHz

02468101214161820222426283032343638404244

0

2

4

6

8

10

12

14

16

18

20

22

-10 0 10 20 30

Po

ut(

dB

m)

Gain

(d

B)

Input Power (dBm)

Gain@23GHzGain@24GHzGain@25GHzGain@26GHzGain@27GHzGain@28GHzGain@29GHzGain@30GHzPiPo@23 GHzPiPo@24 GHzPiPo@25 GHz

Gain

Pout

0

100

200

300

400

500

600

700

800

900

1000

-10 -5 0 5 10 15 20 25 30

Id1(m

A)

Pin (dBm)

Id1@23 GHz Id1@24 GHz




Id2@23GHz Id2@24GHz

Id2@25Ghz Id2@26GHz

Id2@27GHz Id2@28GHz

Id2@29GHz Id2@30GHz

0

5

10

15

20

25

30

35

40

45

23 24 25 26 27 28 29 30

Po

ut

(dB

m),

Gain

(d

B),

PA

E%

Frequency (GHz)

Linear Gain (dB) Gain @ Pin=-10 dBm

PGain@Pin=27dBm (dB) P1dB (dBm)

Psat (dBm) PAE% @ PSat

Max PAE%









Die Size and Bond Pad Locations (Not to Scale)

Biasing/De-Biasing Details:

Bias is single sided and is from the top only.

Listed below are some guidelines for GaN device testing and wire bonding: a. Limit positive gate bias (G-S or G-D) to < 1V

b. Know your devices’ breakdown voltages

c. Use a power supply with both voltage and current limit.

d. With the power supply off and the voltage and current levels at minimum, attach the ground lead to

your test fixture.

i. Apply negative gate voltage (-5 V) to ensure that all devices are off

ii. Ramp up drain bias to ~10 V

iii. Gradually increase gate bias voltage while monitoring drain current until 20% of the operating

current is achieved

iv. Ramp up drain to operating bias

v. Gradually increase gate bias voltage while monitoring drain current until the operating current

is achieved

e. To safely de-bias GaN devices, start by debiasing output amplifier stages first (if applicable):

i. Gradually decrease drain bias to 0 V.

ii. Gradually decrease gate bias to 0 V.

iii. Turn off supply voltages

f. Repeat de-bias procedure for each amplifier stage


1950 µm

903 µm 903 µm

3300 µm

1327 µm

VG

2

VD

2

RFIN

GND

GND

GN

D

GN

D

GN

D

RFOUT GND

GND

GN

D

X = 3300 µm 25 µm Y = 1950 25 µm DC Bond Pad = 100 x 100 0.5 µm RF Bond Pad = 100 x 100 0.5 µm Chip Thickness = 101 5 µm

528 µm

928 µm

VD

1

VG

1

1927 µm








RFIN GND

GND RFOUT

GND

GND

VG

2

VD

2

GN

D

GN

D

GN

D

GN

D

VG

1

Recommended Assembly Notes

1. Bypass caps should be 100 pF (approximately) ceramic (single-layer) placed no farther than 30 mils from the amplifier.

2. Best performance obtained from use of <10 mil (long) by 3 by 0.5 mil ribbons on input and output.

3. Part must be biased from both sides as indicated.

4. The 0.1uF, 50V capacitors are not needed if the drain supply line is clean. If Drain Pulsing of the device is to be used, do NOT use the 0.1uF , 50V Capacitors.

Mounting Processes

Most NGAS GaN IC chips have a gold backing and can be mounted successfully using either a conductive epoxy or

AuSn attachment. NGAS recommends the use of AuSn for high power devices to provide a good thermal path and a

good RF path to ground. Maximum recommended temp during die attach is 320oC for 30 seconds.

Note: Many of the NGAS parts do incorporate airbridges, so caution should be used when determining the pick up

tool.

CAUTION: THE IMPROPER USE OF AuSn ATTACHMENT CAN CATASTROPHICALLY DAMAGE GaN CHIPS.

Suggested Bonding Arrangement

RF Output

Substrate

RF Input

Substrate

= 100 pF, 15V (Shunt)

= 10 Ohms, 30V (Series)

= 0.01uF, 15V (Shunt)

VG2 VD2

VG1

VD1

PLEASE ALSO REFER TO OUR “GaN Chip Handling Application Note” BEFORE HANDLING,

ASSEMBLING OR BIASING THESE MMICS!

= 0.1uF, 15V (Shunt)

= 100 pF, 50V (Shunt)

= 0.01uF, 50V (Shunt)

= 0.1uF, 50V (Shunt) [4] [4] [4]

VD

1


advance datasheet revision: april 2016

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