www.renesas.eu 2011.02

Advance Information

PFESiP(Platform for Embedded System-in-Package)EP-1 “Configurable Engine for Motor Control”Renesas Electronics proudly presents its new customizable MCU, the PfESiP EP-1 (platform for embedded system in package embedded processor – 1 series). This customizable MCU is suitable for motor control in industrial equipments such as servo and inverter motor systems and in consumer equipments such as outdoor unit of air-conditioning systems.

PFESiP EP-1 embeds a high performance V850E2 MCU, USB2.0 device/host, UARTs, memory controller and up to 240K customizable gates (UDL). By using this platform, development cost and period can considerably be reduced in comparison with full-custom single-chip design. Embedded GA allows the reduction of bill of material over the board making it cheaper and easier to design. This solution provides furthermore higher electrical reliability thanks to the direct connection between CPU and logic IC (eg. reduction of SSO noise and EMS).

System Block Example

In the above application example, the PfESiP has been used to realize an “Configurable Engine for Motor Control”. The fixed part of this MCU, allow direct connection of Flash, RAM or ROM memories, USB connection for external devices, such as USB key, and an A/D. Customer Logic part is used to integrate additional RAM, Phase generator and phase driver for motor control.

V850E2CPU

Instructioncache

Datacache

InstructionRAM

DataRAM

UART

Clockedserial

interface

USBhost

USBfunction

Memorycontroller

Interruptcontroller

DMAcontroller

Timer A/Dconverter

EEPROM

Memorycontroller

Businterface

Watchdogtimer

Real timeclock

WorkRAM

Interruptrequester

Temperature Sensor

Flash ROM Program code, fixed data…

EA-9HDOver-current

detection

PFES

iP M

icro

Com

pute

rPF

ESiP

/V85

0EP1

PFESiP EP-1

WorkRAM Dead time

processing

3-phasePWM

generation

Carriergeneration

6-phase PWM output

driver

Monitor

TimerENC

IM

Rotation and position sensor

Phot

ocou

pler

/ G

ate

driv

er

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All rights reserved. Printed in Germany.

Before purchasing or using any Renesas Electronics products listed herein, please refer to the latest product manual and/or data sheet in advance.

Document No. R05PF0019ED0000

PFESiP – EP-1 „Configurable Engine for Motor Control“

Features

V850E2 CPU core, max. 430 MIPS in operation ●

Up to 240K gates in the customizable logic ●

USB2.0 FS (host x2, device x1) ●

On-board memory controller, UARTs, ADC ●

Selectable external bus 16-/32-bits ●

Large instruction RAM: 192 KB ●

Large choice of packages (from 417 to 572 PBGA) ●

Low power consumption ●

Low EMI noise ●

Evaluation Board

Block Diagram

EP - 1

V850E2 Core

NPB

dLB CPUCore

NPBI/F

dMEM32 kB

i$ 8kB

iMEM192 kB

N-Wired$ 8kB

INTC

VSB

Arbiter

RCUDCU

TimerC x4ch

TimerD x6ch

UART5 x4ch

PWM x2ch

PORT

CSI0 x2ch

TimerENC x2chWork32kB

DMACNBA85E300

INTCI/F

VSBI/F

N-Wire ICE

ADC x8

USB 2.0 FS Function

USB 2.0 FS Host x2

User Logic

80K/160K/240K

MCU for PFESiP“PFESiP/V850EP1”Ext. bus 32-bit type

SiP Int. connection(16-bit bus)

Aurora : UX4 (0.15 um)GA/EA : UC1H (0.35 um)

Ext. bus(32-bit)

FlashROM

SDRAM SRAM I/O

External Bus

iLB

MEMCNBA85E535