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ADVANCEMulti-simulation Concepts

John Colley10th November 2011

Southampton

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Introduction

• Motivation• Discrete Event Simulation Principles• Single-thread/Multi-thread Implementations• Co/Multi-simulation Principles– Two Simulators– More than Two Simulators

• Continuous Simulation Principles• Hybrid Continuous/Discrete Multi-simulation• Summary

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Discrete Event Simulation: Motivation

• Dominant Verification Technology for Synchronous Digital Hardware and Systems on Chip– $300 million per year Market– Mature Tools (30 years of development)– High Price Tools ($30k per seat + maintenance)

• Single Kernel, Multi-Language Tools for Model Re-use– VHDL– SystemVerilog– SystemC (C++)– C

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A

C

B

D

C1

C2

COMPONENT VIEW

Components: A, B, C, D (processes)

Connections: C1, C2 (unidirectional)

Ports: IN OUT

SIMULATOR API

GetValue(port)

HasChanged(port)

SetValue(OUT port, val, delay)

ScheduleEval(component, delay)

Discrete Event Simulation

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

The Two-list Simulation Algorithm

t = n

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

The Two-list Simulation Algorithm

t = n

Why not just have a single, time-ordered list?

7

A

C

B

D

C1

C2

updatelist

evaluationlist

A B C D

t = 0

Time Zero Initialisation: Evaluate all Components

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

Component evaluations call SetValue, ScheduleEval

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

Component evaluations call SetValue, ScheduleEval

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

C: future eval

D: future eval

C: C2 new val

A: C1 new val

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

Global Time is Advanced to t = 20

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

Add to eval list each component on C1 fanout

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

B D

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A

C

B

D

C1

C2

updatelist

evaluationlist

B calls ScheduleEval with delay 40

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

B D

t = 60 EB

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A

C

B

D

C1

C2

updatelist

evaluationlist

Time advances to t = 30: two updates

t = 20 C1

t = 30 C2t = 30 ED

t = 50 EC

t = 60 EB

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A

C

B

D

C1

C2

updatelist

evaluationlist

Time advances to t = 30: two updates, one eval

t = 30 C2t = 30 ED

t = 50 EC

t = 60 EB

D

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 30 C2t = 30 ED

t = 50 EC

t = 60 EB

Simple Algorithm, Complex Implementation forPerformance

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 30 C2t = 30 ED

t = 50 EC

t = 60 EB

Simple Algorithm, Complex Implementation forPerformance

Why not just have a single, time-ordered list?

RACE

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A

C

B

D

C1

C2update

list

evaluationlist

Simulating Models without Discrete Delays –Unit Delay

EB C1

Each evaluate/updatecycle advances time byone tick

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A

C

B

D

C1

C2

The Simulation Testbench

Primaryinputs

Primaryoutputs

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A

C

B

D

C1

C2

The Simulation Testbench

Primaryinputs

PrimaryoutputsIn principle, just another component using the API

In practice, a complex model of the design environment:Constrained Random Test Generation

Assertion CheckingFunctional Coverage Metrics

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A

C

B

D

C1

C2

Discrete Event Simulation Languages: Hierarchy

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A

C

B

D

C1

C2

Discrete Event Simulation Languages: Hierarchy

Hierarchy is flattened for simulation

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Discrete Event Simulation Languages: Function

• There must be an Entry Point to implement the Eval API call

• Eval call must execute to completion– Method call– Actor

• Languages with Embedded Wait– Eval call must resume at the Wait Point– Implement as Finite State Machine• Stored Current State represents the next Entry Point

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

A Concurrent Simulator Implementation?

t = n

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

A Concurrent Simulator Implementation

t = n

A B C D

EVAL Components in Parallel

Atomic Insertion

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

A Concurrent Simulator Implementation

t = n

A B C D

EVAL Components in Parallel

Atomic InsertionAmdahl’s Law Revisited for Single Chip Systems

Jo-Ann M. Paul and Brett H. Meyer, 2006

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Event-Driven vs Process-Driven

• Event-Driven– Single core, single process

• Process-Driven– Threads• OpenMP

– Portable– Optimised for multi-core

• Python Generators (coroutines)• Single core only (SimPy)

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A

C

B

D

C1

C2

updatelist

evaluationlist

t = 0

What if Component D does not have a native implementation?

t = n

A B C D

C3

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A

C

B

DExternalModel

C1

C2

updatelist

evaluationlist

t = 0

Component D is simulated with a different Simulator:Co-Simulation

t = n

A B C D

C3

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A

C

B

DExternalModel

C1

C2

Master/Slave Co-Simulation

Master Simulator

- Master Event Queue- Design Topology

- Components- Connectors

- Initiates the Slave and establishes Inter-Process Communication

Slave Simulator

- Slave Event Queue- Slave Component

C3

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A

C

B

DExternalModel

C1

C2

Master/Slave Co-Simulation

Co-Simulation

- Initialise Master Simulator- Initialise Slave Simulator- Get time Ts of next event

from Slave- Run Master until

- Time = Ts OR- D sees change on C1

or C2- Get time Tm of next event

from Master- Tell Slave to run until

- Time = Tm- B sees change on C3

C3

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A

C

BExternalModel

DExternalModel

C1

C2

What if B is represented by a 3rd Simulator?

Master Simulator

- Initialise Master Simulator- Initialise Slave Simulator- Get time Ts of next event

from Slave- Run Master until

- Time = Ts OR- D sees change on C1

or C2- Get time Tm of next event

from Master- Tell Slave to run until

- Time = Tm- B sees change on C3

C3

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A

C

BExternalModel

DExternalModel

C1

C2

What if B is represented by a 3rd Simulator?

Master Simulator

- Initialise Master Simulator- Initialise Slave Simulator- Get time Ts of next event

from Slave- Run Master until

- Time = Ts OR- D sees change on C1

or C2- Get time Tm of next event

from Master- Tell Slave to run until

- Time = Tm- B sees change on C3

C3Simulators run in

Lock-Step

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A

C

B

DExternalModel

C1

C2

Two Simulators, Slave Evaluates much more slowly than Master and Slave can Backtrack

Co-Simulation

- Initialise Master Simulator- Initialise Slave Simulator- Run Slave- Run Master until D sees a

change on C1 or C2 at time Tc

- If Slave time Ts < Tc- Continue running

Slave until Tc- Else

- Slave backtracks to Tc- Slave accepts new input

value

C3

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Continuous v Discrete Simulation

Continuous• Equation-basedmodel cont01 Real x, y, z;equation x + y + z = 5.000; der(y) = x + 1.365; y = der(z) – 1.875;end cont01;

Discrete• Assignment-basedalways @ (posedge clk)begin x <= x + 1 y <= x - 1end

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Hybrid Modeling

• Continuous-time + Discrete-time Modeling– Modelica “when”

model t03 Real x, y, z; equation x + y + z = 5; when sample(0, 1) then x = x + 1; y = delay(x – 1, 20); end when; end t03;

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A

C

BExternalModel

DExternalModel

C1

C2

What if B is represented by a Continuous Simulator?

Multi-Simulation

- A, C in Master multi-sim environment

- B in Continuous Simulator- Modelica- Simulink

- D in 3rd party Discrete Simulator

- IN/OUT interfaces to B must be Discrete

- Modelica when

C3

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A

Multi-sim Architecture

Rodin Platform

ProB Multi-Simulation Core

3rd

Partysim

3rd

Partysim

. . .

ADVANCE

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Summary

• Discrete Event Simulation– Two-List Algorithm for Deterministic Execution– “Event-driven” or “Process-driven”– Hardware/Software

• Continuous Simulation– Modelica, Matlab/Simulink

• Co-Simulation/Multi-Simulation– Optimisations for 2 Simulators– More than 2 Simulators must run in Lock-Step– Hybrid Continous/Discrete Simulation

• Discrete Interfaces