advanced analog frequency synthesizers, clock and data ... · m.h. perrott 2 bandwidth constraints...

Short Course On Phase-Locked Loops and Their Applications

Day 1, PM Lecture

Advanced Analog Frequency Synthesizers, Clock and Data Recovery

Michael PerrottAugust 11, 2008

Copyright © 2008 by Michael H. PerrottAll rights reserved.

2M.H. Perrott

Bandwidth Constraints for Integer-N Synthesizers

PFD output has a periodicity of 1/T- 1/T = reference frequency

Loop filter must have a bandwidth << 1/T- PFD output pulses must be filtered out and average value

extracted

PFD LoopFilter(1/T = 20 MHz)

ref(t) out(t)

N[k]

Divider

1/T Loop FilterBandwidth << 1/T

Closed loop PLL bandwidth often chosen to be afactor of ten lower than 1/T

3M.H. Perrott

Bandwidth Versus Frequency Resolution

Frequency resolution set by reference frequency (1/T)- Higher resolution achieved by lowering 1/T

PFD LoopFilter

1.80 1.82 GHz

(1/T = 20 MHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]9091

Divider

frequency resolution = 1/T

1/T


4M.H. Perrott

Increasing Resolution in Integer-N Synthesizers

Use a reference divider to achieve lower 1/T- Leads to a low PLL bandwidth ( < 20 kHz here )

PFD LoopFilter

1.80 1.8002 GHz

(1/T = 200 kHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]90009001

Divider


1/T


10020 MHz

5M.H. Perrott

The Issue of Noise

Lower 1/T leads to higher divide value- Increases PFD noise at synthesizer output

PFD LoopFilter

1.80 1.8002 GHz

(1/T = 200 kHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]90009001

Divider


1/T


10020 MHz

6M.H. Perrott

Modeling PFD Noise Multiplication

Influence of PFD noise seen in model from Lecture 16- PFD spectral density multiplied by N2 before influencing PLL

output phase noise

Φvn(t)en(t)

Φout(t)Φc(t)Φn(t)

Φnvco(t)Φnpfd(t)

fo1-G(f)

foG(f)�πNα

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn(f)

-20 dB/dec

Divider Controlof Frequency Setting

(assume noiseless for now)

Sen(f)�πNα

2

Rad

ians

2 /Hz

SΦvn(f)

f(fo)opt0

Rad

ians

2 /Hz SΦnpfd(f)

SΦnvco(f)

f(fo)opt0

High divide values high phase noise at low frequencies

7M.H. Perrott

Outline Of Talk

Dual-loop SynthesizersDirect Digital SynthesizersFractional-N Synthesizers- Traditional Approach- Sigma-Delta Concepts- Synthesizer Noise Analysis

8M.H. Perrott

Dual-Loop Frequency Synthesizer

Overall synthesizer output

From trigonometry: cos(A-B) = cosAcosB+sinAsinB

out

PFD

N

LoopFilter

DividerVCO

ref1

PFD LoopFilter

DividerVCO

ref2

cos(w1t)sin(w1t)

sin(w2t)cos(w2t)

M

Single-sidebandMixer

9M.H. Perrott

Choose top synthesizer to provide coarse tuning and bottom synthesizer to provide fine tuning- Choose w1 to be high in frequency

Set ref1 to be high to avoid large N low resolution- Choose w2 to be low in frequency

Allows ref2 to be low without large M high resolution

Advantage #1: Avoids Large Divide Values

out

PFD

N

LoopFilter

DividerVCO

ref1

PFD LoopFilter

DividerVCO

ref2

cos(w1t)sin(w1t)

sin(w2t)cos(w2t)

M


10M.H. Perrott

Advantage #2: Provides Suppression of VCO Noise

Top VCO has much more phase noise than bottom VCO due to its much higher operating frequency- Suppress top VCO noise by choosing a high PLL

bandwidth for top synthesizerHigh PLL bandwidth possible since ref1 is high

out

PFD

N

LoopFilter

DividerVCO

ref1

PFD LoopFilter

DividerVCO

ref2

cos(w1t)sin(w1t)

sin(w2t)cos(w2t)

M


11M.H. Perrott

Alternate Dual-Loop Architecture

Calculation of output frequency

PFD

N

LoopFilter

DividerVCO

ref1

PFD

M

LoopFilter

DividerVCO

ref2

cos(w1t)sin(w1t)

sin(w2t)cos(w2t)

out


y

12M.H. Perrott

Advantage of Alternate Dual-Loop Architecture

Issue: a practical single-sideband mixer implementation will produce a spur at frequency w1 + w2PLL bandwidth of top synthesizer can be chosen low enough to suppress the single-sideband spur- Negative: lower suppression of top VCO noise

PFD

N

LoopFilter

DividerVCO

ref1

PFD

M

LoopFilter

DividerVCO

ref2

cos(w1t)sin(w1t)

sin(w2t)cos(w2t)

out


y

13M.H. Perrott

Direct Digital Synthesis (DDS)

Encode sine-wave values in a ROMCreate sine-wave output by indexing through ROM and feeding its output to a DAC and lowpass filter- Speed at which you index through ROM sets frequency

of output sine-waveSpeed of indexing is set by increment value on counter (which is easily adjustable in a digital manner)

Counter ROM DAC LPF

clk

out

14M.H. Perrott

Pros and Cons of Direct Digital Synthesis

Advantages- Very fast adjustment of frequency- Very high resolution can be achieved- Highly digital approach

Disadvantages- Difficult to achieve high frequencies- Difficult to achieve low noise- Power hungry and complex

Counter ROM DAC LPF

clk

out

15M.H. Perrott

Hybrid Approach

Use DDS to create a finely adjustable reference frequencyUse integer-N synthesizer to multiply the DDS output frequency to much higher valuesIssues- Noise of DDS is multiplied by N2

- Complex and power hungry

outCounter ROM DAC LPF

clk

PFD LoopFilter

DividerVCO

ref

N

16M.H. Perrott

Fractional-N Frequency Synthesizers

Break constraint that divide value be integer- Dither divide value dynamically to achieve fractional values- Frequency resolution is now arbitrary regardless of 1/T

Want high 1/T to allow a high PLL bandwidth

DitheringModulator

PFD LoopFilter

1.80 1.82 GHz

(1/T = 20 MHz)ref(t) out(t)

out(t)

Sout(f)

N[k]Nsd[k]

Nsd[k]90

90

91

91Divider

frequency resolution << 1/T

1/T

17M.H. Perrott

Classical Fractional-N Synthesizer Architecture

Use an accumulator to perform dithering operation- Fractional input value fed into accumulator- Carry out bit of accumulator fed into divider

1-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

Nsd[k] = N + frac[k]

18M.H. Perrott

Accumulator Operation

Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value- Accumulator residue increments by input fractional

value each clock cycle

residue[k]

carry_out[k]

frac[k] =.25

1-bitM-bit

M-bitfrac[k]

Accumulatorcarry_out[k]

residue[k]

clk(t)

19M.H. Perrott

Fractional-N Synthesizer Signals with N = 4.25

Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to

accumulate- Reset phase error by “swallowing” a VCO cycle

Achieved by dividing by 5 every 4 reference cycles

phase error(t)

carry_out(t)

out(t)

div(t)

ref(t)

e(t)

20M.H. Perrott

The Issue of Spurious Tones

PFD error is periodic- Note that actual PFD waveform is series of pulses – the

sawtooth waveform represents pulse width values over timePeriodic error signal creates spurious tones in synthesizer output- Ruins noise performance of synthesizer

1-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

Nsd[k] = N + frac[k]

21M.H. Perrott

The Phase Interpolation Technique

Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator- Cancel out phase error based on accumulator residue

1-bitM-bit

M-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

D/A

residue[k]

α

22M.H. Perrott

The Problem With Phase Interpolation

Gain matching between PFD error and scaled D/A output must be extremely precise- Any mismatch will lead to spurious tones at PLL output

1-bitM-bit

M-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

D/A

residue[k]

α

Is There a Better Way?

24M.H. Perrott

A Better Dithering Method: Sigma-Delta Modulation

Sigma-Delta dithers in a manner such that resulting quantization noise is “shaped” to high frequencies

M-bit Input 1-bitD/A

Analog Output

Input

QuantizationNoise

Digital InputSpectrum

Analog OutputSpectrum

Time Domain

Frequency Domain

Σ−Δ

Digital Σ−ΔModulator

25M.H. Perrott

Linearized Model of Sigma-Delta Modulator

Composed of two transfer functions relating input and noise to output- Signal transfer function (STF)

Filters input (generally undesirable)- Noise transfer function (NTF)

Filters (i.e., shapes) noise that is assumed to be white

x[k] y[k] y[k]x[k]q[k]

r[k]

z=ej2πfT

z=ej2πfT

NTF

STF

Σ−Δ

Hn(z)

Hs(z)

1

Sr(ej2πfT)= 112

Sq(ej2πfT)= |Hn(ej2πfT)|2112

26M.H. Perrott

Example: Cutler Sigma-Delta Topology

Output is quantized in a multi-level fashionError signal, e[k], represents the quantization errorFiltered version of quantization error is fed back to input- H(z) is typically a highpass filter whose first tap value is 1

i.e., H(z) = 1 + a1z-1 + a2 z-2 L

- H(z) – 1 therefore has a first tap value of 0Feedback needs to have delay to be realizable

x[k] u[k]

e[k]

y[k]

H(z) - 1

27M.H. Perrott

Linearized Model of Cutler Topology

Represent quantizer block as a summing junction in which r[k] represents quantization error- Note:

It is assumed that r[k] has statistics similar to white noise- This is a key assumption for modeling – often not true!

x[k] u[k]

e[k]

y[k]

H(z) - 1

x[k] u[k]r[k]

e[k]

y[k]

H(z) - 1

28M.H. Perrott

Calculation of Signal and Noise Transfer Functions

Calculate using Z-transform of signals in linearizedmodel

- NTF: Hn(z) = H(z)- STF: Hs(z) = 1

x[k] u[k]

e[k]

y[k]

H(z) - 1

x[k] u[k]r[k]

e[k]

y[k]

H(z) - 1

29M.H. Perrott

A Common Choice for H(z)

m = 1

m = 2

m = 3

Mag

nitu

de

0Frequency (Hz)

1/(2T)

8

7

6

5

4

3

2

1

0

30M.H. Perrott

Example: First Order Sigma-Delta Modulator

Choose NTF to be

Plot of output in time and frequency domains with input of

00

Am

plitu

de

Mag

nitu

de (d

B)

Sample Number 200 0

1

Frequency (Hz) 1/(2T)

x[k] u[k]

e[k]

y[k]

H(z) - 1

31M.H. Perrott

Example: Second Order Sigma-Delta Modulator

Choose NTF to be


x[k] u[k]

e[k]

y[k]

H(z) - 1

Mag

nitu

de (d

B)

0 Sample Number 200 0-1

Am

plitu

de

2

1

0

Frequency (Hz) 1/(2T)

32M.H. Perrott

Example: Third Order Sigma-Delta Modulator

Choose NTF to be


x[k] u[k]

e[k]

y[k]

H(z) - 1

Mag

nitu

de (d

B)

0 0Sample Number 200

Am

plitu

de

4

3

2

1

0

-1

-2

-3Frequency (Hz) 1/(2T)

33M.H. Perrott

Observations

Low order Sigma-Delta modulators do not appear to produce “shaped” noise very well- Reason: low order feedback does not properly

“scramble” relationship between input and quantization noise

Quantization noise, r[k], fails to be whiteHigher order Sigma-Delta modulators provide much better noise shaping with fewer spurs- Reason: higher order feedback filter provides a much

more complex interaction between input and quantization noise

34M.H. Perrott

Warning: Higher Order Modulators May Still Have Tones

Quantization noise, r[k], is best whitened when a “sufficiently exciting” input is applied to the modulator- Varying input and high order helps to “scramble”

interaction between input and quantization noiseWorst input for tone generation are DC signals that are rational with a low valued denominator- Examples (third order modulator):

Mag

nitu

de (d

B)

0 Frequency (Hz) 1/(2T)

Mag

nitu

de (d

B)

0 Frequency (Hz) 1/(2T)

x[k] = 0.1 x[k] = 0.1 + 1/1024

35M.H. Perrott

Fractional Spurs Can Be Theoretically Eliminated

See:- M. Kozak, I. Kale, “Rigorous Analysis of Delta-Sigma

Modulators for Fractional-N PLL Frequency Synthesis”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp. 1148-1162, June 2004

- S. Pamarti, I. Galton, "LSB Dithering in MASH Delta–Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779 –790, April 2007.

36M.H. Perrott

Cascaded Sigma-Delta Modulator Topologies

Achieve higher order shaping by cascading low order sections and properly combining their outputsAdvantage over single loop approach- Allows pipelining to be applied to implementation

High speed or low power applications benefitDisadvantages- Relies on precise matching requirements when combining

outputs (not a problem for digital implementations)- Requires multi-bit quantizer (single loop does not)

x[k]

y[k]

q1[k]ΣΔM1[k]

y1[k]

q2[k]ΣΔM2[k]

y2[k]

ΣΔM3[k]

y3[k]

M 1 1

Digital Cancellation LogicMultibitoutput

37M.H. Perrott

MASH topology

Cascade first order sectionsCombine their outputs after they have passed through digital differentiators

x[k]

y[k]

r1[k]ΣΔM1[k]

y1[k]

r2[k]ΣΔM2[k]

y2[k]

u[k]

ΣΔM3[k]

y3[k]

M 1 1

1-z-1 (1-z-1)2

38M.H. Perrott

Calculation of STF and NTF for MASH topology (Step 1)

Individual output signals of each first order modulator

Addition of filtered outputs

x[k]

y[k]

r1[k]ΣΔM1[k]

y1[k]

r2[k]ΣΔM2[k]

y2[k]

u[k]

ΣΔM3[k]

y3[k]

M 1 1

1-z-1 (1-z-1)2

39M.H. Perrott

Calculation of STF and NTF for MASH topology (Step 1)

Overall modulator behavior

- STF: Hs(z) = 1- NTF: Hn(z) = (1 – z-1)3

x[k]

y[k]

r1[k]ΣΔM1[k]

y1[k]

r2[k]ΣΔM2[k]

y2[k]

u[k]

ΣΔM3[k]

y3[k]

M 1 1

1-z-1 (1-z-1)2

40M.H. Perrott

Sigma-Delta Frequency Synthesizers

Use Sigma-Delta modulator rather than accumulator to perform dithering operation- Achieves much better spurious performance than

classical fractional-N approach

PFD ChargePump

Nsd[m]

out(t)e(t)

Σ−ΔModulator

v(t)

N[m]

LoopFilter

DividerVCO

ref(t)

div(t)

MM+1

Fout = M.F Fref

f

Σ−ΔQuantization

Noise

Fref

Riley et. al.,JSSC, May 1993

41M.H. Perrott

Background: The Need for A Better PLL Model

Classical PLL model- Predicts impact of PFD and VCO referred noise sources- Does not allow straightforward modeling of impact due

to divide value variationsThis is a problem when using fractional-N approach

Φdiv[k]

Φref [k] KV

jf

v(t) Φout(t)H(f)

1N

�πα e(t)

Φvn(t)en(t)

Icp

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn(f)

-20 dB/dec

PFDChargePump

LoopFilterDivider

VCO

N[k]

42M.H. Perrott

A PLL Model Accommodating Divide Value Variations

See derivation in Perrott et. al., “A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers …”, JSSC, Aug 2002

Φdiv[k]

Φref[k] KV

jf

v(t) Φout(t)H(f)

1Nnom

2π z-1

z=ej2πfT1 - z-1n[k]

T1

Φd[k]

T2π

e(t)

PFD

Divider

LoopFilterC.P. VCO

α

Tristate: α=1XOR: α=2

Icp

en(t)f

0

SEn(f)

PFD-referredNoise

1/TΦvn(t)

VCO-referredNoise

f0

SΦvn(f)

-20 dB/dec

43M.H. Perrott

Parameterized Version of New Model

Φvn(t)

T G(f)

2π z-1

1 - z-1

n[k]

en(t)

Φout(t)Φc(t)Φd(t)Φn(t)

Φnvco(t)Φnpfd(t)

fo1-G(f)

fo

fo

G(f)�πNnom

z=ej2πfT

α

T�πα

1Ι

espur(t)

Φjit[k]

Ιcpn(t)

G(f)n[k] Φc(t)

jf1Fc(t)

Freq. PhaseD/A and Filter

Alternate Representation

fo

Noise

Dividevalue

variation

f0

SEn(f)

PFD-referredNoise

1/T

VCO-referredNoise

f0

SΦvn(f)

-20 dB/dec

44M.H. Perrott

Spectral Density Calculations

Case (a):

Case (b):

Case (c):

y[k]x[k]H(ej2πfT)

y(t)x[k]H(f)

y(t)x(t)H(f)case (a): CT CT

case (b): DT DT

case (c): DT CT

45M.H. Perrott

Example: Calculate Impact of Ref/Divider Jitter (Step 1)

Assume jitter is white- i.e., each jitter value independent of values at other time

instantsCalculate spectra for discrete-time input and output- Apply case (b) calculation

Δtjit[k]

(Δtjit)rms= β sec.

�π Φjit[k]T

T�πT f

0

SΦjit(ej2πfT)

t

Div(t)

β22

46M.H. Perrott

Compute impact on output phase noise of synthesizer- We now apply case (c) calculation

- Note that G(f) = 1 at DC

Φjit[k]fo

fo

G(f)Nnom

Φn (t)

SΦn(f)

Nnom

f0

2

T

TT1 �π

Tβ2

2

Δtjit[k]

(Δtjit)rms= β sec.

�π Φjit[k]T

T�πT f

0

SΦjit(ej2πfT)

t

Div(t)

β22

Example: Calculate Impact of Ref/Divider Jitter (Step 2)

47M.H. Perrott

Now Consider Impact of Divide Value Variations

Φvn(t)

T G(f)

2π z-1

1 - z-1

n[k]

en(t)

Φout(t)Φc(t)Φd(t)Φn(t)

Φnvco(t)Φnpfd(t)

fo1-G(f)

fo

fo

G(f)�πNnom

z=ej2πfT

α

T�πα

1Ι

espur(t)

Φjit[k]

Ιcpn(t)

G(f)n[k] Φc(t)

jf1Fc(t)

Freq. PhaseD/A and Filter

Alternate Representation

fo

Noise

Dividevalue

variation

f0

SEn(f)

PFD-referredNoise

1/T

VCO-referredNoise

f0

SΦvn(f)

-20 dB/dec

48M.H. Perrott

Divider Impact For Classical Vs Fractional-N Approaches

G(f)n[k] Fout(t)

D/A and Filter

T1n(t)

1/T1

fo

G(f)n[k] Fout(t)

D/A and Filter

T1

1/T1

foDitheringModulator

nsd(t) nsd[k]

Classical Synthesizer

Fractional-N Synthesizer

Note: 1/T block represents sampler (to go from CT to DT)

49M.H. Perrott

Focus on Sigma-Delta Frequency Synthesizer

Divide value can take on fractional values- Virtually arbitrary resolution is possible

PLL dynamics act like lowpass filter to remove much of the quantization noise

G(f)n[k]

n[k]

nsd[k]

nsd[k]

nsd(t) Fout(t)

Fout(t)

D/A and Filter

T1

1/T1

foΣ−Δ

freq=1/T

50M.H. Perrott

Quantifying the Quantization Noise Impact

Calculate by simply attaching Sigma-Delta model- We see that quantization noise is integrated and then

lowpass filtered before impacting PLL output

Φvn(t)

T G(f)

2π z-1

1 - z-1

n[k]nsd[k] Φn[k]

En(t)

Φout(t)Φdiv(t)Φtn,pll(t)

fo1-G(f)

fo

fo

G(f)�πNnom

z=ej2πfT

α

f0 f0

-20 dB/decSEn

(f)

Sq(ej2πfT)

SΦvn(f)

1/T

f0

z=ej2πfT

Σ−Δ

q[k]

r[k]

NTF

STF

Hn(z)

Hs(z)

Sr(ej2πfT)= 112

PFD-referredNoise

VCO-referredNoise

Σ−ΔQuantization

Noise

51M.H. Perrott

A Well Designed Sigma-Delta Synthesizer

Order of G(f) is set to equal to the Sigma-Delta order- Sigma-Delta noise falls at -20 dB/dec above G(f) bandwidth

Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T

10 kHz 100 kHz 1 MHz 10 MHz

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−Δnoise

SΦout,ΔΣ(f)

fo = 84 kHz

52M.H. Perrott

Impact of Increased PLL Bandwidth

Allows more PFD noise to pass throughAllows more Sigma-Delta noise to pass throughIncreases suppression of VCO noise

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T


PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−Δnoise

SΦout,ΔΣ(f)

f0 1/T


Frequency

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Spe

ctra

l Den

sity

(dB

c/H

z)

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−Δnoise

SΦout,ΔΣ(f)

fo = 84 kHz fo = 160 kHz

53M.H. Perrott

Impact of Increased Sigma-Delta Order

PFD and VCO noise unaffectedSigma-Delta noise no longer attenuated by G(f) such that a -20 dB/dec slope is achieved above its bandwidth

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T


PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−Δnoise

SΦout,ΔΣ(f)

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Spe

ctra

l Den

sity

(dB

c/H

z)f0 1/T


PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−Δnoise

SΦout,ΔΣ(f)

Frequency

m = 2 m = 3

54M.H. Perrott

Summary of Advanced Analog Synthesizers

Integer-N synthesizers have limited resolution for a given PLL bandwidthAdvanced synthesizers improve the achievable resolution for a given bandwidth- Dual-loop synthesizers leverage two synthesizers and

an I/Q mixer- Direct digital synthesizers use a lookup table and digital

logic- Fractional-N synthesizers leverage Sigma-Delta

modulationSimpler structure than the other approachesPrimary issue is introduction of Sigma-Delta quantization noise

Clock And Data Recovery

56M.H. Perrott

High Speed Data Links

A challenging component is the clock and data recovery circuit (CDR)- Two primary functions

Extract the clock corresponding to the input data signalResample the input data

Zin

Zo AmpFrom Broadband

Transmitter

PC boardtrace

PackageInterface

In Clock andData

Recovery

Data

Clk

LoopFilter

PhaseDetector

Data Out

Data In Clk Out

VCO

57M.H. Perrott

Outline of Talk

Clock and Data Recovery circuits- Jitter specifications- Phase detection- Modeling- Data dependent jitter- Bang-bang systems

Delay locked loops- Implementation- The issue of infinite delay

58M.H. Perrott

PLL Based Clock and Data Recovery

Use a phase locked loop to tune the frequency and phase of a VCO to match that of the input dataPerformance issues- Jitter- Acquisition time- Bit error rate (at given input levels)

Let’s focus on specifications for OC-192- i.e., 10 Gbit/s SONET

PD ChargePump

clk(t)e(t) v(t)LoopFilter

VCO

retimeddata(t)

data(t)

59M.H. Perrott

Jitter Generation

Definition- The amount of jitter at the output of the CDR when no

jitter (i.e., negligible jitter) is present on the data inputSONET requires- < 10 mUI rms jitter- < 100 mUI peak-to-peak jitter

Note: UI is unit interval, and is defined as the period of the clk signal (i.e., 100 ps for 10 Gbit/s data rates)

PD ChargePump


VCO

retimeddata(t)

data(t)

60M.H. Perrott

Jitter Tolerance

Definition- The maximum amount of jitter allowed on the input while

still achieving low bit error rates (< 10e-12)SONET specifies jitter tolerance according to the frequency of the jitter- Low frequency jitter can be large since it is tracked by PLL- High frequency jitter (above the PLL bandwidth) cannot be

as high (PLL can’t track it out)Limited by setup and hold times of PD retiming register

PD ChargePump


VCO

retimeddata(t)

data(t)

61M.H. Perrott

Example Jitter Tolerance Mask

CDR tested for tolerance compliance by adding sine wave jitter at various frequencies (with amplitude greater than mask) to the data input and observing bit error rate

Jitter Frequency (Hz)

Jitte

r Tol

eran

ce U

.I.

OC-192 Jitter Tolerance Mask

24 kHz 4 MHz 100 MHz

0.15 UI

1.5 UI

15 UI

400 kHz2.4 kHz

AcceptableRegion

62M.H. Perrott

Jitter Transfer

Definition- The amount of jitter attenuation that the CDR provides

from input to outputSONET specifies jitter transfer by placing limits on its transfer function behavior from input to output- Peaking behavior: low frequency portion of CDR transfer

function must be less than 0.1 dB- Attenuation behavior: high frequency portion of CDR

transfer function must not exceed a mask limit

PD ChargePump


VCO

retimeddata(t)

data(t)

63M.H. Perrott

Example Jitter Transfer Mask

CDR tested for compliance by adding sine wave jitter at various frequencies and observing the resulting jitter at the CDR output

-35

-30

-25

-20

-15

-10

-5

0.1

Frequency (Hz)

Mag

nitu

de (d

B)

100 kHz 8 MHz 100 MHz1 MHz10 kHz

AcceptableRegion

OC-192 Jitter Transfer Mask

Maximum Allowed "Peaking" = 0.1 dB

64M.H. Perrott

Summary of CDR Performance Specifications

Jitter- Jitter generation- Jitter tolerance- Jitter transfer (and peaking)

Acquisition time- Must be less than 10 ms for many SONET systems

Bit error rates- Must be less than 1e-12 for many SONET systems

65M.H. Perrott

Phase Detectors in Clock and Data Recovery Circuits

Key issue- Must accommodate “missing” transition edges in input

data sequenceTwo styles of detection- Linear – PLL can analyzed in a similar manner as

frequency synthesizers- Nonlinear – PLL operates as a bang-bang control

system (hard to rigorously analyze in many cases)

PD ChargePump


VCO

retimeddata(t)

data(t)

66M.H. Perrott

Popular CDR Phase Detectors

Linear- Hogge detector produces an error signal that is

proportional to the instantaneous phase errorNonlinear- Alexander (Bang-bang) detector produces an error signal

that corresponds to the sign of the instantaneous phase error

D Q D Q

clk(t)

data(t)retimeddata(t)

Reg Latch

e(t)

D Q D Q

Reg Latch

D Q D Q

clk(t) e(t)

data(t)retimeddata(t)Reg Reg

clk(t)

Hogge Detector (Linear) Bang-Bang Detector (Nonlinear)

67M.H. Perrott

A Closer Look at the Hogge Detector

Error output, e(t), consists of two pulses with opposite polarity- Positive polarity pulse has an area that is proportional

to the phase error between the data and clk- Negative polarity pulse has a fixed area corresponding to half of the clk period- Overall area is zero when data edge is aligned to falling clk edge

clk(t)data(t)

retimed data(t)

e(t)

A

A(t)B

B(t)

C

C(t)

1

-10

D Q D Q

clk(t)


Reg Latch

e(t)

Hogge Detector (Linear)

68M.H. Perrott

Example CDR Settling Characteristic with Hogge PD

CDR tracks out phase error with an exponential transition responseJitter occuring at steady state is due to VCO and non-idealities of phase detector

Inst

anta

neou

s P

hase

Err

or (U

I)0.6

0.5

0.4

0.3

0.2

0.1

0

36322824201612840-0.1

Instantaneous Phase Error vs Time for CDR 1 (Hogge Detector)(Steady-State RMS Jitter = 3.0756 mUI)

69M.H. Perrott

Modeling of CDR with Hogge Detector

Similar to frequency synthesizer model except- No divider- Phase detector gain depends on the transition density

of the input dataThe issue of transition density- Phase error information of the input data signal is only

seen when it transitionsVCO can wander in the absence of transitions

- Open loop gain (and therefore the closed loop bandwidth) is decreased at low transition densities

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter

α = transition density0 < α < 1, = 1/2for PRBS input

v(t)i(t)

70M.H. Perrott

A Common Loop Filter Implementation

Use a lead/lag filter to implement a type II loop- Integrator in H(s) forces the steady-state phase error to

zero (important to minimize jitter)

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter


sCtot(1+s/wp)1+s/wz

v(t)

C1C2

R1

i(t)

1s(C1+C2)

=1+sR1C2

1+sR1C||

C|| =C1C2

C1+C2

=

v(t)i(t)

H(s)

71M.H. Perrott

Open Loop Response and Closed Loop Pole/Zeros

Key issue: an undesired pole/zero pair occurs due to stabilizing zero in the lead/lag filter

Non-dominantpole

Dominantpole pair

Open loopgain

increased

120o

-180o

-140o

-160o

20log|A(f)|

ffz

0 dB

PM = 55o for CPM = 53o for APM = 54o for B

angle(A(f))

A

A

A

A

B

B

B

B

C

C

C

C

Evaluation ofPhase Margin

Closed Loop PoleLocations of G(f)

fp

Re{s}

Im{s}

0

72M.H. Perrott

Corresponding Closed Loop Frequency Response

Undesired pole/zero pair causes peaking in the closed loop frequency responseSONET demands that peaking must be less than 0.1 dB- For classical lead/lag filter approach, this must be achieved

by having a very low-valued zeroRequires a large loop filter capacitor

wwowz

wzwcp

|G(w)| Peaking caused byundesired pole/zero pair

0

1

Frequency (rad/s)

73M.H. Perrott

An Interesting Observation

Calculation of closed loop transfer function

Key observation- Zeros in feedback loop do not appear as zeros in the

overall closed loop transfer function!

NA(s)X(s)DA(s)

Y(s)

NB(s)DB(s)

74M.H. Perrott

Method of Achieving Zero Peaking

We can implement a stabilizing zero in the PLL feedback path by using a variable delay element- Loop filter can now be implemented as a simple integrator

Issue: delay must support a large rangeSee T.H. Lee and J.F. Bulzacchelli, “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop”, JSSC, Dec 1992

PD ChargePump


VCO

retimeddata(t)

data(t)

AdjustableDelay Element

75M.H. Perrott

Model of CDR with Delay Element

Delay “gain”, Kd, is set by delay implementationNote that H(s) can be implemented as a simple capacitor- H(s) = 1/(sC)

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter


v(t)i(t)

Kd

Note: Kd unitsare radians/V

Note: Kv unitsare Hz/V

76M.H. Perrott

Derivation of Zero Produced by Delay Element

Zero set by ratio of delay gain to VCO gain

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter


v(t)i(t)

Kd

KvΦout(t)

s2π

VCO

H(s)

LoopFilter

v(t)i(t)

KdKv

s2π

KvΦout(t)

s2π

VCO

H(s)

LoopFilter

v(t)i(t)

KdKv

s2π1+

Note: Kd unitsare radians/V

Note: Kv unitsare Hz/V

77M.H. Perrott

Alternate Implementation

Can delay data rather than clk- Same analysis as before

PD ChargePump


VCO

retimeddata(t)

data(t)

-1


78M.H. Perrott

The Issue of Data Dependent Jitter

For classical or Bulzacchelli CDR- Type II PLL dynamics are employed so that steady state

phase detector error is zeroIssue: phase detector output influences VCO phase through a double integrator operation- The classical Hogge detector ends up creating data

dependent jitter at the VCO output

PD ChargePump


VCO

retimeddata(t)

data(t)

Φclk(t)

79M.H. Perrott

Culprit Behind Data Dependent Jitter for Hogge PD

The double integral of the e(t) pulse sequence is nonzero (i.e., has DC content)- Since the data transition activity is random, a low

frequency noise source is createdLow frequency noise not attenuated by PLL dynamics

A

B C

D Q D Q

clk(t)


Reg Latch

e(t)

clk(t)

data(t)

retimed data(t)

e(t)

A(t)

B(t)

C(t)

1

-10


e(t) 0

80M.H. Perrott

One Possible Fix

Modify Hogge so that the double integral of the e(t) pulse sequence is zero- Low frequency noise is now removed

See L. Devito et. al., “A 52 MHz and 155 MHz Clock-recovery PLL”, ISSCC, Feb, 1991

clk(t)

data(t)

retimed data(t)

e(t)

A

A(t)

B B(t)CC(t)

1

-2

0

clk(t)


D Q

Reg

e(t)

D Q

Latch


D(t)

e(t) 0

Latch

D Q

D2

81M.H. Perrott

A Closer Look at the Bang-Bang Detector

Error output consists of pulses of fixed area that are either positive or negative depending on phase errorPulses occur at data edges- Data edges detected when sampled data sequence is

different than its previous valueAbove example illustrates the impact of having the data edge lagging the clock edge

clk(t)data(t)

retimed data(t)

e(t)

A(t)

B(t)

C(t)

1

-10

D Q D Q

Reg Latch

D Q D Q

clk(t) e(t)


clk(t)

Bang-Bang Detector (Nonlinear)

A

B

C

D D(t)

82M.H. Perrott

A Closer Look at the Bang-Bang Detector (continued)

Above example illustrates the impact of having the data edge leading the clk edge- Error pulses have opposite sign from lagging edge case

clk(t)data(t)

retimed data(t)

e(t)

A(t)

B(t)

C(t)

1

-10

D Q D Q

Reg Latch

D Q D Q

clk(t) e(t)


clk(t)

Bang-Bang Detector (Nonlinear)

A

B

C

D D(t)

83M.H. Perrott

Example CDR Settling Characteristic with Bang-Bang PD

Bang-bang CDR response is slew rate limited- Much faster than linear CDR, in general

Steady-state jitter often dominated by bang-bang behavior (jitter set by error step size and limit cycles)

Inst

anta

neou

s P

hase

Err

or (U

I)0.05

0

-0.05

-0.1

-0.15

-0.220181614121086420

Time (Micro Seconds)

Instantaneous Phase Error vs Time for CDR 2 (Bang-Bang Detector)(Steady-State RMS Jitter = 3.4598 mUI)

84M.H. Perrott

The Issue of Limit Cycles

Bang-bang loops exhibit limit cycles during steady-state operation- Above diagram shows resulting waveforms when data

transitions on every cycle- Signal patterns more complicated for data that randomly

transitionsFor lowest jitter: want to minimize period of limit cycles

clk(t)e(t) v(t)

VCO

data(t)Sense Drive

Φclk(t)Bang-Bang Style Phase Detector

Φclk(t)

e(t)

v(t)

85M.H. Perrott

The Impact of Delays in a Bang-Bang Loop

Delays increase the period of limit cycles, thereby increasing jitter

clk(t)e(t) v(t)

VCO

data(t)Sense DriveDelay

Φclk(t)Bang-Bang Style Phase Detector

Φclk(t)

e(t)

v(t)

Φclk(t)

e(t)

v(t)

86M.H. Perrott

Practical Implementation Issues for Bang-Bang Loops

Minimize limit cycle periods- Use phase detector with minimal delay to error output- Implement a high bandwidth feedforward path in loop

filterOne possibility is to realize feedforward path in VCO

See B. Lai and R.C Walker, “A Monolithic 622 Mb/s Clock Extraction Data Retiming Circuit”, ISSCC, Feb 1991

Avoid dead zones in phase detector- Cause VCO phase to wonder within the dead zone,

thereby increasing jitterUse simulation to examine system behavior- Nonlinear dynamics can be non-intuitive- For first order analysis, see R.C. Walter et. al., “A Two-

Chip 1.5-GBd Serial Link Interface”, JSSC, Dec 1992

87M.H. Perrott

Recall the CDR Model (Hogge Det.) From Lecture 21

Similar to frequency synthesizer model except- No divider- Phase detector gain depends on the transition density

of the input data

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter


v(t)i(t)

88M.H. Perrott

Key Observation: Must Use a Type II Implementation

Integrator in H(s) forces the steady-state phase error to zero- Important to achieve aligned clock and to minimize jitter

1πα Kv

Φout(t)Φdata(t)

s2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter


sCtot(1+s/wp)1+s/wz

v(t)

C1C2

R1

i(t)

1s(C1+C2)

=1+sR1C2

1+sR1C||

C|| =C1C2

C1+C2

=

v(t)i(t)

H(s)

89M.H. Perrott

Issue: Type II System Harder to Design than Type I

A stabilizing zero is requiredUndesired closed loop pole/zero doublet causes peaking

Non-dominantpole

Dominantpole pair

Open loopgain

increased

120o

-180o

-140o

-160o

20log|A(f)|

ffz

0 dB

PM = 55o for CPM = 53o for APM = 54o for B

angle(A(f))

A

A

A

A

B

B

B

B

C

C

C

C



fp

Re{s}

Im{s}

0

90M.H. Perrott

Delay Locked Loops

Delay element used in place of a VCO- No integration from voltage input to phase output- System is Type 1

1

πα Kv

Φout(t)Φdata(t)

s

2π

Hogge Detector

PhaseSampler VCO

e(t)H(s)Icp

ChargePump

LoopFilter

α = transition density0 < α < 1,

= 1/2 for PRBS input

v(t)i(t)

1

πα Kv

Φout(t)Φdata(t)

2π

Hogge Detector

PhaseSampler

e(t)H(s)Icp

ChargePump

LoopFilter

α = transition density0 < α < 1,

= 1/2 for PRBS input

v(t)i(t)

Voltage-ControlledDelay

Element

91M.H. Perrott

System Design Is Easier Than For CDR

-90o

-315o

-165o

-180o

-240o

20log|A(f)|

ffp3

\A(f)

Open loopgain

increased

0 dB

PM = 51o for B

PM = -12o for C

PM = 72o for A

Non-dominantpoles

Dominantpole pair

ABC

B

A

A

B

C

C



fp fp2

Re(s)

Im(s)

0

No stabilizing zero required- No peaking in closed loop frequency response

92M.H. Perrott

Example Delay-Locked Loop Implementation

Assume an input clock is provided that is perfectly matched in frequency to data sequence- However, phase must be adjusted to compensate for

propagation delays between clock and data on the PC boardA variable delay element is used to lock phase to appropriate value- Phase detector can be similar to that used in a CDR

Hogge, Bang-Bang, or other structures possible

PD ChargePump

e(t) v(t)LoopFilter

retimeddata(t)

data(t)


clk(t)

Clock and Dataarrive misaligned

in phase

Clock and Dataare now re-aligned

in phase

adjustedclk(t)

93M.H. Perrott

The Catch

Delay needs to support an infinite range if system to be operated continuously- Can otherwise end up at the end of range of delay element

Won’t be able to accommodate temperature variationsMethods have been developed to achieve infinite range delay elements- Efficient implementation of such delay elements is often the

key issue for high performance designs

PD ChargePump

e(t) v(t)LoopFilter

retimeddata(t)

data(t)


clk(t)


in phase


in phase

adjustedclk(t)

94M.H. Perrott

The Myth

Delay locked loop designers always point to jitter accumulation problem of phase locked loops- Implication is that delay locked loops can achieve much lower

jitter than clock and data recovery circuitsThe reality: phase locked loops can actually achieve lower jitter than delay locked loops- PLL’s can clean up high frequency jitter of input clock- Whether a PLL or DLL is better depends on application (and

achievable VCO performance)

PD ChargePump

e(t) v(t)LoopFilter

retimeddata(t)

data(t)


clk(t)


in phase


in phase

adjustedclk(t)

95M.H. Perrott

One Method of Achieving Infinite Delay

I

Q

φ

cos(2πfint)

cos(2πfint+φ)

cos(2πfint+φ) = cos(2πfint)cos(φ) - sin(2πfint)sin(φ)

Phase shift of a sine wave can be implemented with I/Q modulation

Note: infinite delay range allows DLL to be used to adjust frequency as well as phase- Phase adjustment now must vary continuously- Hard to get low jitter in practical implementations

96M.H. Perrott

Conceptual Implementation of Infinite Delay Range

Practical designs often implement cos(Φ) and sin(Φ) signals as phase shifted triangle waves

I

Q

φ

φcos(2πfint+φ)

cos(2πfint)cos(2πfint)

sin(φ)

iin(t)

qin(t)90

o

cos(φ)φ

cos(2πfint)

cos(2πfint+φ)

cos(2πfint+φ)

cos(2πfint)

cos(2πfint+φ) = cos(2πfint)cos(φ) - sin(2πfint)sin(φ)

97M.H. Perrott

Some References on CDR’s and Delay-Locked Loops

Tom Lee et. al. were pioneers of the previous infinite range DLL approach- See T. Lee et. al., “A 2.5 V CMOS Delay-Locked Loop for an

18 Mbit, 500 Megabyte/s DRAM”, JSSC, Dec 1994Check out papers from Mark Horowitz’s group at Stanford- Oversampling data recovery approach

See C-K K. Yang et. al., “A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery using Oversampling”, JSSC, May 1998

- Multi-level signalingSee Ramin Farjad-Rad et. al., “A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver”, JSSC, May 2000

- Bi-directional signalingSee E. Yeung, “A 2.4 Gb/s/pin simultaneous bidirectional

parallel link …”, JSSC, Nov 2000

98M.H. Perrott

Summary

Clock and data recovery circuits generate a clock that is phase and frequency aligned to an incoming data signal- Jitter characteristics are one of the key performance

metrics- Implementations are either linear or bang-bang

Linear is needed for well-defined jitter transfer functionBang-bang has simpler implementation

Delay locked loops phase align an existing clock to an incoming data stream- Potentially simpler implementation than CDR

advanced analog frequency synthesizers, clock and data ... · m.h. perrott 2 bandwidth constraints...

Documents