advanced digital logic design – eecs 303 - robert...
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Advanced Digital Logic Design – EECS 303
http://ziyang.eecs.northwestern.edu/eecs303/
Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298
AdministrationOverview of course
HomeworkMisc.
Outline
1. Administration
2. Overview of course
3. Homework
4. Misc.
2 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Today’s goals
1 Know how to get access to the resources you’ll need for thiscourse
Books, computer lab, website, newsgroup
2 Understand work and grading policies
3 Have a rough understanding of the topics we will cover4 Have a rough understanding of an example design
You’ll soon be designing similar systems on your own
3 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Administration
Lecture notes handed out before class
PDF files posted after lectures
http://ziyang.eecs.northwestern.edu/∼dickrp/eecs303/
If something isn’t clear and you ask about it in class, I’llsometimes add more detail to the slides before posting
4 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Class prerequisites
ECE 203: Introduction to Computer Engineering
Need to have basic understanding of digital systems, logic gates,combinational logic, and sequential logic
Need Unix experience (or need to catch up) since we will use theMentor Graphics tools on Sun workstations
Expect you to familiarize yourself with the basics of using this OSon your own but will give some hints
Use search engine, e.g., google: “unix beginners”http://www.ee.surrey.ac.uk/Teaching/Unix/ not a bad place tostart
5 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Class foundation for
EECS 347: Microprocessor System Projects
EECS 357: Introduction to VLSI CAD
EECS 361: Computer Architecture
EECS 362: Computer Architecture Projects
EECS 391: Introduction to VLSI Design
EECS 392: VLSI Design Projects
EECS 393: Design and Analysis of High-Speed Integrated Circuits
6 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Required book
M. Morris Mano and Charles R. Kime. Logic and ComputerDesign Fundamentals. Prentice-Hall, NJ, fourth edition, 2008
7 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Reference books
Allen Dewey. Analysis and Design of Digital Systems WithVHDL. PWS Publishing Company, International ThompsonPublishing, 1997
Zvi Kohavi. Switching and Finite Automata Theory. McGraw-HillBook Company, NY, 1978
A. V. Aho, R. Sethi, and J. D. Ullman. Compilers principles,techniques, and tools. Addison-Wesley, MA, 1986
Randy H. Katz. Contemporary Logic Design. TheBenjamin/Cummings Publishing Company, Inc., 1994
8 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Grading policies
Homeworks: 25% of gradeLabs: 25% of gradeMidterm exam: 20% of gradeFinal exam: 30% of grade
Homeworks and labs due at beginning of class on due date
5% penalty for handing after start of class but still on due date
10% penalty per late working day
No credit if more than three working days late
9 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Grading style
Homeworks and some labs will be graded quite strictly
Learn from the feedbackSee the TA or me if something doesn’t make senseDon’t assume a 75% grade on the homework implies a C in thecourse – it doesn’t
Will cover a limited amount material in lectures that does notappear in the course textbook
However, you’ll have access to the full set of lecture notes
I will do my best not to make exams surprising
However, they won’t be easy and the best students in the classprobably won’t get 100% on the exams
10 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Lab assignments
Tried to make lab assignments get to the point w.o. wasting time
In this area, lab assignments necessarily require some time
May take you much longer than some other students if you needto refresh your memory or fill in gaps in your background
You probably will not be able to finish labs on time if you startthem the day before they’re due
11 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Lab assignments
Tried to make lab assignments get to the point w.o. wasting time
In this area, lab assignments necessarily require some time
May take you much longer than some other students if you needto refresh your memory or fill in gaps in your background
You probably will not be able to finish labs on time if you startthem the day before they’re due
11 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Lab work
Computer aided-design (CAD) software from Mentor Graphics
Sun workstations in the Wilkinson Lab (M338 Tech)
Lab Hours: Open
Topics
Tutorial on Mentor Graphics (simple logic)Design of combinational logicDesign of sequential logicUse of VHDL for combinational and sequential design
12 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Decide office hours
We can reschedule office hours based on your comments
Person Day Time RoomRobert Dick Tuesday 5:00–6:00 L477 TechRobert Dick Thursday 5:00–6:00 L477 Tech
We’ll go to the Wilkinson Lab (M338 Tech) when requested.
13 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Subscribe to mailing list
Very useful for getting questions rapidly answered
If you email an academic question to the TA or me, we will postthe question and the answer to the newsgroup/mailing list butremove your name
Send mail to “[email protected]”
No subject
Body of SUBSCRIBE ADLD [Firstname] [Lastname]
Send mail to “[email protected]” to post
I will archive posts and make them available via the course webpage
14 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Outline
1. Administration
2. Overview of course
3. Homework
4. Misc.
15 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Section outline
2. Overview of courseTopicsGoalsOverview and reviewCase study
16 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course topics in context I
1 Boolean algebra (brief review)
Formulating problems as Boolean expressionsCan use to solve problems in many fields of engineering
2 Karnaugh maps (brief review)
Helps visualize problem in which adjacency is important
3 Quine–McCluskey (fairly quick coverage, depending onbackground)
Covering
17 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course topics in context II
4 Heuristic logic minimization
Complexity and algorithms
5 Implementation technologies
Useful starting point for prototyping designsImplementation technologies are constantly changing
6 Graph definitions, critical path, and topological sort
Basic understanding of graph algorithms
7 Number systems, binary arithmetic (more detail, advancedoperations)
Fundamental meaning of mathematical operations
18 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course topics in context III
8 Technology mapping
Covering
9 FSM design, non-deterministic intermediate representations
Compiler, languages, CS theory
10 Incompletely specified FSM state minimization
Covering
11 CAD software
Testing ideas in other fields, e.g., computer architecture
12 Testing (if time permits)
19 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Section outline
2. Overview of courseTopicsGoalsOverview and reviewCase study
20 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course goals I
1 Learn to manually design, optimize, and implement small digitalcombinational circuits.
2 Have a basic understanding of the building blocks andimplementation technologies available to digital designers.
3 Understand how to use schematic capture software to designdigital circuits.
4 Be capable of doing automatic and manual timing analysis ofcombinational circuits.
5 Be capable of using CAD software to automatically optimizelarge digital combinational circuits and map them to a targettechnology.
21 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course goals II
6 Have a high-level understanding of the algorithms such synthesissoftware uses (e.g., logic optimization and technology mapping).This first portion of the course was dedicated to combinationaldesign. I went into depth on a few more advanced topics becauseI wanted you to see some of the beauty of the algorithms used toautomatically design circuits, e.g., my description of portions ofthe Espresso algorithm.
7 Understand how to design, optimize, and implement finite statemachines.
8 Understand that sequential behavior can be specified in differentways and have a reasonably good understanding of how to startfrom a few different types of specifications and end up withworking logic.
22 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Course goals III
9 Understand the differences between synchronous andasynchronous finite state machines and know the advantages ofeach.
10 Be capable of doing simple VHDL designs.
23 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Section outline
2. Overview of courseTopicsGoalsOverview and reviewCase study
24 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Design, implementation, and debugging
time
design
time
implementation
design
time
implementation
debugging
design
time
implementation
debugging
design
time
implementation
debugging
design
Functionality
Constraints: Timing, area, power, price
Formally define abstract blocks
25 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Design, implementation, and debugging
time
design
time
implementation
design
time
implementation
debugging
design
time
implementation
debugging
design
time
implementation
debugging
design
Assemble primitive building blocks into hierarchical system
Choose among design alternatives after impacts explored
25 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Design, implementation, and debugging
time
design
time
implementation
design
time
implementation
debugging
design
time
implementation
debugging
design
time
implementation
debugging
design
Fault isolation: Design flaws, implementation flaws, componentflaws
Hypothesis formation and testing
Good design and implementation make debugging easier
4–5 hours → 12–14 hours
25 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Design, implementation, and debugging
time
design
time
implementation
design
time
implementation
debugging
design
time
implementation
debugging
design
time
implementation
debugging
design
25 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Design, implementation, and debugging
time
design
time
implementation
design
time
implementation
debugging
design
time
implementation
debugging
design
time
implementation
debugging
design
25 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Ambitious goal for synthesis
Start from single system-level description
Automatically build all hardware
Where do we start?
26 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Review: MOSFETs
gate
silicon bulk (P)
drain (N)source (N)
oxide
27 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Relationship with CMOS
Metal Oxide Silicon
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
28 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Relationship with CMOS
Metal Oxide Silicon
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
28 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Relationship with CMOS
Metal Oxide Silicon
Positive and negative carriers
Complimentary MOS
PMOS gates are like normally closed switches that are good attransmitting only true (high) signals
NMOS gates are like normally open switches that are good attransmitting only false (low) signals
28 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
NAND gate
Therefore, NAND and NOR gates are used in CMOS designinstead of AND and OR gates
ba
output
true
false
=
ba
output
true
false
=
NMOS
PMOS
29 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
NAND gate
Therefore, NAND and NOR gates are used in CMOS designinstead of AND and OR gates
ba
output
true
false
=
ba
output
true
false
=
NMOS
PMOS
29 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Floorplanning
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AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Thermal analysis
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-4-2
0 2
4 6
8
-8
-6
-4
-2
0
2
4
6
8
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Temperature (°C)
Position (mm)
Temperature (°C)
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AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
New technologies
Source(S)
Optionalsecond
gate (G2) Drain(D)
(G)Gate
Insulator
Island
Junctions
32 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Review: Boolean algebra
The only values are 0 (or false) and 1 (or true)
One can define operations/functions/gates
Boolean values as input and output
A truth table enumerates output values for all input valuecombinations
33 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
AND
a b a ∧ b
0 0 00 1 01 0 01 1 1
b
a
a AND b = a ∧ b = a b
34 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
OR
a b a + b
0 0 00 1 11 0 11 1 1
a
b
a OR b = a ∨ b = a + b
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AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
NOT
a a
0 11 0
a
NOT a = a
36 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Section outline
2. Overview of courseTopicsGoalsOverview and reviewCase study
37 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study of simple combinational logic design –seven-segment display
Given: A four-bit binary input
Display a decimal digit ranging from zero to nine
Use a seven-segment display
38 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – seven-segment display
i3 i2 i1 i0 dec
0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9
39 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
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i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
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i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
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L4
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i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
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i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
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i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
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L1
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L7
L1
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L7
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L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L5
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L7
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L7
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L7
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L7
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L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L7
L1
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L7
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L7
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L7
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L2
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L7
L1
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L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L5
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L7
L1
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L7
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L7
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L7
L1
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L7
L1
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L7
L1
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L7
L1
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L7
L1
L2
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L7
L1
L2
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L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L4
L5
L6
L7
L1
L2
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L6
L7
L1
L2
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L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
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L4
L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
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L4
L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
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L7
L1
L2
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L6
L7
L1
L2
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L6
L7
L1
L2
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L6
L7
L1
L2
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L5
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L7
L1
L2
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L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L6
L7
L1
L2
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L5
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L7
L1
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L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Case study – Seven-segment
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
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L5
L6
L7
L1
L2
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L7
L1
L2
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L7
L1
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L5
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L7
L1
L2
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L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
L1
L2
L3
L4
L5
L6
L7
i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L70 0 0 0 0 1 0 1 1 1 1 10 0 0 1 1 0 0 0 0 0 1 10 0 1 0 2 1 1 1 0 1 1 00 0 1 1 3 1 1 1 0 0 1 10 1 0 0 4 0 1 0 1 0 1 10 1 0 1 5 1 1 1 1 0 0 10 1 1 0 6 1 1 1 1 1 0 10 1 1 1 7 1 0 0 0 0 1 11 0 0 0 8 1 1 1 1 1 1 11 0 0 1 9 1 1 0 1 0 1 1
40 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Implement L4
i3 i2 i1 i0 dec L40 0 0 0 0 10 0 0 1 1 00 0 1 0 2 00 0 1 1 3 00 1 0 0 4 10 1 0 1 5 10 1 1 0 6 10 1 1 1 7 01 0 0 0 8 11 0 0 1 9 1
41 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
L4 implementation
L4
42 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Combinational vs. sequential logic
No feedback between inputs and outputs – combinational
Outputs a function of the current inputs, only
Feedback – sequential
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
43 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Combinational vs. sequential logic
No feedback between inputs and outputs – combinational
Outputs a function of the current inputs, only
Feedback – sequential
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
43 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Combinational vs. sequential logic
No feedback between inputs and outputs – combinational
Outputs a function of the current inputs, only
Feedback – sequential
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
43 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Sequential logic
Outputs depend on current state and (maybe) current inputs
Next state depends on current state and input
For implementable machines, there are a finite number of states
Synchronous
State changes upon clock event (transition) occurs
Asynchronous
State changes upon inputs change, subject to circuit delays
44 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
What can we do?
Finite state machine design
Logic minimization
Implementation with gates
Need a lot more depth, and a lot more detail!
45 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
What can we do?
Finite state machine design
Logic minimization
Implementation with gates
Need a lot more depth, and a lot more detail!
45 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
What can we do?
Finite state machine design
Logic minimization
Implementation with gates
Need a lot more depth, and a lot more detail!
45 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
What can we do?
Finite state machine design
Logic minimization
Implementation with gates
Need a lot more depth, and a lot more detail!
45 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Ambitious goal for synthesis
Start from single system-level description
Automatically build all hardware
Where do we start?
What are the fundamental barriers?
What new discoveries are necessary?
46 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Conventional synthesis
system level
behavior level
system level
behavior level
register−transfer level
system level
behavior level
register−transfer level
logic level
system level
behavior level
register−transfer level
logic level
layout level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
system level
behavior level
register−transfer level
logic level
layout level
transistor level
layout estimation
behavior estimation
register−transfer est.
logic estimation
transistor estimation
system level
47 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Status and approach
Understand a few combinational logic design techniques
Much left to learn
Have scratched the surface of sequential logic design
Much left to learn
Little knowledge of automation and its fundamental barriers
Approach: Start from the core we learned in EECS 203
Build breadth and depth
48 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
TopicsGoalsOverview and reviewCase study
Combinational design
Let’s start by reviewing combinational design
A lot of amazing stuff will build upon this later
49 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Outline
1. Administration
2. Overview of course
3. Homework
4. Misc.
50 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Get Wilkinson lab account
Confirm that you are registered for the course athttp://courses.northwestern.edu/
The administrators have a list of students.
They will create accounts and add physical access to M334 toyour card.
51 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Introductory reading assignments
In general, reading assignments will cover material that will bepresented in the next class.
It may seem like a lot but most should be review from EECS 203.
Even if you think you remember the material from EECS 203,spend a few minutes with the book to confirm.
M. Morris Mano and Charles R. Kime. Logic and ComputerDesign Fundamentals. Prentice-Hall, NJ, fourth edition, 2008
Chapters 2, 3, and 4
52 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Outline
1. Administration
2. Overview of course
3. Homework
4. Misc.
53 Robert Dick Advanced Digital Logic Design
AdministrationOverview of course
HomeworkMisc.
Computer geek culture
RLE
Compression geek culture: compression = prediction =classification
54 Robert Dick Advanced Digital Logic Design