advanced encryption standard smart card

7/29/2019 advanced encryption standard Smart Card

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Advanced Encryption StandardFor

Smart Card Security

Aiyappan Natarajan David Jasinski

Kesava R.Talupuru Lilian Atieno

Advisor: Prof. Wayne Burleson


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Outline

Motivation

System Architecture

System Interface

Encryption CoreKey Scheduling

Decryption Core

ResultsConclusion

Future work


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Motivation

Security in Smart Cards - Cryptography

Applications

Identification Cards

Credit Cards

Algorithms Used

Rijndael (Advanced Encryption

Standard) DES(Data Encryption Standard)

RSA(Ronald, Samir and Adleman)


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System Architecture

Processor

InputController

Output Controller

Data/Key RegEncryption Core

Key

Scheduling

Decryption Core

External

System

Output data

(From Enc/Dec core)

128

128

128

128

Memory

128


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External

System

Input

Controller

FSM

Processor

FSM

Data/Key

Register

Serial I/O

send

Rdy_in Rdy_Out

rec_data

clk Reset clk

128

Parallel Data

Reset

Mux_en d_k

clk

128

128

Data

Key

Processor Input Controller Interface

PC

instr

2

3


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Processor

FSM

Encryption

Core

clk

128 Key_Out

Resetencrypt

clk

128

128

Input Data

Cipher Text

Processor Encryption Core Interface

PC

instr

2

3

Key

Scheduling

clk


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Processor - Output Controller Interface

Output dataExternal

System

Output

Controller

FSM

Processor

FSM

Serial I/O

clk

128

clkSend_data

Data_rdy

Reset

sentOutput_data

instr PC

2

3


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Key Add Substitution Shift Row Mix Column Key Add

SubstitutionShift RowKey Add

Sub Key

Sub Key

ED

Raw Data

Encryption Algorithm Flow

Sub KeyRepeat (Round-1) times


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Encryption Core

SB SR MCFFARK

FF

sel

cntrl

Plain Text128

CT

clk

clk


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Sub_bytes (SB) Transformation

S S S

8 8 8

8 8 8

S S S

8 8 8

8 8 8

Input

Output


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Add Round key (ARK) Operation

A B C D

E F G H

I J K L

M N O P

A1 B1 C1 D1

E1 F1 G1 H1

I1 J1 K1 L1

M1 N1 O1 P1

A2 B2 C2 D2

E2 F2 G2 H2

I2 J2 K2 L2

M2 N2 O2 P2

=

State Key Output


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BLOCK DIAGRAM FOR MIX COLUMN

8h1b

S0,C

x2 x3 x1

Left shiftby 1 bit

S1,C

x2 x3 x1

S2,C

x2 x3 x1

S3,C

x2 x3 x1

8h1b 8h1b 8h1b

S0,C S2,C S3,CS1,C

XOR

XOR


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30

02010103

03020101

01030201

01010302

'

'

'

'

,3

,2

,1

,0

,3

,2

,1

,0

cfor

S

S

S

S

S

S

S

S

C

C

C

C

C

C

C

C

Mix column() Transformation

- Operates on State column-by-column.

- Each column is treated as a four-term polynomial.

-The four bytes in the four rows are used for matrix

multiplication in GF(28) as shown below.


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S 0,0 S 0,1 S 0,2 S 0,3

S 1,0 S 1,1 S 1,2 S 1,3

S 2,0 S 2,1 S 2,2 S 2,3

S 3,0 S 3,1 S 3,2 S 3,3

S 0,0 S 0,1 S 0,2 S 0,3

S 1,1 S 1,2 S 1,3 S 1,0

S 2,2 S 2,3 S 2,0 S 2,1

S 3,3 S 3,0 S 3,1 S 3,2

no shift

Shift Rows (SR)


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Encryption Simulations Result


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Key Scheduling

486 lines of Verilog code (including 256lines of a lookup table)

Input: 128 bit Key

Output: 1408 bit Expanded Key, sent out asfour 32 bit keys at a time

Process:

Word rotation Look up Tables

XOR operations


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Block Diagram

Key_In

Comb

Logic

W_Out

Mux_select

Mux_select

128

128

128

128

128

clk

clk

128


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Key Add Inv Shift Substitution Key Add Inv Mix

Inv ShiftSubstitutionKey Add

Sub Key

Sub Key

PT

Raw Data

Decryption Algorithm Flow

Sub KeyRepeat (Round-1) times


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Decryption Core

ARK FF ISR

ISB

ARK

IMC

FF

Cipher

Textkey

128

PT

sel clk

clk

128

128


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Decryption Simulation Results


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Processor FSM

Encrypt Key Sched

I/P FSM O/P FSM

Hierarchical Representation of

the whole system

Decryption

SB SR MC AR ISB ISR IMC IAR


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Synthesis with Synopsys

Used a Virginia Tech Academic 0.25 um

library (vtvtlib25.db)

Input:

module.v files

vtvtlib25 library

Output: module_gate.v files

S d l l


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Synopsys at Module Level


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Floorplanning with Silicon Ensemble

Input: module_gate.v files and VirginiaTech LEF files

Output: module.gds2 files

Sizes of 4 main modules:

Interface 760 um X 760 um

Encryption Core 1095 um X 1095 um Decryption Core error in floorplanning

Key Schedule 1800 um X 1800 um

Sili E bl (Pl & R t )


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Silicon Ensemble (Place & Route)

C d Vi t (DRC & E t ti )


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Cadence Virtuoso (DRC & Extraction)


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Conclusions

Hardware Implementation of the Rijndael

algorithm using Verilog HDL

Functional Verification of the code(1800)

with the 384 test vectors for

encryption/decryption

Synthesis of Verilog Code

Area Estimations


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Future Work

Optimize the system to accommodate

different key and data lengths

Delay and Power estimation

Optimize the design in synthesis

Verify using FPGA


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References

Draft of AES - Federal Information Processing

Standards Publication, Washington D.C.

Kuo, Henry and Ingrid Verbauwhede-

Architectural Optimization for a 1.82Gbits/secVLSI implementation of the AES Rijndael

Algorithm

Rankl and W.Effing- Smart Card Handbook,

Second Edition, Chichester, England, John Wiley

& Sons Ltd.,2000

advanced encryption standard smart card

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