Advanced Power Module Packaging for increased Operation Temperature and Power

Density

Peter Beckedahl SEMIKRON International GmbH, Nuremberg, Germany, peter.beckedahl@semikron.com

Abstract — Power Electronics is a key enabling technology for the effective and efficient generation, distribution, and use of electrical energy. In the range of kW to MW, power semiconductor modules play a key role in power electronic systems. While in the past decade the R&D activities mainly concentrated on continuous improvement of materials and production processes, more drastic technology changes are emerging nowadays. This is driven by the urgent need for much higher power densities, for higher reliability and further cost reduction. Also the requirements imposed by wide band gap semiconductors need now seriously to be addressed. Therefore, this paper presents an overview of recent material, process and technology developments which enable such improvements. In particular, the latest innovations in die attach technologies as well as the potential of direct liquid cooling and system integration will be highlighted.

Keywords — Power Module Packaging, High Operation Temperature, Direct Liquid Cooling

I. INTRODUCTION In the last years of booming economy one has seen a

drastic cost increase of raw materials used in the power module industry. Still, power semiconductor dies like IGBT and fast diodes usually represent more than 50% of the power module cost. A logical consequence for future module designs is to further increase the power density of power modules and to get the best utilization of the available die, respective module area.

The maximum power dissipation of the semiconductors is limited by the maximum junction temperature, the coolant temperature and the thermal resistance from chip to cooling medium.

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Since the coolant temperature is given by the application one of the possible ways to increase the power density is to increase the maximum junction temperature. Another possibility is to improve the thermal resistance from chip to ambient.

Either way, the module’s internal and external interconnection interfaces like die top and bottom side contact, DBC substrate to baseplate joint, the thermal grease layer and the heat sink itself are stressed with a higher temperature gradient.

For example, increasing the maximum junction temperature from 150°C to 175°C with a given heat sink temperature of 90°C will lead to about 25% higher output power. In turn the increased temperature swing ΔTj from 60K to 85K will typically reduce the power cycling capability of the power module by a factor of 5.

Therefore, this paper focuses on new packaging technologies to increase the power cycling capability as well as the power density of future power modules.

II. STANDARD MODULE PACKAGING

The power density of silicon power devices has increased significantly over the last years. Fig. 1 shows the schematic cross section of a conventional power module. Power semiconductor chips, having typical sizes between 2 x 2 mm² and 24 x 24 mm², are attached by soft soldering to a DBC substrate. The contact of the power chip top side to the substrate is made by heavy Al-wire wedge bonding. The substrate itself is soft soldered to a base plate. The base plate is then bolted down to a heat sink by screws with a layer of thermally conductive paste (thermal interface material – TIM) to avoid air gaps between module and heat sink.

Fig. 1: Cross section of a traditional power module Today, the maximum junction temperature for

rectifiers and thyristors is 130 °C, for IGBTs it is 150°C to 175 °C. The latest developments aim at a further increase of these maximum temperatures up to 200°C.

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III. ADVANCED DIE ATTACH TECHNOLOGY Over the last years the power module society has been

introduced to several innovative packaging concepts all aiming for a significant increase of the power module reliability at high temperature operation [1].

When junction temperatures reach 200°C, the operating temperature will exceed 90% of the homologous temperature (when measured in absolute temperature in K) of the soft solder material, whose process temperature is typically below 250°C. Therefore, soft soldering does not represent a durable die to substrate interconnect technology any longer, as soft solder is subjected to extensive thermally activated creep processes leading to partial die disconnect by fast solder crack propagation [2]. Two technologies have emerged which can solve this problem: One technology is transient liquid phase soldering or bonding [3, 4]. The SnCu solder is partially converted to high melting point intermetallic SnCu-Phases, which are formed from a soft solder alloy by a time and temperature controlled process. The copper is either provided from Cu particles inside the solder (TLPS, Fig 2) or from the contact surfaces (TLPB).

Fig. 2: Transient liquid phase soldering (TLPS)

The second technology is silver diffusion sintering [5] which is explained schematically in Fig 3. A thin layer of sinter paste containing µm-size silver flakes is subjected to high pressure (40 MPa) and moderate temperature (250 °C). Under this condition the silver diffuses to form a massive silver layer with a remaining porosity of about 10-20%.

Fig. 3: Silver diffusion sintering process With both technologies, the die is attached at moderate

temperature and the interconnect undergoes a change by diffusion processes, resulting in a much higher homologous temperature in the range of 50% for TLPS

and 30% for silver sintering. Thus these joints are considered to be mechanically stable. Fig. 4 shows this for silver sintering, were the homologous temperature is well below 40% at 150°C junction temperature, enabling stable die to substrate interconnects even at temperatures of 200 °C.

material SnAg(3.5)Ag sinter

layersolidus temperature [°C] 221 961solidus temperature [K] 494 1234operation temperature [°C] 150 150operation temperature [K] 423 423homologous temperature [%] 86 34 Fig 4: Homologous temperature comparison

Extensive lifetime tests have shown that the power

cycling capability can be increased by more than one order of magnitude. For example: while a conventional chip solder joint shows a significant increase of thermal resistance (due to reduced contact area caused by solder cracks) after 40k cycles at ΔTj of 110 K [6], silver sintered chips do not exhibit any change in thermal resistance even after >700k cycles at ΔTj of 110 K [7].

Another weak link in standard power modules is the chip top side contact made of Al-wire. The bond wire diameter typically varies between 125-600µm, depending on the module type and chip size. The wire is attached to the Al top side metallization by an ultrasonic wedge bonding process. The main reason for wire bond fatigue is the large difference in the coefficients of thermal expansion (CTE) of the Al wire (25 ppm/K) and the silicon die (4 ppm/K) and the DBC (7 ppm/K). The resulting failure modes after load cycling are wire bond heel cracking and bond wire lift off.

An excellent alternative are Cu-wire bonds due to the reduced CTE of 18 ppm/K and the high yield strength of Cu. In addition, Cu has a higher thermal and electrical conductivity. Unfortunately, due to the mechanical properties of the materials it is not possible to realize a Cu-wedge bond on a chip with a standard Al topside metallization. The copper penetrates the soft Al contact, causing severe damage to the silicon underneath. Therefore, Cu-wires have so far only been used to connect the DBC substrate to Cu lead frames for the power module main and auxiliary terminals.

With the introduction of a thick Cu chip top side metallization the situation has changed [4]. Due to improved thermal and electrical properties of the Cu contact and the improved CTE mismatch unprecedented power cycling results of >1Mio cycles at ΔTj of 110 K have been demonstrated.

However putting thick Cu metallization on thin wafers is a critical process causing wafer bow and handling problems. Therefore, alternatives like a buffer layer to a standard chip top side have been proposed [8]. In addition to the chip bottom side sinter connection, also the chip top side is sintered to an additional copper foil that in turn can be wedge bonded with Cu-wires, showing the same reliability improvement like a direct Cu chip top side contact.

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Fig. 5: Cu wire bonding on Cu metallized chips. Photo by courtesy of Infineon Technologies.

Recently, novel heavy wire bonds made of an Al and

Cu composite material were introduced [9]. A Cu wire core is cladded by an Al surface. Fig. 6 shows a cross section of the material. In contrast to a pure Cu-wire no change in the metallization of the chip surface is necessary to establish a stable bonding process. The new material is still under development with the goal to increase the Cu content to a maximum without yield problems during the bonding process. The published power cycling results of > 250k cycles at ΔTj of 110 K are already 4 times higher than with a standard Al-wire. Al/Cu wire bonds provide a potential low cost solution to achieve higher operation temperatures for most applications.

Fig. 6: Cross section of a 300µm Al/Cu wire bond

IV. SKIN TECHNOLOGY A total different approach is to eliminate the bond wires

completely and to replace them with a flexible Cu foil that is sintered to the die top surface, the so called SKiN-Technology [7, 10].

In the SKiN-Technology all solder and bond wire contacts of the standard power module design are replaced by silver diffusion sintering joints. Fig. 7 shows a schematic cross section of such a module. In addition to the sinter joint between chip and DBC also the DBC backside is sintered to the baseplate or directly to the heat sink. The top side of the chip is sintered to a 2 layer flex board. While the lower layer of the flex carries the main high power current the upper layer takes care of low power auxiliary and sensor signals.

While bond wires due to manufacturing limitations can only make contact to about 21% of the total metallized chip surface, the sintered flex foil exhibits a contact area of 50% on the IGBT and 85% on the diode, which can be

seen on Fig. 8. The increased contact surface and the thick metal layer improve the heat distribution to reduce hot spots as well as the surge current capability which is increased by about 30%.

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Fig. 7: Schematic cross section of SKiN-Technology

All new materials are suited for future applications with

maximum chip temperatures of 200°C. Due to the rigid sinter connection and the reduced CTE mismatch of the joining partners impressive improvement in power cycling of >700k cycles at ΔTj of 110 K and >3Mio cycles at a ΔTj of 70 K have already been demonstrated.

Fig. 8: Top view of SKiN device. The picture shows a half bridge configuration with two IGBTs per switch and a single diode in between.

V. POWER DENSITY IMPROVEMENT The thermal resistance from chip to cooling medium is

indirectly proportional to the maximum power dissipation of the device (1). Over the last years several advances in reducing the thermal resistance have been made, mainly by enhanced thermal conductivity of DBC ceramics and reduced layer thickness. Today the most common substrates are Al2O3 DBCs with 0,38mm ceramic thickness. A new promising ceramic material is Si3N4 mainly due to its improved thermal conductivity and its superior mechanical strength.

For a standard power module mounted on a water cooler with 45°C water temperature and a junction temperature of 125°C a power density of about 1,2W/mm2 chip area is a typical number. For assemblies on air coolers it is about 0,6W/mm2.

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Fig. 9 illustrates the distribution of the thermal resistance between heat sink, thermal interface material (TIM) and DBC plus chips for a water cooled system. It consists of a baseplate-less module connected to the heat sink by either TIM or a large-area Ag sinter layer. The comparison shows that the TIM layer alone, although it has just a thickness of 20µm, makes almost 30% of the total thermal resistance. If this TIM layer is eliminated by a sintered joint the overall thermal resistance is reduced by 24% and the power density can be increased to 1,5W/mm2.

Fig. 9: Calculated thermal resistance comparison for a baseplate–less module using either TIM or an overall sintered solution

In the SKiN power module a high density pin fin Al

heat sink is used that is in direct contact with the cooling fluid. Fig. 10 shows the device which is rated 180A, 1700V, the dimensions are 74mm x 56mm. In this design the total thermal resistance from junction to water is just 0,2K/W with 5 liter/min and a total chip area of 200mm2. Using the same parameters as in the example above a power density of 2W/mm2 chip area is reached. If the maximum chip temperature is increased to 150°C which is made possible by the superior power cycling capability of the SKiN technology, this number can be even further increased up to 2,6W/mm2.

Fig. 10: SKiN power module with integrated high performance pin fin cooler

Such high power densities are of special interest for

automotive as well as high power industrial applications. The power brick concept in Fig. 11 gives an example for an integration of four SKiN power modules in parallel in a high power industrial building block [11]. Two modules on each side are arranged back to back on a water distribution frame. Rubber gaskets are sealing each module against the frame. The DC and AC terminals are on opposite sides forming a half bridge arrangement with a 3 dimensional integrated water cooler. The power brick

has a rating of 720A, 1700V. For multi megawatt converters again 4 power bricks are arranged on a common water distribution rail. Fig. 12 shows such a 3MWphase leg assembly with a film capacitor block in the back. The overall dimensions of such a phase leg are 400 x 190 x 200 mm³ with 2880A, 1700V. Due to the superior cooling concept this device is capable to carry 2900A RMS current at 2,5kHz switching frequency, 1100V DC-link voltage and 50°C coolant temperature, which is the same as the Ic nominal rating. Such high power densities are only made possible due to direct water cooling. At overload conditions one has to take care not to exceed the maximum pulsed collector current of the die, which is typical 2-3 times the nominal rated current.

Fig. 11: Power Brick assembly with 4 SKiN modules back to back in parallel (left) and with cover (right)

Fig. 12: High power assembly with four Power Bricks in parallel on a common water distribution rail with a film capacitor in the back

VI. CONCLUSION With the need for higher power densities and further

cost reduction of power electronics it is evident that higher junction temperatures and higher integration levels of power module packaging has become a major research challenge. Many different innovative concepts have been followed by industry and academia over the last years. The published reliability improvements, which seemed to be impossible 10 years ago, will enable the use of future 200°C rated Si and SiC devices, without any drawback in reliability. For die attachment, transient liquid phase soldering, Ag diffusion sintering, Cu or Cu/Al wire

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bonding and sintered flex foils all provide exciting and partly competing ways of future die attachment methods. The future will show which, if any, concept will become the mainstream for future industrial module production.

Direct liquid cooling of modules and innovative system integration lead the way to unprecedented power densities, reducing cost and volume of power electronic systems. However the presented improvements are only possible for water cooled devices. Air cooled systems which are dominating the low to medium power converters will only benefit from the increased junction temperature, which in turn will also lead to increased heat sink temperatures. Reliability issues associated with the resulting higher operating temperatures of passive components or controllers need to be addressed by future material research as well as an intelligent temperature management.

With SKiN technology, a packaging technology has emerged which opens the way to new packaging and system integration concepts, which could help to overcome these problems.

REFERENCES [1] T. Stockmeier: “Power Module Packaging Technologies: The

World is complex”, PCIM, Shanghai, China, 2012 [2] M. Poech, R. Eisele: „Modelling the Mechanical Behaviour of

Large-Area Solder Joints“, PCIM, Nuremberg, Germany, 2000 [3] W.D. MacDonald, T.W. Eagar: “Transient Liquid Phase

Bonding”, Annual Rev. Mater. Sci. 1992. 22: pp. 23 - 46. [4] K. Guth, D. Siepe, J. Görlich, H. Torwesten, F. Hille, F. Umbach,

R. Roth: „New assembly and interconnects beyond sintering method“, PCIM, Nuremberg, Germany, 2010

[5] S. Klaka: „Eine Niedertemperatur-Verbindungstechnik zum Aufbau von Leistungshalbleitermodulen“, Dissertation, Cuvillier Verlag, 1997

[6] U. Scheuermann, R. Schmidt, “Impact of Solder Fatigue on Module Lifetime in Power Cycling Tests” EPE, Birmingham, UK, 2011

[7] P. Beckedahl, M. Hermann, M. Kind, M. Knebel, J. Nascimento, A. Wintrich: “Performance comparison of traditional packaging technologies to a novel bond wire-less all sintered power module”, PCIM, Nuremberg, Germany, 2011

[8] J. Rudzki, F. Osterwald, M. Becker, R. Eisele, “Novel Cu-bond contacts on sintered metal buffer for power module with extended cababilities”, PCIM, Nuremberg, Germany, 2012

[9] R. Schmidt, U. Scheuermann, Eugen Milke, “Al-Clad Cu Wire Bonds Multiply Power Cycling Lifetime of Advanced Power Modules”, PCIM, Nuremberg, Germany, 2012

[10] T. Stockmeier, P. Beckedahl, C. Göbl, T. Malzer, “SKiN - Double side sintering technology for new packages”, ISPSD, San Diego, USA, 2011

[11] T. Grasshoff, P. Beckedahl, R. Ehler, “Ultra compact power module for liquid cooled inverter”, PCIM, Nuremberg, Germany, 2012

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