1

EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces

Lecture #22Link Budgeting and BER AnalysisVladimir Stojanovic (vlada@stanford.edu)Stanford University and Rambus Inc.4/8/2004

2

Agenda

Backplane channel reviewLink system models and noisePerformance analysis

2

3

Backplane Environment - Recap

Line attenuationReflections from stubs (vias)

Back plane connector

Line card trace

Package

On-chip parasitic(termination resistance and device loading capacitance)

Line card via

Back plane trace

Backplane via

Package via

Back plane connector

Line card trace

Package

On-chip parasitic(termination resistance and device loading capacitance)

Line card via

Back plane trace

Backplane via

Package via

4

Backplane ChannelLoss is variable

Same backplaneDifferent lengthsDifferent stubs

Top vs. Bot

Required signal amplitude set by noise

Need to architect the link to work over all channels

Need tools to estimate link performance over all channels

0 2 4 6 8 10

-60

-50

-40

-30

-20

-10

0

frequency [GHz]

Atte

nuat

ion

[dB

]

9" FR4, via stub

26" FR4,via stub

26" FR4

9" FR4

3

5

Inter-symbol Interference (ISI) - RecapChannel is low pass

Our nice short pulse gets spread out

0 1 2 3

0

0.2

0.4

0.6

0.8

1

ns

puls

e re

spon

se

Tsymbol=160ps

Dispersion –short latency(skin-effect, dielectric loss) Reflections –long latency(impedance mismatches –connectors, via stubs, device parasitics, package)

6

ISI

Middle sample is corrupted by 0.2 trailing ISI (from the previous symbol), and 0.1 leading ISI (from the next symbol) resulting in 0.3 total ISIAs a result middle symbol is detected in error

0 2 4 6 8 10 12 14 16 180

0.2

0.4

0.6

0.8

1

Symbol time

Am

plitu

de

Error!

4

7

CrosstalkDon’t just receive the signal you want

Get versions of signals “close” to youVertical connections have worse coupling

“Close” in these vertical connection regions

Far-end XTALK (FEXT)

Desired signal

Near-end XTALK (NEXT)

Reflections

Sercu, DesignCon03

8

Frequency View of Crosstalk

For this example:> 4GHz, noise is as large as the signal

0 2 4 6 8 10

-60

-50

-40

-30

-20

-10

0

frequency [GHz]

Atte

nuat

ion

[dB

]

FEXT

NEXT

THROUGH

5

9

Agenda

Backplane channel reviewLink system models and noise

Previous standard approachesStatistical modeling

Performance analysis

10

Parameter Definition for VT Based BudgetVoltage parameter definitions

Simultaneous switching output (SSO) noiseReceiver sensitivity (offset + overdrive)Channel lossCrosstalk Back-to-back read

Timing parameter definitionstQ: transmitter output timingtSH: receiver output timingtCE: channel timing errortJ: clock source jitter

6

11

Component of RAC to RDRAMTiming Budget ps %

Bit time 1250.0RAC tQ 500.0 40.0%

RDRAM tSH 400.0 32.0%tCE 290.0 23.2%tJ 60.0 4.8%

Margin 0.0 0.0%Total 100.0%

RDRAM VT Budget

Vterm=1.2V and 36D (channel)At 800Mb/s

tCE is at 23% of bit timevCE is at 62.5% Vswing (900mV)

12

Fiber Channel – Methodologies for Jitter SpecificationTotal jitter = Deterministic (DJ) + random jitter (RJ)DJ: Non-Gaussian, bounded in amplitude and has specific causes (duty cycle distortion, data dependent, sinusoidal and uncorrelated (power supply noise injection))DJ is measured as a peak-to-peak value and adds linearlyRJ: Gaussian and measured as an RMS valueRJ: Peak-to-peak jitter = 14 * RMS jitter for a BER of 10

-12

Total jitter = peak-to-peak DJ + peak-to-peak RJJitter measurement definitions

Jitter outputJitter transferJitter tolerance (ability of a CDR to successfully recover the data in the presence of jitter)

Create a tolerance mask by examining the CDR lock at different frequencies vs. sinusoidal jitter magnitude

7

13

Jitter measurement definitions

Jitter generation (jitter added by the PLL due to phase and supply noise)Jitter transfer (jitter at the output of the PLL due to refClk noise)Jitter tolerance (ability of a CDR to successfully recover the data in the presence of jitter)

Create a tolerance mask by examining the CDR lock at different frequencies vs. sinusoidal jitter magnitude

CDR Tolerance & XAUI Sinusoidal Jitter Tolerance Mask

0.000.501.001.502.002.503.003.504.004.505.005.506.006.507.007.508.008.509.00

0.010 0.100 1.000 10.000 100.000

Jitter Frequency (MHz)

Jitt

er A

mpl

itude

(UI)

XAUI MaskLV at Vtt-Rx=1V & 3.125Gbps

XAUI Sinusoidal Jitter Mask

1.875MHz 20 MHz

0.1UI0.1UI

22KHz

14

Fiber Channel Jitter Specification for 1.0625 Gbps

8

15

Previous system modelsMostly non-existentBorrowed from computer systems

Worst case analysisCan be too pessimistic in links

Borrowed from data communicationsGaussian distributions

Works well near mean Often way off at tails

ISI distribution is bounded

Need accurate models To relate the power/complexity to performance

16

Comparison w/ Gaussian Model

0 25 50 75 100

-10

-8

-6

-4

-2

0

re sidual ISI [m V ]80 100 120 140 160 180

-10

-8

-6

-4

-2

0

40mV error @ 10-10

25% of eye height

4% Tsym bol

error @ 10-10

9% Tsym bol

log 10

pro

babi

lity

[cdf

]

log 10

Ste

ady-

Stat

e Ph

ase

Prob

abili

ty

phase count

Cumulative ISI distribution Impact on CDR phase

Gaussian model only good down to 10-3 probabilityWay pessimistic for much lower probabilities

9

17

A new model

Use direct noise and interference statistics

Main system impairmentsInterference

Voltage noise (thermal, supply, offsets, quantization)

Timing noise – always looked at separatelyKey to integrate with voltage noise sourcesNeed to map from time to voltage

18

Residual ISI Error

Cannot correct all the ISI

Equalizers are finite length

EQ coefficients quantized

Channel estimate error

The error affects both voltage and timing

Need to find the distribution of this error

10

19

Generating ISI Distributions

-3 -2 -1 0 1 2 -10

15

200

-10 10 0

0.25

0.5

0.75

1

-15 15 0

0.25

0.5

0.75

1

-25 -5 5 25 0

0.25

0.5

0.75

1

volta

ge [m

V]

sample #

[mV]

prob

abili

ty [p

mf]

prob

abili

ty [p

mf]

prob

abili

ty [p

mf]

[mV]

voltage [mV]

Convolution method

Tx Equalizedpulse response ISI distribution

20

Estimated Residual Error

-60 -40 -20 0 20 40 60 0

0.01

0.02

0.03

0.04

voltage [mV]

prob

abili

ty d

istri

butio

n of

resi

dual

ISI

-150 -100 -50 0 50 100 150 0

0.004

0.008

0.012

0.016

voltage [mV]

prob

abili

ty d

istri

butio

n of

resi

dual

ISI

Data sample distribution Edge sample distribution

5 Tap Transmitter Equalizer

11

21

Equalizer Related Error Sources

Residual ISI is the biggest source of errorQuantization error and equalizer estimation

Are significant for reasonable assumptions about accuracy

0 1 2 3

-60

-50

-40

-30

0 1 2 3

-60

-50

-40

-30data sample

residual ISI

Pow

er s

pect

ral d

ensi

ty [d

BV]

10%/tap max. eq. estimation error

10mV/tap max. eq. quantization error

frequency [GHz] frequency [GHz]

10mV/tap max. eq. quantization error

10%/tap max. eq. estimation error

residual ISI

edge sample

22

Random Voltage Noise

Thermal noiseResistor and Device noise

Quantization Estimation errorSupply noiseReceiver offset

12

23

Effect of Timing NoiseNeed to map from time to voltage

Ideal sampling

The effect is going to depend on the size of the jitter, the input sequence, and the channel

Jittered sampling

Voltage noiseVoltage noise when receiver clock is off

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Effect of Transmitter Jitter

Decompose output into ideal and noiseNoise are pulses at front and end of symbol

Width of pulse is equal to jitter

Jittered pulse decomposition

ideal

noise

kb

kT

TXkε

Tk )1( +

TXk 1+ε

kT

TXkε

Tk )1( +

TXk 1+ε

+

kb−

kb

kb

1

2

V. Stojanović, M. Horowitz, “Modeling and Analysis of High-Speed Links,” IEEE Custom Integrated Circuits Conference, September 2003.

13

25

Transmitter Jitter NoiseApproximate the noise pulses with deltas

Assuming jitter is much narrower than channel impulse response

Channel outputOutput with no jitterResponse to the noise deltas

TXkε

TXk 1+ε

kb−

kb

≈TXkkb ε−

TXkkb 1+ε

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Jitter effect on voltage noiseTransmitter jitter

High frequency (cycle-cycle) jitter is badChanges the energy (area) of the symbolNo correlation of noise sources that sum

Low frequency jitter is less badEffectively shifts waveformCorrelated noise give partial cancellation

Receive jitterModeled by shift of transmit sequenceSame as low frequency transmitter jitter

εεεεkRx≡≡≡≡

εεεεkRx

14

27

Jitter Propagation Model

Channel bandwidth mattersIf h(T/2) is small, the noise is smallh(nT+1/2) not small, many pulses add

TXw )( jTp

)(sHjitPLL

ka kb

TXkk 1, +ε

inn

+

2TjTh

+ kxISIkx

jitTXkx RX

kε

kaprecoder

impulseresponse

pulseresponse

vddn

RX

ideal

noise

∑−=

− +=++sbE

sbSjijk

RXki

ISI jTpbkTx )()( φεφ

( ) ( )∑−=

−+−−

−+−−−++=++

sbE

sbSj

TXjk

RXki

TXjk

RXkijk

RXki

jitter TjThTjThbkTx 1)2

()2

()( εεφεεφεφ

28

Voltage Noise From Jitter

White jitterNoise from Tx much larger than from Rx jitterFrom Rx jitter, noise is whiteFrom Tx jitter, filtered by the channel

Y-axis is noise σσσσ (in Volts)If the noise was whiteσ = 10mV => -40dBV

0 0.5 1 1.5 2 2.5 3

-60

-50

-40

-30

Pow

er s

pect

ral d

ensi

ty [d

BV

]

frequency [GHz]

Source – white jitter

Noise from Tx jitter

Noise from Rx jitter

Bandwidth of the jitter is criticalIt sets the magnitude of the noise created

15

29

Jitter Source From PLL Clocks

Ref Clk Phasedetector

Kpd

Icp

Icp R

C

VCOKvco/s

Clockbuffer

N÷

+−

Noise sourcesReference clock phase noiseVCO supply noiseClock buffer supply noise

Stationary phase-space model

30

Noise Transfer Functions

105 106 107 108 109 1010

-30

-20

-10

0

10

frequency [Hz]

Noi

se tr

ansf

er fu

nctio

ns [d

B]

fromVCO supply

frominput clock

fromclock buffer supply

Ref Clk PhasedetectorKpd

Icp

Icp R

C

VCOKvco/s

Clockbuffer

N÷

+−

Low-pass from reference (input clock)Band-pass from VCO supplyHigh-pass from clock buffer supply

M. Mansuri, C-K.K. Yang, "Jitter optimization based on phase-locked loop design parameters," IEEE Journal Solid-State Circuits, Nov. 2002

16

31

PLL supply noise

Total noise ~ 25mV peak-to-peak3.7% of on-chip VddA (quiet PLL supply)

Deterministic noise still present.

Where is this noise coming from?

E. Alon, V. Stojanovic, M. Horowitz “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise,” IEEE Symposium on VLSI Circuits, June 2004.

32

Noise Spectrum (1)

Deterministic noise frequency components:200MHz - ASIC core operating frequency.

Noise on link supplies due to ground bounce.400MHz - reference clock, some link logic.4GHz - link data rate.

Data & edge clocks at 2GHz => 4GHz noise.Tail current modulation in diff. pairs.

10MHz 100MHz 1GHz 10GHz-100

-80

-60

-40

-20

0

Frequency

PSD

(dBV

)

10MHz 100MHz 1GHz 10GHz-100

-80

-60

-40

-20

0

Frequency

PSD

(dBV

)

Noise floor Noise floor

Vdd noise VddA noise

17

33

Noise Spectrum (2)

Random noise mostly white.Low frequency peaking in Vdd noise due to underdamped impedance of distribution network.

VddA distribution network more damped because of higher resistance.

10MHz 100MHz 1GHz 10GHz-100

-80

-60

-40

-20

0

Frequency

PSD

(dBV

)

10MHz 100MHz 1GHz 10GHz-100

-80

-60

-40

-20

0

Frequency

PSD

(dBV

)

Noise floor Noise floor

Vdd noise VddA noise

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Slicer

PD

deserializer

PLL

dataOut

ref Clk

Phasecontrol

Phasemixeredge Clk

data Clk

RX

2x Oversampled Bang-Bang CDR

Generate early/late from dn,dn-1,enSimple 1st order loop, cancels receiver setup time

Now need jitter on data Clk, not PLL output

dn-1

dn

en (late)

dn

en

18

35

Data Clk NoiseModel phase selector and PLL

Base linear PLL jitterAdd non-linear phase selector noise from CDR

Model the CDR loop as a state machineThe current phase position is the stateState transitions are caused by early/lateJitter on input data and PLL means

Possible to be late and get early PD resultOften filter early/late to generate up/down

A.E. Payzin, "Analysis of a Digital Bit Synchronizer," IEEE Transactions on Communications, April 1983.

36

Transition Probabilities

0 50 100 150 200 2500

0.2

0.4

0.6

0.8

1

Accumulate-resetfilter, length 4Pr

obab

ility

Phase count

p-early

p-hold

p-late

p-no-validtransitions

p-up p-dn Example system:CDR loopResidual ISI

At edge -30dBVDesired phase

State = 133

On average move to correct positionBut probability of wrong movement is not smallNeed to find probability of at each phase location

19

37

Bang-Bang CDR Statistical Model

Need steady state probabilities of the statesHave the transition probabilities

Iteratively apply transition probabilities (Markov chain)Results will converge to a steady-state

iφ1−iφ 1+iφ0φ Lφ

iholdp ,

iupp ,

idnp ,

38

0 50 100 150 200 250

-15

-10

-5

0

Phase Count

log 10

Ste

ady-

Stat

e Pr

obab

ility

Bang-Bang CDR Model

Gives the probability distribution of phaseWhich is the CDR jitter distribution

20

39

Noise and Interference SummaryMany important sources of noise and interference

ISI, crosstalk, quantization, estimation, etc.Largest error comes from ISI

By factor of 10xTiming is noisy too

High frequency transmitter jitter is badCDR jitter needs to be considered

Especially if the data input is noisy

What is the impact on performance?

40

Agenda

Backplane channel reviewLink system models and noise

Previous standard approachesStatistical modeling

Performance analysis

21

41

50 60 70 80 90 100 110-300

-200

-100

0

100

200

300

time [ps]

volta

ge [m

V]

-30

-25

-20

-15

-10

-52PAM - lin. eq

ISI and CDR Phase Distributions

In ideal world, there would be only two dotsThis plot shows how these dots spread out

Vertical slice – ISI distribution per time offsetHorizontal weight – CDR phase distribution

42

Putting It All Together

To compare different designsCompare the voltage margin at given BER

Need to include all noise sourcesAccurate ISI distributionTransmit and receive jitterCDR jitterEQ quantization noiseReceiver offset

22

43

0 20 40 60 80 100 120 140 160-150

-100

-50

0

50

100

150

time [ps]

mar

gin

[mV]

-30

-25

-20

-15

-10

-5

BER Contours

Voltage marginMin. distance between the receiver threshold and contours with same BER

0 20 40 60 80 100 120 140 160-150

-100

-50

0

50

100

150

time [ps]m

argi

n [m

V]

-30

-25

-20

-15

-10

-5

5 tap Tx Eq 5 tap Tx Eq + 1 tap DFE

44

BER Contours PAM2 DFE PAM4 linear equalization

0 40 80 120 160250

200

150

100

-50

0

50

100

150

200

250

time [ps]

mar

gin

[mV]

-30

-25

-20

-15

-10

-5

0 40 80 120 160 200 240 280 320-250

-200

-150

-100

-50

0

50

100

150

200

250

time [ps]

mar

gin

[mV]

-30

-25

-20

-15

-10

-5

23

45

Model and measurements

-80-60-40-200 20 40 60 80

-14

-12

-10

-8

-6

-4

-2

0

log1

0(B

ER)

Voltage Margin [mV]

PAM4, 3taps of transmit equalization, 5Gb/s, 26” FR4 channel

46

Example channels

Legacy (FR4) - lots of reflectionsMicrowave engineered (NELCO)

0 5 10 15 20

-100

-80

-60

-40

-20

0

Atte

nuat

ion

[dB

]

frequency [GHz]

26" FR4, via stub

26" NELCO,no stub

(b)

V. Stojanović, A. Amirkhany, M. Horowitz, “Optimal Linear Precoding with Theoretical and Practical Data Rates in High-Speed Serial-Link Backplane Communication,” IEEE International Conference on Communications, June 2004

24

47

Capacity achieving bit loading

0 5 10 15 20 250

1

2

3

4

5

6

7

8

9

10

frequency [GHz]

#bits

/Hz

Capacity with thermal noise

Nelco 105Gb/sFR4 70Gb/s

0 2 4 6 8 10 12 140

2

4

6

8

10Multi-tone data rates with thermal noise

Nelco 64Gb/sFR4 38Gb/s

#bits

/Hz

frequency [GHz]

Capacity is very bigPractical rates lower

low target BER<10-15

peak power constraintThermal noise – the smallest noise source

48

Capacity with link-specific noise

Effective noise from phase noiseProportional to signal energyDecreases expected gains

Still, capacity is much higher than data rates in today’s links (3Gb/s)

NELCO FR4

-25 -20 -15 -10 -5 00

20

40

60

80

100

120

140

Cap

acity

[Gb/

s]

log10(Clipping probability)

thermal noise

thermal noise and LC PLL phase noise

thermal noise and ring PLL phase noise

-25 -20 -15 -10 -5 00

20

40

60

80

100

120

140

Cap

acity

[Gb/

s]

log10(Clipping probability)

thermal noise

thermal noise and LC PLL phase noise

thermal noise and ring PLL phase noise

25

49

Multi-tone with integer bit loading

-25 -20 -15 -10 -5 00

10

20

30

40

50

60

70

80

90D

ata

rate

[Gb/

s] a) NELCOthermal noise

thermal noise and LC PLL phase noise

thermal noise and ring PLL phase noise

log10(Clipping probability)-25 -20 -15 -10 -5 00

10

20

30

40

50

60

70

80

90

Dat

a ra

te [G

b/s] b) FR4

thermal noise

thermal noise and LC PLL phase noise

thermal noise and ring PLL phase noise

log10(Clipping probability)

Peak-power constraint introduces large gap penalty to capacity (can go around with coding, but too expensive)Still pretty high data rates

NELCO FR4

50

Multi-level: Offset and jitter are crucial

thermal noise + offset

thermal noise + offset+ jitter

To make better use of available bandwidth, need better circuitsPAM2/PAM4 robust candidate for next generation links

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

Dat

a ra

te [G

b/s]

Symbol rate [Gs/s]

PAM16

PAM8

PAM4

PAM2

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

Symbol rate [Gs/s]

Dat

a ra

te [G

b/s]

PAM2

PAM4

PAM8

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

35

40

45

Dat

a ra

te [G

b/s]

PAM4

PAM16

PAM8

PAM2

Symbol rate [Gs/s]

thermal noise

26

51

Full ISI compensation too costly

0 2 4 6 8 10 12 14 160

2

4

6

8

10

12

14

16

18

20

Dat

a ra

te [G

b/s]

Symbol rate [Gs/s]

PAM16PAM4

PAM2PAM8

0 2 4 6 8 10 12 14 160

2

4

6

8

10

12

14

16

18

20

Symbol rate [Gs/s]

Dat

a ra

te [G

b/s]

PAM8

PAM4

PAM2

0 2 4 6 8 10 12 14 160

2

4

6

8

10

12

14

16

18

20

Symbol rate [Gs/s]

Dat

a ra

te [G

b/s]

PAM2

PAM4

PAM8

thermal noisethermal noise + offset

thermal noise + offset+ jitter

Today’s links cannot afford to compensate all ISILimits today’s maximum achievable data rates

52

ConclusionsBackplane links limited by the channelISI is large in baseband links

Can’t completely compensate(At least not with reasonable area/power)

Residual ISI also increases CDR jitterGenerally have low BER requirements

Accurate noise statistic important Many of large noise source are bounded

Power constrained transmitterPAM4 and PAM2 with simple DFE are attractive solutions

Still, capacity of these links is very bigSmart multi-tone?