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Hezi Saar April 27, 2017 IoT DevCon Conference Advantages of MIPI Interfaces in IoT Applications

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Page 1: Advantages of MIPI Interfaces in IoT Applications of MIPI Interfaces... · Advantages of MIPI Interfaces in IoT Applications ... Start of Transmission EoT – End of Transmission

Hezi Saar

April 27, 2017

IoT DevCon Conference

Advantages of MIPI Interfaces in IoT Applications

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© 2017 Synopsys, Inc. 2

Abstract

In addition to sensors, high-resolution cameras are key enablers of IoT devices. The challenge for IoT designers is to find a solution that delivers low power consumption and high performance, while meeting cost constraints. MIPI CSI-2 is a proven interface in the mobile market, and because of its successful implementation, it is being utilized in new applications like IoT and virtual/augmented reality devices. The new MIPI I3C specification delivers a cost-effective solution that enables multiple sensor connectivity in a simplified architecture. This presentation defines the MIPI CSI-2 and I3C specifications, and describes their implementation, as well as power and performance advantages in IoT SoCs.

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Agenda

Implementation of MIPI interfaces in mobile applications and beyond

Advantages of MIPI CSI-2, DSI, I3C, D-PHY specifications

Summary

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MIPI Specifications in New ApplicationsIoT / Wearables, Virtual / Augmented Reality, Automotive

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From the Edge to the Cloud

IoT Edge Devices(Smart Devices)

Aggregation Layers(Hubs/Gateways)

Remote Processing(Cloud Based)

“Things” with sensors & actuators that monitor and

control

Connectivity & Interfaces to aggregate the edge data to

send to the cloud

Applications to analyze the data and offer cloud services

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Higher DSP Processing

+ Display

IoT Devices Getting More Complex

Battery Life Up to 14 days

DiscreteVoice, Image, Multiple Sensors

• More capabilities, complex features, and high performance

• Higher level of user and sensor interaction

• Devices with longer battery life

• Ability to turn on/off certain functionalities to reduce power

Low DSP Processing, No Display

Battery Life< 7 days

SingleSensor

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High End SoC for “Always-on” IoT

• Applications– IoT wearables, smart energy hubs– Health / fitness devices– Wireless audio (Bluetooth low energy)

• Common system components– RTOS or bare metal– AA/Coin, lithium– Bluetooth, 802.15.4, Zigbee, Wi-Fi

• Unique technology & IP needs– Embedded NVM (Flash/MTP) – Connectivity, sensors, multimedia and security

Common Characteristics

USB 2.0 Host OTG

w/Charge Detect

Security

Radio (WiFi, Bluetooth Smart, 802.15.4)

Data Fusion IP Subsystem

ADC

ARC EMxDProcessor

I2C/ I3C SPI

UART

Timers

ROM

GPIOSRAM

H/WAccel

NVM (eFlash / MTP)

MIPICSI2 Host

MIPIDSI Host

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Implementation of Widely-Used MIPI SpecificationsCSI-2, DSI, D-PHY

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MIPI CSI-2 Over D-PHY Overview

CSI-2 Device

DPH Y

CSI-2 Host

DPHY

Clk+

Clk-

L0+

L0-

Clk+

Clk-

L0+

L0-L1+

L1-

L1+

L1-

Frame Buffer

CSI-2 Transmitter

PacketBuilder

LaneDistribution

CCI SlaveSCL

SDA

SCL

SDA

CCI Master

CSI-2 Packet

CSI-2 Packet

D-PHYHS Burst

D-PHYHS Burst

CSI-2 Receiver

PacketDecoder

LaneMerger

CSI-2 Packet

CSI-2 Packet

Frame Buffer

VC CRCD

T WC ECC

Payload byte size Data CRC processing

ECC protecting the header

Data Format Definition

Virtual Channel Identification

Packet Builder

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MIPI CSI-2 Packets

Data PFPHFS FEData PFPH

KEY:SoT – Start of Transmission EoT – End of Transmission LPS – Low Power StatePH – Packet Header PF – Packet Footer + Filler (if applicable)FS – Frame Start FE – Frame EndLS – Line Start LE – Line End

Frame Start Packet

Frame End Packet

First Packet of Data

Last Packet of Data

VVALID

HVALID

DVALID

SoT LPSEoT SoT EoTLPSEoT SoTEoT SoT

Short packets used for frame synchronization

Image data

Low power states between

image lines

Short packets used for frame synchronization

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DSI SPacket

DSI SPacket

VC CRCD

T WC ECC

Payload byte size Data CRC processing

ECC protecting the header

Data Format definition

Virtual Channel Identification

Packet Builder – LONG Packet

MIPI DSI Over D-PHYDSI Video Mode Example – DPI Interface

DPH Y

DPHY

Clk+

Clk-

L0+

L0-

Clk+

Clk-

L0+

L0-

L1+

L1-

L1+

L1-

DSI Transmitter

PacketBuilder

Lanedistribution

DSI Receiver

PacketDecoder

Lanemerger

VSS HSE

VC

DT DATA0 ECC

ECC protecting the short packet

Data Format definition

Virtual Channel Identification

Packet Builder – SHORT Packet

DATA1

D-PHYHS Burst

D-PHYHS Burst

DSI LPacket

Valid Image Line

DSI SPacket

VSS

DSI SPacket

HSE D-PHYHS Burst

D-PHYHS Burst

D-PHYHS Burst

D-PHYHS Burst

DSI LPacket

Valid Image Line

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DSI SPacket

DSI SPacket

VC CRCD

T WC ECC

Payload byte size Data CRC processing

ECC protecting the header

Data Format definition

Virtual Channel Identification

Packet Builder – LONG Packet

MIPI DSI Over D-PHYDSI Video Mode Example – DPI Interface

DPH Y

DPHY

Clk+

Clk-

L0+

L0-

Clk+

Clk-

L0+

L0-

L1+

L1-

L1+

L1-

DSI Transmitter

PacketBuilder

Lanedistribution

DSI Receiver

PacketDecoder

Lanemerger

VSS HSE

VC

DT DATA0 ECC

ECC protecting the short packet

Data Format definition

Virtual Channel Identification

Packet Builder – SHORT Packet

DATA1

D-PHYHS Burst

D-PHYHS Burst

DSI LPacket

Valid Image Line

DSI SPacket

VSS

DSI SPacket

HSE D-PHYHS Burst

D-PHYHS Burst

D-PHYHS Burst

D-PHYHS Burst

DSI LPacket

Valid Image Line

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D-PHY Architecture

• Synchronous Forwarded DDR clock link architecture

• One clock and multiple data lanes configuration

• Static/dynamic de-skew supported through calibration

• No encoding overhead• Low-power and high-speed modes• Primarily targeting camera and display• Spread spectrum clocking supported for

EMI/EMC considerations• Large eco-system, proven in millions of

phones, wearables and cars

The Popular Physical Layer Used for CSI-2 and DSI Specifications

Two Data Lane Configuration

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Complete Camera and Display SolutionSingle-Vendor Solution, Production-Proven, Interoperable

Secret Sauce

I2C nowI3C soon

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Implementation of New MIPI I3C Specification Standardizing Sensor Interface

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Why I3C?

• Today Smartphones typically have 10-15+ sensors– Which require 12-18+ pins

• Different Sensors have different requirements – Fingerprint vs Compass

• Typical approach is to connect sensors using a mix of I2C and SPI – I2C for lower data rates and SPI for higher

data ratesMultiple side band signals– For interrupts, chip selects, power

management

Challenge of Integrating Multiple Sensors with Different Requirements

This will increase the package size and add complexity which translates into additional costs

So many I/Os

required!!

Images are courtesy of the MIPI Alliance

No Standard driver for these fragmented interfaces

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MIPI I3C Standardized Sensor Interface

It takes the goodness of I2C – Two-wire, Simple

It takes the goodness of SPI – Low Power and Speed

Adds features such as– In-band interrupt/command support– Dynamic addressing– Advanced power management– High data rates

While maintaining support for legacy I2C sensors

– Evolutionary, not revolutionary

You Can do More with Two Wire communication interface, Clock (SCL) and Data (SDA)

I/Osreduced to just two!!

Images are courtesy of the MIPI Alliance

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I3C Enhanced Capabilities

• Built-in CCC commands allow efficient bus management – Each device has its own attributes (speed capabilities, latency

requirements, etc)– Master can use these commands to query and store device attributes – Master uses all this information to schedule I3C traffic accordingly and

broadcast instructions (enter HDR, enable/disable interrupts, etc.) • Built-in CCC commands enable advanced use cases

– Secondary master role for sensor hub applications– Timing control and time-stamping

• With I3C, user application is not involved in low level protocol details– Complexity in managing multiple sensor is significantly reduced with I3C

I3C is a Sophisticated Protocol … As Opposed to I2C

Image courtesy of MIPI Alliance

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I3C Transfers

• All I3C communication occurs within a frame. The frame begins with a START, followed by one or more transfers, and a STOP

• Legacy I2C messages remain unchanged • Three types SDR messages:

– The address in the address header matches the Slave’s dynamic address

– The address in the address header is 7’h7E (the I3C broadcast address)

– Direct CCC or Broadcast CCC

• HDR messages:– After broadcast address, EnterHDR CCCs is issued

indicating that the Master is entering an HDR mode. Each HDR mode has its own EnterHDR CCC

Legacy I2C ,Typical SDR, SDR CCC Broadcast, SDR Direct CCC and HDR

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I3C Slave Requests

• I3C Slave shall wait for the bus available condition and then issue START by pulling the SDA line low

• In response, the main master shall start the clock on the SCL line, while leaving the SDA line free at high level

• The I3C Slave shall then drive the SDA with its own address, followed by an RnW bit of 1.

• Master accepts the IBI by providing the ACK bit – If the I3C Slave’s BCR[2] bit is set to 1, IBI has

data and Master shall read the mandatory data byte that follows

I3C Slave Interrupt Request – IBI With or Without Data

I3CMASTER

I3CSLAVE

I3CSLAVE

I3CSECY

MASTERI2C SLAVE

S Slave_addr_as_IBI/R Master_ACK SCL HIGH TSlave Byte P

DYNAMICADDR

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I3C Use CasesExamples

Secondary camera module

Primary camera module

Lens actuators/controllers

Image sensor/

SoC

Host processor/

ISP

Image sensor

Pixels

PixelsAccelerometer

Gyroscope

Magnetometer

Ambient Light

Pressure

Humidity

Temperature

Others

Sensor Hub

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C

mas

ter

I3C

se

cond

ary

mas

ter

Application Processor

I3C

mas

ter

Accelerometer

Gyroscope

Magnetometer

Ambient Light

Pressure

Humidity

Temperature

Others

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

Application Processor

I3C

mas

ter

Sensor Hub Sensor Subsystem Image Sensors

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I3C Enables Efficient System ArchitecturesLower Power, More Efficient System, Faster Data Transfer

Accelerometer

Gyroscope

Magnetometer

Ambient Light

Pressure

Humidity

Temperature

Others

Sensor Hub

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

I3C slave

Application Processor I3

C

mas

ter

I3C

se

cond

ary

mas

ter

Application Processor I3

C

mas

ter

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Summary

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Complete MIPI CSI-2, DSI, I3C & D-PHY IP for IoT

• MIPI CSI-2, DSI, D-PHY and I3C protocols– Enables new set of power efficient applications

in AR/VR, IoT markets– Lowers integration risk for application

processors, bridge ICs and multimedia co-processors

• Future proof IP supporting variety of speeds, proven in silicon– Reduces cost & power for multiple

instantiations– Testability features enable low cost

manufacturing

Complete Single-Vendor Solution, Production-Proven, Interoperable

Industry’s first MIPI I3C Demo

Image Signal

Processing

CSI-2 Host Controller

D-PHY

CSI-2 Host Controller

D-PHY

DSI Device Controller

D-PHY

CSI-2 Device

ControllerD-PHY

DSI Host Controller

D-PHY

I3C

SoC