afero tech note - integrating the murata wi-fi+ble …...to use the same design as this would...
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© Afero 2018 – Version 1.2 - D-LIT-00054-00 Afero Proprietary and Confidential Information - 1
Tech Note Integrating the Murata Type1LD BLE+Wi-Fi Module
An Afero Compatible Solution
November 26, 2018 - Version 1.2
1. Introduction 12. Components 2
2.1 Murata Type1LD BLE+Wi-Fi Combo Module 22.2 Afero Security Module 32.3 Winbond Serial Flash 4
3. Antenna Design Recommendations 44. Programming the Murata Module 55. FCC Certification 56. Key Components List 5
1. IntroductionThis tech note describes what you must do for your connected hardware IoT project to work as an edge device in the Afero IoT ecosystem. The ecosystem includes the edge device, the Afero Secure Hub™, the Afero mobile app, and the Afero Cloud.
The instructions in this tech note use the following components:
• Bluetooth® low energy (BLE) + Wi-Fi combo Module (LBEE5PA1LD)• Afero-specific Microchip CryptoAuthentication™ Security Module (ATECC508A-MAHKN)• SPI flash memory (W25Q32JVSSIQ)
Afero Tech Note – Integrating the Murata Wi-Fi+BLE Module
© Afero 2018 – Version 1.2 - D-LIT-00054-00 Afero Proprietary and Confidential Information - 2
2. ComponentsThe block diagram below illustrates the components required for this integration:
2.1 Murata Type1LD BLE+Wi-Fi Combo Module Wi-Fi and BLE enable the “internet” in the Internet of Things (IoT). Wi-Fi provides the backhaul to the data from the edge device, and BLE is used to onboard the device and also as a backhaul when a hub is involved.
The Murata LBEE5PA1LD (1LD) combo module provides an embedded wireless LAN and Bluetooth network controller solution, ideal for IoT applications. It is enabled with Cypress Wireless Internet Connectivity for Embedded Devices (WICED) architecture, hosting the Wi-Fi, TCP/IP network stack, security supplicant, and other network application features.
WICED is a Cypress development system that vastly reduces the effort required to add wireless connectivity to embedded devices.
For more information, go to: https://wireless.murata.com/eng/products/rf-modules-1/wi-fi-bluetooth/type1ld.html
© Afero 2018 – Version 1.2 - D-LIT-00054-00 Afero Proprietary and Confidential Information - 3
Afero Tech Note – Integrating the Murata Wi-Fi+BLE Module
Afero designed the following reference schematic with Murata. (To enlarge the schematic for viewing, zoom using the View menu in your PDF viewer.)
2.2 Afero Security Module Afero uses a security module that stores the keys/certificates required to securely communicate between the Afero Cloud/Hub and the edge device. We integrate this module over I2C.
The Microchip ATECC508A integrates ECDH (Elliptic Curve Diffie Hellman) security protocol, an ultra-secure method providing key agreement for encryption/decryption, along with ECDSA (Elliptic Curve Digital Signature Algorithm) sign-verify authentication for IoT edge devices. The ATECC508A includes an EEPROM array, which can be used for storing security configurations.
Kindly reach out to Afero before mass production procurement since Afero must provide authorization to purchase this module.
For more information, go to: http://ww1.microchip.com/downloads/en/DeviceDoc/20005927A.pdf
1
2
3
4
5
A B C D E F G H
1
2
3
4
5
A B C D E F G H
GND
GND
VDD_IO
I2C1_SDA
GND
GND
RF_O
UT
4.7uF
0.1uF
4.7uF
0.1uF
VDD_WLAN
PC15/O
SC32_O
UT
PC14/O
SC32_IN
VBAT_MCU
45
GND
13
GND
12
VD
D_IO
34
GN
D
33
nR
ESET
32
PB12/SPI2_N
SS
31
PB13/SPI2_SCK
30
PB14/SPI2_M
ISO
29
PB15/SPI2_M
OSI
28
PA12/U
SAR
T1_R
TS
27
PA11/U
SAR
T1_CTS
26
PA10/U
SAR
T1_R
X
25
PA9/U
SAR
T1_TX
24
GND
46
PA14/JTCK
21
PC1/WAKE
14
WL_GPIO_0_HOST_WAKE
15
LPO_IN
16
PA8/MCO_1
17
PB3/JTDO
18
PB4/JTRST
19
PA13/JTMS
20
PA15/JTDI
22
GND
23
RF_O
UT
11
GN
D
10
BT_PCM
_SYN
C
9
BT_PCM
_O
UT
8
BT_PCM
_IN
7
BT_PCM
_CLK
6
GN
D
5
VD
D_W
LAN
4
GN
D
3
PC14/O
SC32_IN
2
PC15/O
SC32_O
UT
1
GN
D
65-70
GND
35
PC7/USART6_RX
36
PC6/USART6_TX
37
BOOT0
38
PA7/SPI1_MOSI
39
PA5/SPI1_SCK
40
PA4/SPI1_NSS
41
PA6/SPI1_MISO
42
VSSA/VREF-
43
VDDA_MCU
44
GND
47
GND
48
PC5
49
WL_GPIO_1
50
WL_GPIO_2
51
WLRF_GPIO
52
CLK_REQ
53
PB9
54
PB10
55
GND
64
PB2/BOOT1
63
PB7/I2C1_SDA
62
PB5/I2C1_SMBA
60
PC4
59
PB0/I2S5_CK
58
PB1/I2S5_WS
57
PB8/I2S5_SD
56
PB6/I2C1_SCL
61
LBEE5PA1LD
U1
MEM_TX_MOSI
MEM_SPI_SCK
MEM_SPI_NSS
MEM_RX_MISO
I2C1_SCL
DBG
_U
AR
T_TX
DBG
_U
AR
T_R
X
DBG
_U
AR
T_CTS
DBG
_U
AR
T_R
TS
GND
0.1uF
HOST_RX_MISO
HOST_TX_MOSI
WRITE
SWO
SWDIO
HOLD
SWDCLK
4.7uF0.1uF
0.1uF 4.7uF
GND
VDDA_MCU
VBAT_MCU
BTP10
RESET_B
SWO
SWDCLK
SWDIOBTP4
BTP5
BTP6
BTP7
10k 10k
TP2
TP3
HOST_TX_MOSI
HOST_RX_MISO
BTP2
BTP3
DBG_UART_RX
DBG_UART_TX
DBG_UART_RTS
DBG_UART_CTSBTP11
BTP12
VDD_IO
00
RF_OUT
DEPOPDEPOPDEPOPDEPOP
GND GND GND GND
*0ohm and DEPOP are for initial evaluation.
Please make sure to tune "Antenna matching" and "PI-network attenuator
PI-network attenuator Antenna matching
RF line
X'tal
PC15/OSC32_OUT
PC14/OSC32_IN
0ohm
32.768kHz
GNDGND
VDD_IO
GND
0.1uF
HOLD
WRITE
/CS
1
VCC
8
GND
4
/WP
3
DO
2
DI
5
CLK
6
/HOLDor/RESET
7
W25Q32JVSSIQ
MEM_SPI_SCK
MEM_TX_MOSI
MEM_RX_MISO
MEM_SPI_NSS
100k 100k
TP7
TP6 TP5
TP4
TTP2
GND
TP1
TP10
TTP1
I2C1_SDA
GND GND
0.1uF
NC1
1
EP
9
VCC
5
GND
4
NC3
3
NC2
2
SDA
8
SCL
7
NC7
6
AFERO-HSM
I2C1_SCL
1.8k1.8k
VDD_IO
Afero HSM
RESET_B
BTP1
GND
Flash & Flash Programming
Debug & Programming
Power Supply
VDD_WLAN
VDDA_MCU
VDD_IO
VBAT_MCU
VCC_3V3
© Afero 2018 – Version 1.2 - D-LIT-00054-00 Afero Proprietary and Confidential Information - 4
Afero Tech Note – Integrating the Murata Wi-Fi+BLE Module
2.3 Winbond Serial Flash Afero uses serial flash to execute the code directly from Dual/Quad SPI Flash. This is also used to store data shadowing the contents of the RAM. The flash is a critical component for Over-the-Air (OTA) updates; for an Afero OTA to work, we need a flash, such as the one mentioned directly below (W25Q32JVSSIQ).
The SPI Flash array is organized into 16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase), or the entire chip (chip erase).
For more information, please read the Winbond W25Q32JV SPI Flash Data Sheet: https://www.winbond.com/resource-files/w25q32jv%20spi%20revc%2008302016.pdf
Note: Afero firmware uses certain sets of pins for SPI, I2C, and debug UART. We expect our customers to use the same design as this would immensely minimize firmware customization needs. Please request a schematic and schematic review by submitting a JIRA ticket to the Afero Customer Enablement (ACE) team.
3. Antenna Design RecommendationsIf customers want to leverage Murata’s regulatory filings, customers need to follow the recommended antenna layout that Murata calls out in the 1LD datasheet. If that antenna does not work for the customer application, please consult with Murata for assistance.
In general, the following design recommendations are good best practices when not following specific recommendations from a manufacturer:
• Antenna impedance should be as close as possible to 50 ohm and have a return loss of -10dB orbetter.
• Place a Pi network placeholder on the RF trace during the first build. Once boards are available andmatching is done, remove the unwanted matching components to reduce BOM cost.
• Measure antenna gain on the actual design to confirm it fits with Murata’s filings.
© Afero 2018 – Version 1.2 - D-LIT-00054-00 Afero Proprietary and Confidential Information - 5
Afero Tech Note – Integrating the Murata Wi-Fi+BLE Module
4. Programming the Murata ModuleCreating a programming port to this module is essential during development and production. We use Segger J-link to flash a firmware image to the Murata module. For details on programming the module, please refer to the Product Specification, “Afero Factory Programmer, Cypress WICED Based Modules, Equipment and Setup”, PN D-SPC-00007-00. Please contact Afero for a copy of the specification.
Consider the following for mass production:
• You may decide to expose programming pins on an internal circuit board, or on the outside of yourproduct’s enclosure. Your final design should consider the overall cost of production and the servicelife of the product.
• The method of programming mentioned above does take some time and is slower. For massproduction, programming the SPI flash and MCU in parallel greatly reduces the time but addssignificant complexity as it requires more test points and two SEGGER J-Links. Once the product isready for production, refer to the “Afero Factory Programmer, Cypress WICED Based Modules,Equipment and Setup” specification referenced above.
5. FCC CertificationRadio Frequency (RF) devices are required to be properly authorized under 47 CFR part 2 prior to being marketed or imported into the United States. The Office of Engineering and Technology (OET) administers the equipment authorization program. This program is one of the principal ways the Commission ensures that RF devices used in the United States operate effectively without causing harmful interference and otherwise comply with the Commission’s rules. All RF devices subject to equipment authorization must comply with the Commission’s technical requirements prior to importation or marketing.
For information on FCC certification steps, go to: https://www.fcc.gov/engineering-technology/laboratory-division/general/equipment-authorization
Other regions have their own regulatory requirements. Please check with your Regulatory and Compliance Engineer for direction on meeting these requirements.
Murata’s 1LD Wi-Fi/BLE module has FCC-approval and other regulatory certifications for their reference and antenna design. For more information, contact Murata via https://afero.io/murata-contact.
6. Key Components List
DESCRIPTION MANUFACTURER VALUE QTY SUPPLIER PART #
SUPPLIER INFO
Afero specific Microchip CryptoAuthentication Security Module
Microchip I2C 1 ATECC508A-MAHKN
Afero
Bluetooth low energy (BLE) + Wi-Fi combo Module
Murata IC 1 LBEE5PA1LD Murata
SPI flash memory Winbond SPI 1 W25Q32JVSSIQ Digi-Key