agenda - university of california, berkeleycs61c/fa10/lectures/09...instr7 if& id& alu mem...

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CS 61C: Great Ideas in Computer Architecture (Machine Structures)

Instructors: Randy H. Katz

David A. PaHerson hHp://inst.eecs.Berkeley.edu/~cs61c/fa10

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Agenda

•  InstrucTon Stages Revisited •  Administrivia

•  Technology Break •  Rise of the Warehouse-‐Scale Computer

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Agenda

•  InstrucTon Stages Revisited •  Administrivia


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InstrucTon Level Parallelism

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P 1

Instr 1 IF ID ALU MEM WR

P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 9 P 10 P 11 P 12

Instr 2 IF ID ALU MEM WR IF ID ALU MEM WR Instr 2

Instr 3 IF ID ALU MEM WR

IF ID ALU MEM WR Instr 4





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Conceptual MIPS Datapath

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Stages of the Datapath (1/5)

•  There is a wide variety of MIPS instrucTons: so what general steps do they have in common?

•  Stage 1: Instruc(on Fetch – No maHer what the instrucTon, the 32-‐bit instrucTon word must first be fetched from memory (the cache-‐memory hierarchy)

– Also, this is where we Increment PC (that is, PC = PC + 4, to point to the next instrucTon: byte addressing so + 4)

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•  Stage 2: Instruc(on Decode – Upon fetching the instrucTon, we next gather data from the fields (decode all necessary instrucTon data)

– First, read the opcode to determine instrucTon type and field lengths

– Second, read in data from all necessary registers •  For add, read two registers •  For addi, read one register •  For jal, no reads necessary

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•  Stage 3: ALU (ArithmeTc-‐Logic Unit) – Real work of most instrucTons is done here: arithmeTc (+, -‐, *, /), shihing, logic (&, |), comparisons (slt)

– What about loads and stores? •  lw $t0, 40($t1) •  Address we are accessing in memory = the value in $t1 PLUS the value 40

•  So we do this addiTon in this stage

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•  Stage 4: Memory Access – Actually only the load and store instrucTons do anything during this phase; the others remain idle during this phase or skip it all together

– Since these instrucTons have a unique step, we need this extra phase to account for them

– As a result of the cache system, this phase is expected to be fast

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•  Stage 5: Register Write – Most instrucTons write the result of some computaTon into a register

– E.g.,: arithmeTc, logical, shihs, loads, slt

– What about stores, branches, jumps? •  Don’t write anything into a register at the end •  These remain idle during this fihh phase or skip it all together

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Limits to Performance: Latency vs. Bandwidth

•  Latency: the Tme to access first item

•  Bandwidth: # of items accessed per unit Tme

•  Historically, bandwidth has improved much faster than latency

•  Why?

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Bandwidth improves faster than latency

Latency improves faster than bandwidth

Latency vs. Bandwidth: Physical Analogy

•  Time to first drop

•  Time to fill glass •  Water per Tme

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Water Tank

Glass Glass Glass Length and diameter of pipes affects

latency and bandwidth

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Latency vs. Bandwidth: Which is “Faster”?

•  SD SF, 1 Truck, 10 hours, 1000 by 1 TByte Disks (1 PByte) – Time to first byte: – Time to last byte: – Bandwidth:

•  SDSF, 100 gbps fiber link (10 GB per sec) – Time to first byte: – Time to last byte: – Bandwidth:

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Latency vs. Bandwidth: Which is “Faster”?

•  SD SF, 1 Truck, 10 hours, 1000 by 1 TByte Disks (1 PByte) –  Time to first byte: 10 hours –  Time to last byte: 10 hours

–  Bandwidth: 100 TBytes/hr (222 Gbps) •  SDSF, 100 Gbps fiber link (10 GB per sec)

–  Time to first byte: 2.6 ms (speed of light @ 500 mi!) –  Time to last byte: 28 hours –  Bandwidth: 10 GB/s

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Agenda

•  Stages of an InstrucTon Revisited •  Administrivia


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Administrivia

•  Due dates for Project 2/First Part (Saturday, 18 September) and Project 2/Second Part (Saturday, 25 September) are @23:59:59

•  Midterm ExaminaTon, 6 October, 6-‐9 PM, 1 Pimentel

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Agenda


•  Technology Break •  Rise of Warehouse-‐Scale Computers

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Agenda


•  Technology Break •  Rise of Warehouse-‐Scale Computers

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Growth in Access Devices

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The ARM Inside the iPhone

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iPhone Innards

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1 GHz ARM Cortex A8

E.g., Google’s Oregon Datacenter

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Energy ProporTonal CompuTng

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Figure 1. Average CPU uTlizaTon of more than 5,000 servers during a six-‐month period. Servers are rarely completely idle and seldom operate near their maximum uTlizaTon, instead operaTng most of the Tme at between 10 and 50 percent of their maximum

It is surprisingly hard to achieve high levels of uTlizaTon of typical servers (and your home PC or laptop is even worse)

“The Case for Energy-‐ProporTonal CompuTng,” Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007

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Figure 2. Server power usage and energy efficiency at varying uTlizaTon levels, from idle to peak performance. Even an energy-‐efficient server sTll consumes about half its full power when doing virtually no work.

“The Case for Energy-‐ProporTonal CompuTng,” Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007 Doing nothing well …

NOT!

Energy Efficiency = UTlizaTon/Power

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26 Figure 3. CPU contribuTon to total server power for two generaTons of Google servers at peak performance (the first two bars) and for the later generaTon at idle (the rightmost bar).


CPU energy improves, but what about the rest of the server architecture?

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Figure 4. Power usage and energy efficiency in a more energy-‐proporTonal server. This server has a power efficiency of more than 80 percent of its peak value for uTlizaTons of 30 percent and above, with efficiency remaining above 50 percent for uTlizaTon levels as low as 10 percent.


Design for wide dynamic power range and ac(ve low power modes

Doing nothing VERY well

Energy Efficiency = UTlizaTon/Power

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Energy Use In Datacenters

LBNL Michael PaHerson, Intel

Datacenter Energy Overheads

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Datacenter Power

Peak Power %

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Nameplate vs. Actual Peak

X. Fan, W-‐D Weber, L. Barroso, “Power Provisioning for a Warehouse-‐sized Computer,” ISCA’07, San Diego, (June 2007).

Component CPU Memory Disk PCI Slots Mother Board Fan System Total

Peak Power 40 W 9 W 12 W 25 W 25 W 10 W

Count 2 4 1 2 1 1

Total 80 W 36 W 12 W 50 W 25 W 10 W 213 W

Nameplate peak 145 W Measured Peak

(Power-‐intensive workload) In Google’s world, for given DC power budget, deploy as many machines as possible

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Server Innards

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Server Internals

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Server Internals

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Google Server

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Summary

•  Five Stages/Phases of an InstrucTon –  InstrucTon Fetch (IF) –  InstrucTon Decode (ID) –  Execute (ALU) –  Memory (MEM) –  Write Results (WR)

•  Bandwidth vs. Latency –  Easier to increase bandwidth than reduce latency

•  Rise of the Warehouse-‐Scale Computer –  Energy ProporTonal CompuTng

•  Power (WaHs), Energy (Power x Time, WaH-‐hours) •  Subject to responsiveness goals, drive nodes to higher uTlizaTon to achieve beHer energy efficiency

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agenda - university of california, berkeleycs61c/fa10/lectures/09...instr7 if& id& alu mem...

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