Faculty of Engineering

ENEL 384 Midterm 2November 2, 201250 minutes50 marksStudent Name: _______________________________Student ID: _______________________________

This is a closed book exam, one crib sheet is allowed.

No electronics, other than the Faculty approved calculator permitted.

Please do not begin the test until instructed to do so.

Short answer questions – 1 mark each – except where noted.

1. What are three advantages of implementing digital logic designs in CPLD’s versus discrete logic?

Fewer parts, smaller amount of printed circuit board required and you can simulate your design.

2. What does term concurrency mean with respect to CPLD hardware?Outputs change at the same time.

3. Convert 841 to binary to BCD. Show your work.

binary 1101001001 BCD 1000 0100 0001 841 = 512 + 256 + 64 + 8 + 1 8 4 1

4. What is the valid range of numbers for an unsigned 8 bit binary and a signed 8 bit binary value? (2 marks)

Unsigned 2^n -1 = 255Signed means sign plus 7 magnitude bits, so -2^n<= x <= 2^n -1 so, -128 <= x <= +127

5. Convert −37 to 2’s complement in 8 bit signed representation. Show your work.

37 = 32 + 4 + 1 so 001001011’s complement 110110102’s complement 11011011

6. When is a pull up resistor required in a digital network?When we have a digital (or gpio) input that would otherwise befloating.

7. What are the advantages of the HC logic family over TTL?Lower power dissipation, unused gates can have inputs configuredIn any arrangement (LL0 or LL1). Works with a wider range of Vcc.

8. What’s the main advantage of using 2’s complement arithmetic in logic circuits?2’s complement arithmetic means we can use the same hardware to addition and subtraction – we just need to add inverters and use C0 (carry in) to invert the bits and add one.

9. What’s the difference between a decoder and a de-multiplexer?A decoder connects the selected output to Vcc, while a de-multiplexer connects an input bit stream to the selected output. Figure 6.45 in the text.

2

Design and Analysis Questions – 8 marks each

Question 10. Design a 2-Bit Parallel Binary Adder using only the parts included at the end of the exam.

The Boolean expressions for Sum and Cout are given as:

Σ=(A⊕B)⊕Cin and C out= (A⊕B )Cin+AB

Complete the following tasks:a) Derive the truth table for a Full Adder circuit. Explain how you found the

values for Σ (Sum) and Cout for each line of the truth table.b) Implement your design using only gates available on the last page of the

exam.c) Complete a build ready drawing with reference designators, pin numbers,

Vcc and ground, etc.

Account for unused gates in each package.

Reference DesignatorsU1 74HC86 Quad 2 input XOR Vcc 14 Gnd 7U2 74HC08 Quad 2 input AND Vcc 14 Gnd 7U3 74HC32Quad 2 input OR Vcc14 Gnd 7

Unused gates: U3C and U3C, both HC, so just ground the input pins.

3

Question 11

The inputs of this system A and B represent one binary number in the range 0..3. The inputs C and D represent a second binary number (also in the range 0..3). There are three outputs, X, Y and Z.Complete a truth table such that Y and Z represent a number equal to the magnitude of the difference of the two inputs, and X is 1 if and only if the first is larger.

Design the logic to implement just the X output of the circuit. Just logic gates are required – no chip designators, pin numbers etc. Use any gate configuration required, and assume all inputs are available in true and complemented forms.

A B C D X Y Z0 0 0 0 0 0 00 0 0 1 0 0 10 0 1 0 0 1 00 0 1 1 0 1 10 1 0 0 1 0 10 1 0 1 0 0 00 1 1 0 0 0 10 1 1 1 0 1 01 0 0 0 1 1 01 0 0 1 1 0 11 0 1 0 0 0 01 0 1 1 0 0 11 1 0 0 1 1 11 1 0 1 1 1 01 1 1 0 1 0 11 1 1 1 0 0 0

X=BC’D’+ABD’+AC’

4

Question 12The inputs to the logic circuit shown below are in state 1, then change to state 2, then to state 3 and finally to state 4.

A B CState 1

0 0 1

State 2

1 0 1

State 3

0 0 1

State 4

0 0 0

Calculate the maximum time it takes for the output, Z to change when the inputs change from state 1 to state 2, state 2 to state 3, and state 3 to state 4. Show your work.

Propagation Delays of 74ASL Gates74ALS0

074ALS02 74ALS0

874ALS32

tpLH 11ns 12ns 14ns 14nstpHL 8ns 10ns 10ns 12ns

Z

5

X is the output of the NOR gate.

State A B C A+B (A+B)' C' X X' C' Z Trans Trans tp(NOR) tp(NAND)1 0 0 1 0 1 0 1 0 0 0 at X at Z 74HC02 74HC002 1 0 1 1 0 0 0 1 0 1 1 -> 0 0 -> 1 tpHL tpLH3 0 0 1 0 1 0 1 0 0 0 0 -> 1 1 -> 0 tpLH tpHL4 0 0 0 0 1 1 1 0 1 1 1 -> 1 0 -> 1 N/C tpLH

Worst case transition timesState 1 to state 2 = tpHL(NOR) + tpLH(NAND) = 10ns + 11ns = 21 nsState 2 to state 3 = tpLH(NOR) + tpHL(NAND) = 12ns + 8ns = 20 nsState 3 to state 4 = nil (no change) + tpLH(NAND) = 0ns + 11ns = 11ns

6

Question 13Calculate the maximum power dissipation for a logic gate network consisting of 16 NAND gates (four integrated circuit chips with four gates each). Driving the logic gate network is a 1MHz clock with 25% duty cycle. All gates are driving a load (another NAND gate). Vcc is 5 volts.

Calculate power dissipated using 74LS00 NAND gates.

Calculate power dissipation using 74HC00 NAND gates.

7

Question 14The following data and parity bits are transmitted four times: ABP = 111. Data and parity are checked by the circuit shown in the figure below.

Parity generator and checker.

a) State the type of parity used.b) The transmission line over which the data are transmitted is analogue; it’s

old and noisy. The data arrive differently each time as follows:1. ABP = 1102. ABP = 1013. ABP = 1004. ABP = 111

Indicate the output P’ of the parity checker for each case and state what the output means.

Solution:

This is odd parity, since P = A XNOR B.In the table below, Rx P’ = Rx P XOR (A XNOR B); if P’ = 1, an error has occurred.

Tx Rx Rx Rx Rx RxABP ABP A XOR B A XNOR B P P’ Result111 110 0 1 0 1 Rx error on P bit111 101 1 0 1 1 Rx error on B bit111 100 1 0 0 0 Undetected errors, B and P111 111 0 1 1 0 OK, no error detected

First transmission, 110 received, since P’ = 1 an error has occurred, here, the B bit is in error.Second transmission 101 received, since P’ = 1 an error has occurred, here, the P bit is in error.Third transmission 100 received, this time P’ = 0, but this is because two transmission errors have occurred, both the B and P bits are inverted.Fourth transmission 111 received, P’ = 0 so no transmission error has occurred.

8

9